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GET /api/patches/807586/?format=api
{ "id": 807586, "url": "http://patchwork.ozlabs.org/api/patches/807586/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504091375-116149-1-git-send-email-liudongdong3@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504091375-116149-1-git-send-email-liudongdong3@huawei.com>", "list_archive_url": null, "date": "2017-08-30T11:09:35", "name": "[V2] PCI/portdrv: Fix MSI/MSI-X bug for PCIe port service drivers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "3f771cb28c209157b0b94904d9f4429c426c0def", "submitter": { "id": 67753, "url": "http://patchwork.ozlabs.org/api/people/67753/?format=api", "name": "Dongdong Liu", "email": "liudongdong3@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504091375-116149-1-git-send-email-liudongdong3@huawei.com/mbox/", "series": [ { "id": 585, "url": "http://patchwork.ozlabs.org/api/series/585/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=585", "date": "2017-08-30T11:09:35", "name": "[V2] PCI/portdrv: Fix MSI/MSI-X bug for PCIe port service drivers", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/585/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807586/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807586/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj2BH4kKdz9t2W\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 20:41:59 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751302AbdH3Kl4 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 30 Aug 2017 06:41:56 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:5494 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751186AbdH3Klz (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Wed, 30 Aug 2017 06:41:55 -0400", "from 172.30.72.60 (EHLO DGGEMS412-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGE64551; Wed, 30 Aug 2017 18:41:53 +0800 (CST)", "from linux-ioko.site (10.71.200.31) by\n\tDGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP\n\tServer id 14.3.301.0; Wed, 30 Aug 2017 18:41:45 +0800" ], "From": "Dongdong Liu <liudongdong3@huawei.com>", "To": "<helgaas@kernel.org>", "CC": "<linux-pci@vger.kernel.org>, <stable@vger.kernel.org>,\n\t<gabriele.paoloni@huawei.com>, <charles.chenxin@huawei.com>,\n\t<linuxarm@huawei.com>, Dongdong Liu <liudongdong3@huawei.com>", "Subject": "[PATCH V2] PCI/portdrv: Fix MSI/MSI-X bug for PCIe port service\n\tdrivers", "Date": "Wed, 30 Aug 2017 19:09:35 +0800", "Message-ID": "<1504091375-116149-1-git-send-email-liudongdong3@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.71.200.31]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A020201.59A69672.0008, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "da38eaa116e524e9689ab80a989b06c2", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Current code is broken as calling pci_free_irq_vectors()\ninvalidates the IRQ numbers returned before by pci_irq_vectors();\nso we need to move all the assignment of the Linux IRQ numbers at\nthe bottom of the function.\n\nAfter removing and adding back the PCI root port device,\nwe see the PCIe port service drivers request irq failed.\n\npcie_pme: probe of 0000:00:00.0:pcie001 failed with error -22\naer: probe of 0000:00:00.0:pcie002 failed with error -22\npciehp 0000:00:00.0:pcie004: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd-\nPwrInd- HotPlug+ Surprise+ Interlock- NoCompl- LLActRep+\npciehp 0000:00:00.0:pcie004: Cannot get irq 20 for the hotplug controller\npciehp 0000:00:00.0:pcie004: Notification initialization failed (-1)\ndpc 0000:00:00.0:pcie010: request IRQ22 failed: -22\ndpc: probe of 0000:00:00.0:pcie010 failed with error -22\n\nCc: <stable@vger.kernel.org>\nFixes: 3674cc4 (\"PCI/portdrv: Use pci_irq_alloc_vectors()\")\nSigned-off-by: Dongdong Liu <liudongdong3@huawei.com>\nSigned-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>\n---\nv1->v2:\n- Fix comments on PATCH v1.\n- Simplify implementation.\n---\n drivers/pci/pcie/portdrv_core.c | 17 ++++++++++++-----\n 1 file changed, 12 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c\nindex 313a21d..89f4cf5 100644\n--- a/drivers/pci/pcie/portdrv_core.c\n+++ b/drivers/pci/pcie/portdrv_core.c\n@@ -55,7 +55,8 @@ static void release_pcie_device(struct device *dev)\n static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n {\n \tint nr_entries, entry, nvec = 0;\n-\n+\tint i;\n+\tint idx[PCIE_PORT_DEVICE_MAXSERVICES];\n \t/*\n \t * Allocate as many entries as the port wants, so that we can check\n \t * which of them will be useful. Moreover, if nr_entries is correctly\n@@ -67,6 +68,9 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \tif (nr_entries < 0)\n \t\treturn nr_entries;\n \n+\tfor (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)\n+\t\tidx[i] = -1;\n+\n \tif (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {\n \t\tu16 reg16;\n \n@@ -90,8 +94,8 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\tif (entry >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);\n-\t\tirqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);\n+\t\tidx[PCIE_PORT_SERVICE_PME_SHIFT] = entry;\n+\t\tidx[PCIE_PORT_SERVICE_HP_SHIFT] = entry;\n \n \t\tnvec = max(nvec, entry + 1);\n \t}\n@@ -118,7 +122,7 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\tif (entry >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);\n+\t\tidx[PCIE_PORT_SERVICE_AER_SHIFT] = entry;\n \n \t\tnvec = max(nvec, entry + 1);\n \t}\n@@ -145,7 +149,7 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\tif (entry >= nr_entries)\n \t\t\tgoto out_free_irqs;\n \n-\t\tirqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry);\n+\t\tidx[PCIE_PORT_SERVICE_DPC_SHIFT] = entry;\n \n \t\tnvec = max(nvec, entry + 1);\n \t}\n@@ -166,6 +170,9 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)\n \t\t\treturn nr_entries;\n \t}\n \n+\tfor (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)\n+\t\tirqs[i] = idx[i] >= 0 ? pci_irq_vector(dev, idx[i]) : -1;\n+\n \treturn 0;\n \n out_free_irqs:\n", "prefixes": [ "V2" ] }