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GET /api/patches/807578/?format=api
{ "id": 807578, "url": "http://patchwork.ozlabs.org/api/patches/807578/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1504088771-6255-1-git-send-email-jaswinder.singh@linaro.org/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504088771-6255-1-git-send-email-jaswinder.singh@linaro.org>", "list_archive_url": null, "date": "2017-08-30T10:26:11", "name": "[net-next,PATCHv6,2/2] net: socionext: Add NetSec driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "acfcd9f6023af484936f650bba0e166132b9102e", "submitter": { "id": 4220, "url": "http://patchwork.ozlabs.org/api/people/4220/?format=api", "name": "Jassi Brar", "email": "jassisinghbrar@gmail.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1504088771-6255-1-git-send-email-jaswinder.singh@linaro.org/mbox/", "series": [ { "id": 577, "url": "http://patchwork.ozlabs.org/api/series/577/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=577", "date": "2017-08-30T10:24:17", "name": "net: ethernet: Socionext Netsec", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/577/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807578/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807578/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"I2Z4NVfI\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj1rK71TLz9t2R\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 20:26:25 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751484AbdH3K0Y (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tWed, 30 Aug 2017 06:26:24 -0400", "from mail-pf0-f193.google.com ([209.85.192.193]:34724 \"EHLO\n\tmail-pf0-f193.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751300AbdH3K0W (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Wed, 30 Aug 2017 06:26:22 -0400", "by mail-pf0-f193.google.com with SMTP id p69so4063188pfk.1;\n\tWed, 30 Aug 2017 03:26:22 -0700 (PDT)", "from localhost.localdomain ([27.255.192.36])\n\tby smtp.gmail.com with ESMTPSA id\n\tw24sm10085884pfl.80.2017.08.30.03.26.16\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 30 Aug 2017 03:26:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=2MOxWTdbLZvNlHmtCln5DxBhyp6zobrwm0b422WFvxY=;\n\tb=I2Z4NVfIrSWTlqKcmMyxKIZ5i6juin6hh0AoKDWpski8lHQ/+jSR1JtPZOLlrJ2qUW\n\tGPIcYeDNE5L8ywnGDtuoFCF0TDjL4CUkM5NkYJ9DPpulk8X/JNb2g68jr+4CkT7i5wCt\n\te8hucBbElFxf08FBFDGFJZJ3Y2BENBnBNOvW/4+N3I8mhNNUti5Ms0OD7D2XHpQdgmjf\n\tdSEWHXC74XOuhApIqJP8gq3A8dF9O4HjwUjjMW1MdpQko+V31Ym4e7fCt6G4/XPXqJlu\n\t01P5VY5st5JnWpKDT0K0jWtV1QJ+jpIMkYM0n3F2BbBHGwru0NNydmx36mmpAWuj/l2i\n\t/H1w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=2MOxWTdbLZvNlHmtCln5DxBhyp6zobrwm0b422WFvxY=;\n\tb=I/3S3i5vm0i2VsrJNYYGdtT4dOCsop/pYbsG85ZgXz4zanUVjCSSYmY2+sUzx5fxRp\n\tLceEq53O8O/ZH3we+0mPT36/nMStaoxGhTTeLvC3DlPfSGzOk3E80eOF0CIEPYEsGHy9\n\t5mBMWCzpeFjJ64KOL2SpfvenMakBwS0M96yHWEyrZFkAS8ukWXOR86Og+ITW25nvp09b\n\tVo1JcHtclZL4WLy8+n5Z7XsWkcaE6RjfoCTA5YCM7nzdTN6y+odGt+Dqs4Hd7oPRseol\n\tqavwJi+0sTdYtUVKtvq/hFLI9/o2AYd8X7Hy7VGL6ul6Yj4pI7wbOqpv7TKGruG10VP2\n\tgzGw==", "X-Gm-Message-State": "AHYfb5hyQz/fsHwoW+2Sn4JtpL47FEls8CZeCs0Mr4q9hF6I15sUnJSG\n\tFzG4T+byvcG53uUrbcQ=", "X-Received": "by 10.84.238.198 with SMTP id l6mr1326597pln.365.1504088780947; \n\tWed, 30 Aug 2017 03:26:20 -0700 (PDT)", "From": "Jassi Brar <jassisinghbrar@gmail.com>", "X-Google-Original-From": "Jassi Brar <jaswinder.singh@linaro.org>", "To": "netdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, davem@davemloft.net", "Cc": "patches@linaro.org, arnd@arndb.de, mark.rutland@arm.com,\n\trobh+dt@kernel.org, andy@warmcat.com,\n\tJassi Brar <jaswinder.singh@linaro.org>", "Subject": "[net-next PATCHv6 2/2] net: socionext: Add NetSec driver", "Date": "Wed, 30 Aug 2017 15:56:11 +0530", "Message-Id": "<1504088771-6255-1-git-send-email-jaswinder.singh@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504088657-6102-1-git-send-email-jaswinder.singh@linaro.org>", "References": "<1504088657-6102-1-git-send-email-jaswinder.singh@linaro.org>", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This driver adds support for Socionext \"netsec\" IP Gigabit\nEthernet + PHY IP used in a variety of their ARM-based ASICs.\n\nSigned-off-by: Jassi Brar <jaswinder.singh@linaro.org>\n---\n drivers/net/ethernet/Kconfig | 1 +\n drivers/net/ethernet/Makefile | 1 +\n drivers/net/ethernet/socionext/Kconfig | 29 +\n drivers/net/ethernet/socionext/Makefile | 1 +\n drivers/net/ethernet/socionext/netsec/Makefile | 6 +\n drivers/net/ethernet/socionext/netsec/netsec.h | 386 +++++++++++++\n .../socionext/netsec/netsec_desc_ring_access.c | 618 +++++++++++++++++++++\n .../net/ethernet/socionext/netsec/netsec_ethtool.c | 76 +++\n .../ethernet/socionext/netsec/netsec_gmac_access.c | 329 +++++++++++\n .../net/ethernet/socionext/netsec/netsec_netdev.c | 558 +++++++++++++++++++\n .../ethernet/socionext/netsec/netsec_platform.c | 330 +++++++++++\n 11 files changed, 2335 insertions(+)\n create mode 100644 drivers/net/ethernet/socionext/Kconfig\n create mode 100644 drivers/net/ethernet/socionext/Makefile\n create mode 100644 drivers/net/ethernet/socionext/netsec/Makefile\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec.h\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_ethtool.c\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_netdev.c\n create mode 100644 drivers/net/ethernet/socionext/netsec/netsec_platform.c", "diff": "diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig\nindex edae15ac..ef23120 100644\n--- a/drivers/net/ethernet/Kconfig\n+++ b/drivers/net/ethernet/Kconfig\n@@ -169,6 +169,7 @@ source \"drivers/net/ethernet/sis/Kconfig\"\n source \"drivers/net/ethernet/sfc/Kconfig\"\n source \"drivers/net/ethernet/sgi/Kconfig\"\n source \"drivers/net/ethernet/smsc/Kconfig\"\n+source \"drivers/net/ethernet/socionext/Kconfig\"\n source \"drivers/net/ethernet/stmicro/Kconfig\"\n source \"drivers/net/ethernet/sun/Kconfig\"\n source \"drivers/net/ethernet/tehuti/Kconfig\"\ndiff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile\nindex bf7f450..b2746b1 100644\n--- a/drivers/net/ethernet/Makefile\n+++ b/drivers/net/ethernet/Makefile\n@@ -80,6 +80,7 @@ obj-$(CONFIG_SFC) += sfc/\n obj-$(CONFIG_SFC_FALCON) += sfc/falcon/\n obj-$(CONFIG_NET_VENDOR_SGI) += sgi/\n obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/\n+obj-$(CONFIG_NET_VENDOR_SNI) += socionext/\n obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/\n obj-$(CONFIG_NET_VENDOR_SUN) += sun/\n obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/\ndiff --git a/drivers/net/ethernet/socionext/Kconfig b/drivers/net/ethernet/socionext/Kconfig\nnew file mode 100644\nindex 0000000..e2bcf90\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/Kconfig\n@@ -0,0 +1,29 @@\n+#\n+# Socionext Network device configuration\n+#\n+\n+config NET_VENDOR_SNI\n+\tbool \"Socionext devices\"\n+\tdefault y\n+\t---help---\n+\t If you have a network (Ethernet) card belonging to this class, say Y.\n+\n+\t Note that the answer to this question doesn't directly affect the\n+\t the questions about Socionext cards. If you say Y, you will be asked for\n+\t your specific card in the following questions.\n+\n+if NET_VENDOR_SNI\n+\n+config SNI_NETSEC\n+\ttristate \"NETSEC Driver Support\"\n+\tdepends on OF\n+\tselect PHYLIB\n+\tselect MII\n+help\n+\t Enable for NETSEC support of Socionext FGAMC4 IP\n+\t Provides Gigabit ethernet support\n+\n+\t To compile this driver as a module, choose M here: the module will be\n+\t called netsec. If unsure, say N.\n+\n+endif # NET_VENDOR_SNI\ndiff --git a/drivers/net/ethernet/socionext/Makefile b/drivers/net/ethernet/socionext/Makefile\nnew file mode 100644\nindex 0000000..9555899\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/Makefile\n@@ -0,0 +1 @@\n+obj-$(CONFIG_SNI_NETSEC) += netsec/\ndiff --git a/drivers/net/ethernet/socionext/netsec/Makefile b/drivers/net/ethernet/socionext/netsec/Makefile\nnew file mode 100644\nindex 0000000..42f6bab\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/Makefile\n@@ -0,0 +1,6 @@\n+obj-m := netsec.o\n+netsec-objs := netsec_desc_ring_access.o \\\n+\t\tnetsec_netdev.o \\\n+\t\tnetsec_ethtool.o \\\n+\t\tnetsec_platform.o \\\n+\t\tnetsec_gmac_access.o\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec.h b/drivers/net/ethernet/socionext/netsec/netsec.h\nnew file mode 100644\nindex 0000000..dadf5d9\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec.h\n@@ -0,0 +1,386 @@\n+/**\n+ * netsec.h\n+ *\n+ * Copyright (C) 2011 - 2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+#ifndef NETSEC_INTERNAL_H\n+#define NETSEC_INTERNAL_H\n+\n+#include <linux/netdevice.h>\n+#include <linux/types.h>\n+#include <linux/device.h>\n+#include <linux/phy.h>\n+#include <linux/ethtool.h>\n+#include <linux/of_address.h>\n+#include <linux/of_mdio.h>\n+#include <linux/etherdevice.h>\n+#include <net/sock.h>\n+\n+#define NETSEC_FLOW_CONTROL_START_THRESHOLD\t36\n+#define NETSEC_FLOW_CONTROL_STOP_THRESHOLD\t48\n+\n+#define NETSEC_CLK_MHZ\t\t\t\t1000000\n+\n+#define NETSEC_RX_PKT_BUF_LEN\t\t\t1522\n+#define NETSEC_RX_JUMBO_PKT_BUF_LEN\t\t9022\n+\n+#define NETSEC_NETDEV_TX_PKT_SCAT_NUM_MAX\t\t19\n+\n+#define DESC_NUM 128\n+\n+#define NETSEC_TX_SHIFT_OWN_FIELD\t\t\t31\n+#define NETSEC_TX_SHIFT_LD_FIELD\t\t\t30\n+#define NETSEC_TX_SHIFT_DRID_FIELD\t\t24\n+#define NETSEC_TX_SHIFT_PT_FIELD\t\t\t21\n+#define NETSEC_TX_SHIFT_TDRID_FIELD\t\t16\n+#define NETSEC_TX_SHIFT_CC_FIELD\t\t\t15\n+#define NETSEC_TX_SHIFT_FS_FIELD\t\t\t9\n+#define NETSEC_TX_LAST\t\t\t\t8\n+#define NETSEC_TX_SHIFT_CO\t\t\t7\n+#define NETSEC_TX_SHIFT_SO\t\t\t6\n+#define NETSEC_TX_SHIFT_TRS_FIELD\t\t4\n+\n+#define NETSEC_RX_PKT_OWN_FIELD\t\t\t31\n+#define NETSEC_RX_PKT_LD_FIELD\t\t\t30\n+#define NETSEC_RX_PKT_SDRID_FIELD\t\t\t24\n+#define NETSEC_RX_PKT_FR_FIELD\t\t\t23\n+#define NETSEC_RX_PKT_ER_FIELD\t\t\t21\n+#define NETSEC_RX_PKT_ERR_FIELD\t\t\t16\n+#define NETSEC_RX_PKT_TDRID_FIELD\t\t\t12\n+#define NETSEC_RX_PKT_FS_FIELD\t\t\t9\n+#define NETSEC_RX_PKT_LS_FIELD\t\t\t8\n+#define NETSEC_RX_PKT_CO_FIELD\t\t\t6\n+\n+#define NETSEC_RX_PKT_ERR_MASK\t\t\t3\n+\n+#define NETSEC_MAX_TX_PKT_LEN\t\t\t1518\n+#define NETSEC_MAX_TX_JUMBO_PKT_LEN\t\t9018\n+\n+enum netsec_rings {\n+\tNETSEC_RING_TX,\n+\tNETSEC_RING_RX\n+};\n+\n+#define NETSEC_RING_GMAC\t\t\t\t15\n+#define NETSEC_RING_MAX\t\t\t\t1\n+\n+#define NETSEC_TCP_SEG_LEN_MAX\t\t\t1460\n+#define NETSEC_TCP_JUMBO_SEG_LEN_MAX\t\t8960\n+\n+#define NETSEC_RX_CKSUM_NOTAVAIL\t\t\t0\n+#define NETSEC_RX_CKSUM_OK\t\t\t1\n+#define NETSEC_RX_CKSUM_NG\t\t\t2\n+\n+#define NETSEC_TOP_IRQ_REG_CODE_LOAD_END\t\tBIT(20)\n+#define NETSEC_IRQ_TRANSITION_COMPLETE\t\tBIT(4)\n+#define NETSEC_IRQ_RX\t\t\t\tBIT(1)\n+#define NETSEC_IRQ_TX\t\t\t\tBIT(0)\n+\n+#define NETSEC_IRQ_EMPTY\t\t\t\tBIT(17)\n+#define NETSEC_IRQ_ERR\t\t\t\tBIT(16)\n+#define NETSEC_IRQ_PKT_CNT\t\t\tBIT(15)\n+#define NETSEC_IRQ_TIMEUP\t\t\t\tBIT(14)\n+#define NETSEC_IRQ_RCV\t\t\t(NETSEC_IRQ_PKT_CNT | NETSEC_IRQ_TIMEUP)\n+\n+#define NETSEC_IRQ_TX_DONE\t\t\tBIT(15)\n+#define NETSEC_IRQ_SND\t\t\t(NETSEC_IRQ_TX_DONE | NETSEC_IRQ_TIMEUP)\n+\n+#define NETSEC_MODE_TRANS_COMP_IRQ_N2T\t\tBIT(20)\n+#define NETSEC_MODE_TRANS_COMP_IRQ_T2N\t\tBIT(19)\n+\n+#define NETSEC_DESC_MIN\t\t\t\t2\n+#define NETSEC_DESC_MAX\t\t\t\t2047\n+#define NETSEC_INT_PKTCNT_MAX\t\t\t2047\n+\n+#define NETSEC_FLOW_START_TH_MAX\t\t\t95\n+#define NETSEC_FLOW_STOP_TH_MAX\t\t\t95\n+#define NETSEC_FLOW_PAUSE_TIME_MIN\t\t5\n+\n+#define NETSEC_CLK_EN_REG_DOM_ALL\t\t\t0x3f\n+\n+#define NETSEC_REG_TOP_STATUS\t\t\t0x80\n+#define NETSEC_REG_TOP_INTEN\t\t\t0x81\n+#define NETSEC_REG_INTEN_SET\t\t\t0x8d\n+#define NETSEC_REG_INTEN_CLR\t\t\t0x8e\n+#define NETSEC_REG_NRM_TX_STATUS\t\t\t0x100\n+#define NETSEC_REG_NRM_TX_INTEN\t\t\t0x101\n+#define NETSEC_REG_NRM_TX_INTEN_SET\t\t0x10a\n+#define NETSEC_REG_NRM_TX_INTEN_CLR\t\t0x10b\n+#define NETSEC_REG_NRM_RX_STATUS\t\t\t0x110\n+#define NETSEC_REG_NRM_RX_INTEN\t\t\t0x111\n+#define NETSEC_REG_NRM_RX_INTEN_SET\t\t0x11a\n+#define NETSEC_REG_NRM_RX_INTEN_CLR\t\t0x11b\n+#define NETSEC_REG_RESERVED_RX_DESC_START\t\t0x122\n+#define NETSEC_REG_RESERVED_TX_DESC_START\t\t0x132\n+#define NETSEC_REG_CLK_EN\t\t\t\t0x40\n+#define NETSEC_REG_SOFT_RST\t\t\t0x41\n+#define NETSEC_REG_PKT_CTRL\t\t\t0x50\n+#define NETSEC_REG_COM_INIT\t\t\t0x48\n+#define NETSEC_REG_DMA_TMR_CTRL\t\t\t0x83\n+#define NETSEC_REG_F_TAIKI_MC_VER\t\t\t0x8b\n+#define NETSEC_REG_F_TAIKI_VER\t\t\t0x8c\n+#define NETSEC_REG_DMA_HM_CTRL\t\t\t0x85\n+#define NETSEC_REG_DMA_MH_CTRL\t\t\t0x88\n+#define NETSEC_REG_NRM_TX_PKTCNT\t\t\t0x104\n+#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT\t0x106\n+#define NETSEC_REG_NRM_RX_RXINT_PKTCNT\t\t0x116\n+#define NETSEC_REG_NRM_TX_TXINT_TMR\t\t0x108\n+#define NETSEC_REG_NRM_RX_RXINT_TMR\t\t0x118\n+#define NETSEC_REG_NRM_TX_DONE_PKTCNT\t\t0x105\n+#define NETSEC_REG_NRM_RX_PKTCNT\t\t\t0x115\n+#define NETSEC_REG_NRM_TX_TMR\t\t\t0x107\n+#define NETSEC_REG_NRM_RX_TMR\t\t\t0x117\n+#define NETSEC_REG_NRM_TX_DESC_START_UP\t\t0x10d\n+#define NETSEC_REG_NRM_TX_DESC_START_LW\t\t0x102\n+#define NETSEC_REG_NRM_RX_DESC_START_UP\t\t0x11d\n+#define NETSEC_REG_NRM_RX_DESC_START_LW\t\t0x112\n+#define NETSEC_REG_NRM_TX_CONFIG\t\t\t0x10c\n+#define NETSEC_REG_NRM_RX_CONFIG\t\t\t0x11c\n+#define MAC_REG_DATA\t\t\t\t0x470\n+#define MAC_REG_CMD\t\t\t\t0x471\n+#define MAC_REG_FLOW_TH\t\t\t\t0x473\n+#define MAC_REG_INTF_SEL\t\t\t0x475\n+#define MAC_REG_DESC_INIT\t\t\t0x47f\n+#define MAC_REG_DESC_SOFT_RST\t\t\t0x481\n+#define NETSEC_REG_MODE_TRANS_COMP_STATUS\t\t0x140\n+#define GMAC_REG_MCR\t\t\t\t0x0000\n+#define GMAC_REG_MFFR\t\t\t\t0x0004\n+#define GMAC_REG_GAR\t\t\t\t0x0010\n+#define GMAC_REG_GDR\t\t\t\t0x0014\n+#define GMAC_REG_FCR\t\t\t\t0x0018\n+#define GMAC_REG_BMR\t\t\t\t0x1000\n+#define GMAC_REG_RDLAR\t\t\t\t0x100c\n+#define GMAC_REG_TDLAR\t\t\t\t0x1010\n+#define GMAC_REG_OMR\t\t\t\t0x1018\n+\n+#define NETSEC_PKT_CTRL_REG_MODE_NRM\t\tBIT(28)\n+#define NETSEC_PKT_CTRL_REG_EN_JUMBO\t\tBIT(27)\n+#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER\t\tBIT(3)\n+#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE\tBIT(2)\n+#define NETSEC_PKT_CTRL_REG_LOG_HD_ER\t\tBIT(1)\n+#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH\t\tBIT(0)\n+\n+#define NETSEC_CLK_EN_REG_DOM_G\t\t\tBIT(5)\n+#define NETSEC_CLK_EN_REG_DOM_C\t\t\tBIT(1)\n+#define NETSEC_CLK_EN_REG_DOM_D\t\t\tBIT(0)\n+\n+#define NETSEC_COM_INIT_REG_PKT\t\t\tBIT(1)\n+#define NETSEC_COM_INIT_REG_CORE\t\t\tBIT(0)\n+\n+#define NETSEC_SOFT_RST_REG_RESET\t\t\t0\n+#define NETSEC_SOFT_RST_REG_RUN\t\t\tBIT(31)\n+\n+#define NETSEC_DMA_CTRL_REG_STOP\t\t\t1\n+#define MH_CTRL__MODE_TRANS\t\t\tBIT(20)\n+\n+#define NETSEC_GMAC_CMD_ST_READ\t\t\t0\n+#define NETSEC_GMAC_CMD_ST_WRITE\t\t\tBIT(28)\n+#define NETSEC_GMAC_CMD_ST_BUSY\t\t\tBIT(31)\n+\n+#define NETSEC_GMAC_BMR_REG_COMMON\t\t0x00412080\n+#define NETSEC_GMAC_BMR_REG_RESET\t\t\t0x00020181\n+#define NETSEC_GMAC_BMR_REG_SWR\t\t\t0x00000001\n+\n+#define NETSEC_GMAC_OMR_REG_ST\t\t\tBIT(13)\n+#define NETSEC_GMAC_OMR_REG_SR\t\t\tBIT(1)\n+\n+#define NETSEC_GMAC_MCR_REG_IBN\t\t\tBIT(30)\n+#define NETSEC_GMAC_MCR_REG_CST\t\t\tBIT(25)\n+#define NETSEC_GMAC_MCR_REG_JE\t\t\tBIT(20)\n+#define NETSEC_MCR_PS\t\t\t\tBIT(15)\n+#define NETSEC_GMAC_MCR_REG_FES\t\t\tBIT(14)\n+#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON\t0x0000280c\n+#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON\t0x0001a00c\n+\n+#define NETSEC_FCR_RFE\t\t\t\tBIT(2)\n+#define NETSEC_FCR_TFE\t\t\t\tBIT(1)\n+\n+#define NETSEC_GMAC_GAR_REG_GW\t\t\tBIT(1)\n+#define NETSEC_GMAC_GAR_REG_GB\t\t\tBIT(0)\n+\n+#define NETSEC_GMAC_GAR_REG_SHIFT_PA\t\t11\n+#define NETSEC_GMAC_GAR_REG_SHIFT_GR\t\t6\n+#define GMAC_REG_SHIFT_CR_GAR\t\t\t2\n+\n+#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ\t\t2\n+#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ\t\t3\n+#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ\t\t0\n+#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ\t1\n+#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ\t4\n+#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ\t5\n+\n+#define NETSEC_REG_NETSEC_VER_F_TAIKI\t\t0x50000\n+\n+#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP\tBIT(31)\n+#define NETSEC_REG_DESC_RING_CONFIG_CH_RST\tBIT(30)\n+#define NETSEC_REG_DESC_TMR_MODE\t\t4\n+#define NETSEC_REG_DESC_ENDIAN\t\t\t0\n+\n+#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST\t\t1\n+#define NETSEC_MAC_DESC_INIT_REG_INIT\t\t1\n+\n+/* this is used to interpret a register layout */\n+struct netsec_pkt_ctrlaram {\n+\tu8 log_chksum_er_flag:1;\n+\tu8 log_hd_imcomplete_flag:1;\n+\tu8 log_hd_er_flag:1;\n+};\n+\n+struct netsec_param {\n+\tstruct netsec_pkt_ctrlaram pkt_ctrlaram;\n+\tbool use_jumbo_pkt_flag;\n+};\n+\n+struct netsec_mac_mode {\n+\tu16 flow_start_th;\n+\tu16 flow_stop_th;\n+\tu16 pause_time;\n+\tbool flow_ctrl_enable_flag;\n+};\n+\n+struct netsec_desc_ring {\n+\tspinlock_t spinlock_desc; /* protect descriptor access */\n+\tphys_addr_t desc_phys;\n+\tstruct netsec_frag_info *frag;\n+\tstruct sk_buff **priv;\n+\tvoid *ring_vaddr;\n+\tenum netsec_rings id;\n+\tint len;\n+\tu16 tx_done_num;\n+\tu16 rx_num;\n+\tu16 head;\n+\tu16 tail;\n+\tbool running;\n+\tbool full;\n+};\n+\n+struct netsec_frag_info {\n+\tdma_addr_t dma_addr;\n+\tvoid *addr;\n+\tu16 len;\n+};\n+\n+struct netsec_priv {\n+\tstruct netsec_desc_ring desc_ring[NETSEC_RING_MAX + 1];\n+\tstruct ethtool_coalesce et_coalesce;\n+\tstruct netsec_mac_mode mac_mode;\n+\tstruct netsec_param param;\n+\tstruct napi_struct napi;\n+\tphys_addr_t rdlar_pa, tdlar_pa;\n+\tphy_interface_t phy_interface;\n+\tspinlock_t tx_queue_lock; /* protect transmit queue */\n+\tstruct netsec_frag_info tx_info[MAX_SKB_FRAGS];\n+\tstruct net_device *ndev;\n+\tstruct device_node *phy_np;\n+\tstruct mii_bus *mii_bus;\n+\tvoid __iomem *ioaddr;\n+\tstruct device *dev;\n+\tstruct clk *clk[3];\n+\tphys_addr_t scb_set_normal_tx_paddr;\n+\tu32 scb_pkt_ctrl_reg;\n+\tu32 rx_pkt_buf_len;\n+\tu32 msg_enable;\n+\tu32 freq;\n+\tint actual_link_speed;\n+\tint clock_count;\n+\tbool rx_cksum_offload_flag;\n+\tbool actual_duplex;\n+\tbool irq_registered;\n+};\n+\n+struct netsec_tx_de {\n+\tu32 attr;\n+\tu32 data_buf_addr_up;\n+\tu32 data_buf_addr_lw;\n+\tu32 buf_len_info;\n+};\n+\n+struct netsec_rx_de {\n+\tu32 attr;\n+\tu32 data_buf_addr_up;\n+\tu32 data_buf_addr_lw;\n+\tu32 buf_len_info;\n+};\n+\n+struct netsec_tx_pkt_ctrl {\n+\tu16 tcp_seg_len;\n+\tbool tcp_seg_offload_flag;\n+\tbool cksum_offload_flag;\n+};\n+\n+struct netsec_rx_pkt_info {\n+\tint rx_cksum_result;\n+\tint err_code;\n+\tbool is_fragmented;\n+\tbool err_flag;\n+};\n+\n+struct netsec_skb_cb {\n+\tbool is_rx;\n+};\n+\n+static inline void netsec_writel(struct netsec_priv *priv,\n+\t\t\t\t u32 reg_addr, u32 val)\n+{\n+\twritel_relaxed(val, priv->ioaddr + (reg_addr << 2));\n+}\n+\n+static inline u32 netsec_readl(struct netsec_priv *priv, u32 reg_addr)\n+{\n+\treturn readl_relaxed(priv->ioaddr + (reg_addr << 2));\n+}\n+\n+static inline void netsec_mark_skb_type(struct sk_buff *skb, bool is_rx)\n+{\n+\tstruct netsec_skb_cb *cb = (struct netsec_skb_cb *)skb->cb;\n+\n+\tcb->is_rx = is_rx;\n+}\n+\n+static inline bool skb_is_rx(struct sk_buff *skb)\n+{\n+\tstruct netsec_skb_cb *cb = (struct netsec_skb_cb *)skb->cb;\n+\n+\treturn cb->is_rx;\n+}\n+\n+extern const struct net_device_ops netsec_netdev_ops;\n+extern const struct ethtool_ops netsec_ethtool_ops;\n+\n+int netsec_start_gmac(struct netsec_priv *priv);\n+int netsec_stop_gmac(struct netsec_priv *priv);\n+int netsec_mii_register(struct netsec_priv *priv);\n+void netsec_mii_unregister(struct netsec_priv *priv);\n+int netsec_start_desc_ring(struct netsec_priv *priv, enum netsec_rings id);\n+void netsec_stop_desc_ring(struct netsec_priv *priv, enum netsec_rings id);\n+u16 netsec_get_rx_num(struct netsec_priv *priv);\n+u16 netsec_get_tx_avail_num(struct netsec_priv *priv);\n+int netsec_clean_tx_desc_ring(struct netsec_priv *priv);\n+int netsec_clean_rx_desc_ring(struct netsec_priv *priv);\n+int netsec_set_tx_pkt_data(struct netsec_priv *priv,\n+\t\t\t const struct netsec_tx_pkt_ctrl *tx_ctrl,\n+\t\t\t u8 count_frags, const struct netsec_frag_info *info,\n+\t\t\t struct sk_buff *skb);\n+int netsec_get_rx_pkt_data(struct netsec_priv *priv,\n+\t\t\t struct netsec_rx_pkt_info *rxpi,\n+\t\t\t struct netsec_frag_info *frag, u16 *len,\n+\t\t\t struct sk_buff **skb);\n+void netsec_ring_irq_enable(struct netsec_priv *priv,\n+\t\t\t enum netsec_rings id, u32 i);\n+void netsec_ring_irq_disable(struct netsec_priv *priv,\n+\t\t\t enum netsec_rings id, u32 i);\n+int netsec_alloc_desc_ring(struct netsec_priv *priv, enum netsec_rings id);\n+void netsec_free_desc_ring(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc);\n+int netsec_setup_rx_desc(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc);\n+int netsec_netdev_napi_poll(struct napi_struct *napi_p, int budget);\n+\n+#endif /* NETSEC_INTERNAL_H */\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c b/drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c\nnew file mode 100644\nindex 0000000..d8e23ca\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c\n@@ -0,0 +1,618 @@\n+/**\n+ * drivers/net/ethernet/socionext/netsec/netsec_desc_ring_access.c\n+ *\n+ * Copyright (C) 2011-2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+\n+#include <linux/spinlock.h>\n+#include <linux/dma-mapping.h>\n+\n+#include \"netsec.h\"\n+\n+static const u32 ads_irq_set[] = {\n+\tNETSEC_REG_NRM_TX_INTEN_SET,\n+\tNETSEC_REG_NRM_RX_INTEN_SET,\n+};\n+\n+static const u32 desc_ring_irq_inten_clr_reg_addr[] = {\n+\tNETSEC_REG_NRM_TX_INTEN_CLR,\n+\tNETSEC_REG_NRM_RX_INTEN_CLR,\n+};\n+\n+static const u32 int_tmr_reg_addr[] = {\n+\tNETSEC_REG_NRM_TX_TXINT_TMR,\n+\tNETSEC_REG_NRM_RX_RXINT_TMR,\n+};\n+\n+static const u32 rx_pkt_cnt_reg_addr[] = {\n+\t0,\n+\tNETSEC_REG_NRM_RX_PKTCNT,\n+};\n+\n+static const u32 tx_pkt_cnt_reg_addr[] = {\n+\tNETSEC_REG_NRM_TX_PKTCNT,\n+\t0,\n+};\n+\n+static const u32 int_pkt_cnt_reg_addr[] = {\n+\tNETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,\n+\tNETSEC_REG_NRM_RX_RXINT_PKTCNT,\n+};\n+\n+static const u32 tx_done_pkt_addr[] = {\n+\tNETSEC_REG_NRM_TX_DONE_PKTCNT,\n+\t0,\n+};\n+\n+static const u32 netsec_desc_mask[] = {\n+\t[NETSEC_RING_TX] = NETSEC_GMAC_OMR_REG_ST,\n+\t[NETSEC_RING_RX] = NETSEC_GMAC_OMR_REG_SR\n+};\n+\n+void netsec_ring_irq_enable(struct netsec_priv *priv,\n+\t\t\t enum netsec_rings id, u32 irqf)\n+{\n+\tnetsec_writel(priv, ads_irq_set[id], irqf);\n+}\n+\n+void netsec_ring_irq_disable(struct netsec_priv *priv,\n+\t\t\t enum netsec_rings id, u32 irqf)\n+{\n+\tnetsec_writel(priv, desc_ring_irq_inten_clr_reg_addr[id], irqf);\n+}\n+\n+static struct sk_buff *alloc_rx_pkt_buf(struct netsec_priv *priv,\n+\t\t\t\t\tstruct netsec_frag_info *info)\n+{\n+\tstruct sk_buff *skb;\n+\n+\tskb = netdev_alloc_skb_ip_align(priv->ndev, info->len);\n+\tif (!skb)\n+\t\treturn NULL;\n+\n+\tnetsec_mark_skb_type(skb, NETSEC_RING_RX);\n+\tinfo->addr = skb->data;\n+\tinfo->dma_addr = dma_map_single(priv->dev, info->addr, info->len,\n+\t\t\t\t\tDMA_FROM_DEVICE);\n+\tif (dma_mapping_error(priv->dev, info->dma_addr)) {\n+\t\tdev_kfree_skb(skb);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn skb;\n+}\n+\n+int netsec_alloc_desc_ring(struct netsec_priv *priv, enum netsec_rings id)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[id];\n+\tint ret = 0;\n+\n+\tdesc->id = id;\n+\tdesc->len = sizeof(struct netsec_tx_de); /* rx and tx desc same size */\n+\n+\tspin_lock_init(&desc->spinlock_desc);\n+\n+\tdesc->ring_vaddr = dma_zalloc_coherent(priv->dev, desc->len * DESC_NUM,\n+\t\t\t\t\t &desc->desc_phys, GFP_KERNEL);\n+\tif (!desc->ring_vaddr) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tdesc->frag = kcalloc(DESC_NUM, sizeof(*desc->frag), GFP_KERNEL);\n+\tif (!desc->frag) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tdesc->priv = kcalloc(DESC_NUM, sizeof(struct sk_buff *), GFP_KERNEL);\n+\tif (!desc->priv) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tnetsec_free_desc_ring(priv, desc);\n+\n+\treturn ret;\n+}\n+\n+static void netsec_uninit_pkt_desc_ring(struct netsec_priv *priv,\n+\t\t\t\t\tstruct netsec_desc_ring *desc)\n+{\n+\tstruct netsec_frag_info *frag;\n+\tu32 status;\n+\tu16 idx;\n+\n+\tfor (idx = 0; idx < DESC_NUM; idx++) {\n+\t\tfrag = &desc->frag[idx];\n+\t\tif (!frag->addr)\n+\t\t\tcontinue;\n+\n+\t\tstatus = *(u32 *)(desc->ring_vaddr + desc->len * idx);\n+\n+\t\tdma_unmap_single(priv->dev, frag->dma_addr, frag->len,\n+\t\t\t\t skb_is_rx(desc->priv[idx]) ? DMA_FROM_DEVICE :\n+\t\t\t\t\t\t\t DMA_TO_DEVICE);\n+\t\tif ((status >> NETSEC_TX_LAST) & 1)\n+\t\t\tdev_kfree_skb(desc->priv[idx]);\n+\t}\n+\n+\tmemset(desc->frag, 0, sizeof(struct netsec_frag_info) * DESC_NUM);\n+\tmemset(desc->priv, 0, sizeof(struct sk_buff *) * DESC_NUM);\n+\tmemset(desc->ring_vaddr, 0, desc->len * DESC_NUM);\n+}\n+\n+void netsec_free_desc_ring(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc)\n+{\n+\tif (desc->ring_vaddr && desc->frag && desc->priv)\n+\t\tnetsec_uninit_pkt_desc_ring(priv, desc);\n+\n+\tif (desc->ring_vaddr) {\n+\t\tdma_free_coherent(priv->dev, desc->len * DESC_NUM,\n+\t\t\t\t desc->ring_vaddr, desc->desc_phys);\n+\t\tdesc->ring_vaddr = NULL;\n+\t}\n+\tkfree(desc->frag);\n+\tdesc->frag = NULL;\n+\tkfree(desc->priv);\n+\tdesc->priv = NULL;\n+}\n+\n+static void netsec_set_rx_de(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc, u16 idx,\n+\t\t\t const struct netsec_frag_info *info,\n+\t\t\t struct sk_buff *skb)\n+{\n+\tstruct netsec_rx_de *de = desc->ring_vaddr + desc->len * idx;\n+\tu32 attr = 1 << NETSEC_RX_PKT_OWN_FIELD | 1 << NETSEC_RX_PKT_FS_FIELD |\n+\t\t\t 1 << NETSEC_RX_PKT_LS_FIELD;\n+\n+\tif (idx == DESC_NUM - 1)\n+\t\tattr |= 1 << NETSEC_RX_PKT_LD_FIELD;\n+\n+\tde->data_buf_addr_up = info->dma_addr >> 32;\n+\tde->data_buf_addr_lw = info->dma_addr & 0xffffffff;\n+\tde->buf_len_info = info->len;\n+\t/* desc->attr makes the descriptor live, so it must be physically\n+\t * written last after the rest of the descriptor body is already there\n+\t */\n+\twmb();\n+\tde->attr = attr;\n+\n+\tdesc->frag[idx].dma_addr = info->dma_addr;\n+\tdesc->frag[idx].addr = info->addr;\n+\tdesc->frag[idx].len = info->len;\n+\n+\tdesc->priv[idx] = skb;\n+}\n+\n+int netsec_setup_rx_desc(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc)\n+{\n+\tstruct netsec_frag_info info;\n+\tstruct sk_buff *skb;\n+\tint n;\n+\n+\tinfo.len = priv->rx_pkt_buf_len;\n+\n+\tfor (n = 0; n < DESC_NUM; n++) {\n+\t\tskb = alloc_rx_pkt_buf(priv, &info);\n+\t\tif (!skb) {\n+\t\t\tnetsec_uninit_pkt_desc_ring(priv, desc);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tnetsec_set_rx_de(priv, desc, n, &info, skb);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void netsec_set_tx_desc_entry(struct netsec_priv *priv,\n+\t\t\t\t struct netsec_desc_ring *desc,\n+\t\t\t\t const struct netsec_tx_pkt_ctrl *tx_ctrl,\n+\t\t\t\t bool first_flag, bool last_flag,\n+\t\t\t\t const struct netsec_frag_info *frag,\n+\t\t\t\t struct sk_buff *skb)\n+{\n+\tstruct netsec_tx_de tx_desc_entry;\n+\tint idx = desc->head;\n+\n+\tmemset(&tx_desc_entry, 0, sizeof(struct netsec_tx_de));\n+\n+\ttx_desc_entry.attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |\n+\t\t\t (desc->id << NETSEC_TX_SHIFT_DRID_FIELD) |\n+\t\t\t (1 << NETSEC_TX_SHIFT_PT_FIELD) |\n+\t\t\t (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |\n+\t\t\t (first_flag << NETSEC_TX_SHIFT_FS_FIELD) |\n+\t\t\t (last_flag << NETSEC_TX_LAST) |\n+\t\t\t (tx_ctrl->cksum_offload_flag <<\n+\t\t\t NETSEC_TX_SHIFT_CO) |\n+\t\t\t (tx_ctrl->tcp_seg_offload_flag <<\n+\t\t\t NETSEC_TX_SHIFT_SO) |\n+\t\t\t (1 << NETSEC_TX_SHIFT_TRS_FIELD);\n+\tif (idx == DESC_NUM - 1)\n+\t\ttx_desc_entry.attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);\n+\n+\ttx_desc_entry.data_buf_addr_up = frag->dma_addr >> 32;\n+\ttx_desc_entry.data_buf_addr_lw = frag->dma_addr & 0xffffffff;\n+\ttx_desc_entry.buf_len_info = (tx_ctrl->tcp_seg_len << 16) | frag->len;\n+\n+\tmemcpy(desc->ring_vaddr + (desc->len * idx), &tx_desc_entry, desc->len);\n+\n+\tdesc->frag[idx].dma_addr = frag->dma_addr;\n+\tdesc->frag[idx].addr = frag->addr;\n+\tdesc->frag[idx].len = frag->len;\n+\n+\tdesc->priv[idx] = skb;\n+}\n+\n+static void netsec_get_rx_de(struct netsec_priv *priv,\n+\t\t\t struct netsec_desc_ring *desc, u16 idx,\n+\t\t\t struct netsec_rx_pkt_info *rxpi,\n+\t\t\t struct netsec_frag_info *frag, u16 *len,\n+\t\t\t struct sk_buff **skb)\n+{\n+\tstruct netsec_rx_de de;\n+\n+\tmemset(&de, 0, sizeof(struct netsec_rx_de));\n+\tmemset(rxpi, 0, sizeof(struct netsec_rx_pkt_info));\n+\tmemcpy(&de, ((void *)desc->ring_vaddr + desc->len * idx), desc->len);\n+\n+\tdev_dbg(priv->dev, \"%08x\\n\", *(u32 *)&de);\n+\t*len = de.buf_len_info >> 16;\n+\n+\trxpi->is_fragmented = (de.attr >> NETSEC_RX_PKT_FR_FIELD) & 1;\n+\trxpi->err_flag = (de.attr >> NETSEC_RX_PKT_ER_FIELD) & 1;\n+\trxpi->rx_cksum_result = (de.attr >> NETSEC_RX_PKT_CO_FIELD) & 3;\n+\trxpi->err_code = (de.attr >> NETSEC_RX_PKT_ERR_FIELD) &\n+\t\t\t\t\t\t\tNETSEC_RX_PKT_ERR_MASK;\n+\tmemcpy(frag, &desc->frag[idx], sizeof(*frag));\n+\t*skb = desc->priv[idx];\n+}\n+\n+static void netsec_inc_desc_head_idx(struct netsec_priv *priv,\n+\t\t\t\t struct netsec_desc_ring *desc, u16 inc)\n+{\n+\tu32 sum;\n+\n+\tsum = desc->head + inc;\n+\n+\tif (sum >= DESC_NUM)\n+\t\tsum -= DESC_NUM;\n+\n+\tdesc->head = sum;\n+\tdesc->full = desc->head == desc->tail;\n+}\n+\n+static void netsec_inc_desc_tail_idx(struct netsec_priv *priv,\n+\t\t\t\t struct netsec_desc_ring *desc)\n+{\n+\tu32 sum;\n+\n+\tsum = desc->tail + 1;\n+\n+\tif (sum >= DESC_NUM)\n+\t\tsum -= DESC_NUM;\n+\n+\tdesc->tail = sum;\n+\tdesc->full = false;\n+}\n+\n+static u16 netsec_get_tx_avail_num_sub(struct netsec_priv *priv,\n+\t\t\t\t const struct netsec_desc_ring *desc)\n+{\n+\tif (desc->full)\n+\t\treturn 0;\n+\n+\tif (desc->tail > desc->head)\n+\t\treturn desc->tail - desc->head;\n+\n+\treturn DESC_NUM + desc->tail - desc->head;\n+}\n+\n+static u16 netsec_get_tx_done_num_sub(struct netsec_priv *priv,\n+\t\t\t\t struct netsec_desc_ring *desc)\n+{\n+\tdesc->tx_done_num += netsec_readl(priv, tx_done_pkt_addr[desc->id]);\n+\n+\treturn desc->tx_done_num;\n+}\n+\n+static int netsec_set_irq_coalesce_param(struct netsec_priv *priv,\n+\t\t\t\t\t enum netsec_rings id)\n+{\n+\tint max_frames, tmr;\n+\n+\tswitch (id) {\n+\tcase NETSEC_RING_TX:\n+\t\tmax_frames = priv->et_coalesce.tx_max_coalesced_frames;\n+\t\ttmr = priv->et_coalesce.tx_coalesce_usecs;\n+\t\tbreak;\n+\tcase NETSEC_RING_RX:\n+\t\tmax_frames = priv->et_coalesce.rx_max_coalesced_frames;\n+\t\ttmr = priv->et_coalesce.rx_coalesce_usecs;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tnetsec_writel(priv, int_pkt_cnt_reg_addr[id], max_frames);\n+\tnetsec_writel(priv, int_tmr_reg_addr[id], ((tmr != 0) << 31) | tmr);\n+\n+\treturn 0;\n+}\n+\n+int netsec_start_desc_ring(struct netsec_priv *priv, enum netsec_rings id)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[id];\n+\tint ret = 0;\n+\n+\tspin_lock_bh(&desc->spinlock_desc);\n+\n+\tif (desc->running) {\n+\t\tret = -EBUSY;\n+\t\tgoto err;\n+\t}\n+\n+\tswitch (desc->id) {\n+\tcase NETSEC_RING_RX:\n+\t\tnetsec_writel(priv, ads_irq_set[id], NETSEC_IRQ_RCV);\n+\t\tbreak;\n+\tcase NETSEC_RING_TX:\n+\t\tnetsec_writel(priv, ads_irq_set[id], NETSEC_IRQ_EMPTY);\n+\t\tbreak;\n+\t}\n+\n+\tnetsec_set_irq_coalesce_param(priv, desc->id);\n+\tdesc->running = true;\n+\n+err:\n+\tspin_unlock_bh(&desc->spinlock_desc);\n+\n+\treturn ret;\n+}\n+\n+void netsec_stop_desc_ring(struct netsec_priv *priv, enum netsec_rings id)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[id];\n+\n+\tspin_lock_bh(&desc->spinlock_desc);\n+\tif (desc->running)\n+\t\tnetsec_writel(priv, desc_ring_irq_inten_clr_reg_addr[id],\n+\t\t\t NETSEC_IRQ_RCV | NETSEC_IRQ_EMPTY |\n+\t\t\t NETSEC_IRQ_SND);\n+\n+\tdesc->running = false;\n+\tspin_unlock_bh(&desc->spinlock_desc);\n+}\n+\n+u16 netsec_get_rx_num(struct netsec_priv *priv)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[NETSEC_RING_RX];\n+\tu32 result;\n+\n+\tspin_lock(&desc->spinlock_desc);\n+\tif (desc->running) {\n+\t\tresult = netsec_readl(priv,\n+\t\t\t\t rx_pkt_cnt_reg_addr[NETSEC_RING_RX]);\n+\t\tdesc->rx_num += result;\n+\t\tif (result)\n+\t\t\tnetsec_inc_desc_head_idx(priv, desc, result);\n+\t}\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\treturn desc->rx_num;\n+}\n+\n+u16 netsec_get_tx_avail_num(struct netsec_priv *priv)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[NETSEC_RING_TX];\n+\tu16 result;\n+\n+\tspin_lock(&desc->spinlock_desc);\n+\n+\tif (!desc->running) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: not running tx desc\\n\", __func__);\n+\t\tresult = 0;\n+\t\tgoto err;\n+\t}\n+\n+\tresult = netsec_get_tx_avail_num_sub(priv, desc);\n+\n+err:\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\treturn result;\n+}\n+\n+int netsec_clean_tx_desc_ring(struct netsec_priv *priv)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[NETSEC_RING_TX];\n+\tunsigned int pkts = 0, bytes = 0;\n+\tstruct netsec_frag_info *frag;\n+\tstruct netsec_tx_de *entry;\n+\tbool is_last;\n+\n+\tspin_lock(&desc->spinlock_desc);\n+\n+\tnetsec_get_tx_done_num_sub(priv, desc);\n+\n+\twhile ((desc->tail != desc->head || desc->full) && desc->tx_done_num) {\n+\t\tfrag = &desc->frag[desc->tail];\n+\t\tentry = desc->ring_vaddr + desc->len * desc->tail;\n+\t\tis_last = (entry->attr >> NETSEC_TX_LAST) & 1;\n+\n+\t\tdma_unmap_single(priv->dev, frag->dma_addr, frag->len,\n+\t\t\t\t DMA_TO_DEVICE);\n+\t\tif (is_last) {\n+\t\t\tpkts++;\n+\t\t\tbytes += desc->priv[desc->tail]->len;\n+\t\t\tdev_kfree_skb(desc->priv[desc->tail]);\n+\t\t}\n+\t\tmemset(frag, 0, sizeof(*frag));\n+\t\tnetsec_inc_desc_tail_idx(priv, desc);\n+\n+\t\tif (is_last)\n+\t\t\tdesc->tx_done_num--;\n+\t}\n+\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\tpriv->ndev->stats.tx_packets += pkts;\n+\tpriv->ndev->stats.tx_bytes += bytes;\n+\n+\tnetdev_completed_queue(priv->ndev, pkts, bytes);\n+\n+\treturn 0;\n+}\n+\n+int netsec_clean_rx_desc_ring(struct netsec_priv *priv)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[NETSEC_RING_RX];\n+\n+\tspin_lock(&desc->spinlock_desc);\n+\n+\twhile (desc->full || (desc->tail != desc->head)) {\n+\t\tnetsec_set_rx_de(priv, desc, desc->tail,\n+\t\t\t\t &desc->frag[desc->tail],\n+\t\t\t\t desc->priv[desc->tail]);\n+\t\tdesc->rx_num--;\n+\t\tnetsec_inc_desc_tail_idx(priv, desc);\n+\t}\n+\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\treturn 0;\n+}\n+\n+int netsec_set_tx_pkt_data(struct netsec_priv *priv,\n+\t\t\t const struct netsec_tx_pkt_ctrl *tx_ctrl,\n+\t\t\t u8 count_frags, const struct netsec_frag_info *info,\n+\t\t\t struct sk_buff *skb)\n+{\n+\tstruct netsec_desc_ring *desc;\n+\tu32 sum_len = 0;\n+\tunsigned int i;\n+\tint ret = 0;\n+\n+\tif (tx_ctrl->tcp_seg_offload_flag && !tx_ctrl->cksum_offload_flag)\n+\t\treturn -EINVAL;\n+\n+\tif (tx_ctrl->tcp_seg_offload_flag) {\n+\t\tif (tx_ctrl->tcp_seg_len == 0)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (priv->param.use_jumbo_pkt_flag) {\n+\t\t\tif (tx_ctrl->tcp_seg_len > NETSEC_TCP_JUMBO_SEG_LEN_MAX)\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\tif (tx_ctrl->tcp_seg_len > NETSEC_TCP_SEG_LEN_MAX)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\tif (tx_ctrl->tcp_seg_len)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!count_frags)\n+\t\treturn -ERANGE;\n+\n+\tfor (i = 0; i < count_frags; i++) {\n+\t\tif ((info[i].len == 0) || (info[i].len > 0xffff)) {\n+\t\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t\t \"%s: bad info len\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsum_len += info[i].len;\n+\t}\n+\n+\tif (!tx_ctrl->tcp_seg_offload_flag) {\n+\t\tif (priv->param.use_jumbo_pkt_flag) {\n+\t\t\tif (sum_len > NETSEC_MAX_TX_JUMBO_PKT_LEN)\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\tif (sum_len > NETSEC_MAX_TX_PKT_LEN)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tdesc = &priv->desc_ring[NETSEC_RING_TX];\n+\tspin_lock(&desc->spinlock_desc);\n+\n+\tif (!desc->running) {\n+\t\tret = -ENODEV;\n+\t\tgoto end;\n+\t}\n+\n+\tsmp_rmb(); /* we need to see a consistent view of pending tx count */\n+\tif (count_frags > netsec_get_tx_avail_num_sub(priv, desc)) {\n+\t\tret = -EBUSY;\n+\t\tgoto end;\n+\t}\n+\n+\tfor (i = 0; i < count_frags; i++) {\n+\t\tnetsec_set_tx_desc_entry(priv, desc, tx_ctrl, i == 0,\n+\t\t\t\t\t i == count_frags - 1, &info[i], skb);\n+\t\tnetsec_inc_desc_head_idx(priv, desc, 1);\n+\t}\n+\n+\twmb(); /* ensure the descriptor is flushed */\n+\tnetsec_writel(priv, tx_pkt_cnt_reg_addr[NETSEC_RING_TX], 1);\n+\n+end:\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\treturn ret;\n+}\n+\n+int netsec_get_rx_pkt_data(struct netsec_priv *priv,\n+\t\t\t struct netsec_rx_pkt_info *rxpi,\n+\t\t\t struct netsec_frag_info *frag, u16 *len,\n+\t\t\t struct sk_buff **skb)\n+{\n+\tstruct netsec_desc_ring *desc = &priv->desc_ring[NETSEC_RING_RX];\n+\tstruct netsec_frag_info info;\n+\tstruct sk_buff *tmp_skb;\n+\tint ret = 0;\n+\n+\tspin_lock(&desc->spinlock_desc);\n+\n+\tif (desc->rx_num == 0) {\n+\t\tdev_err(priv->dev, \"%s 0 len rx\\n\", __func__);\n+\t\tret = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n+\tinfo.len = priv->rx_pkt_buf_len;\n+\trmb(); /* we need to ensure we only see current data in descriptor */\n+\ttmp_skb = alloc_rx_pkt_buf(priv, &info);\n+\tif (!tmp_skb) {\n+\t\tnetsec_set_rx_de(priv, desc, desc->tail,\n+\t\t\t\t &desc->frag[desc->tail],\n+\t\t\t\t desc->priv[desc->tail]);\n+\t\tret = -ENOMEM;\n+\t} else {\n+\t\tnetsec_get_rx_de(priv, desc, desc->tail, rxpi, frag, len, skb);\n+\t\tnetsec_set_rx_de(priv, desc, desc->tail, &info, tmp_skb);\n+\t}\n+\n+\tnetsec_inc_desc_tail_idx(priv, desc);\n+\tdesc->rx_num--;\n+\n+err:\n+\tspin_unlock(&desc->spinlock_desc);\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec_ethtool.c b/drivers/net/ethernet/socionext/netsec/netsec_ethtool.c\nnew file mode 100644\nindex 0000000..91f737d\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec_ethtool.c\n@@ -0,0 +1,76 @@\n+/**\n+ * drivers/net/ethernet/socionext/netsec/netsec_ethtool.c\n+ *\n+ * Copyright (C) 2013-2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+\n+#include \"netsec.h\"\n+\n+static void netsec_et_get_drvinfo(struct net_device *net_device,\n+\t\t\t\t struct ethtool_drvinfo *info)\n+{\n+\tstrlcpy(info->driver, \"netsec\", sizeof(info->driver));\n+\tstrlcpy(info->bus_info, dev_name(net_device->dev.parent),\n+\t\tsizeof(info->bus_info));\n+}\n+\n+static int netsec_et_get_coalesce(struct net_device *net_device,\n+\t\t\t\t struct ethtool_coalesce *et_coalesce)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(net_device);\n+\n+\t*et_coalesce = priv->et_coalesce;\n+\n+\treturn 0;\n+}\n+\n+static int netsec_et_set_coalesce(struct net_device *net_device,\n+\t\t\t\t struct ethtool_coalesce *et_coalesce)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(net_device);\n+\n+\tif (et_coalesce->rx_max_coalesced_frames > NETSEC_INT_PKTCNT_MAX)\n+\t\treturn -EINVAL;\n+\tif (et_coalesce->tx_max_coalesced_frames > NETSEC_INT_PKTCNT_MAX)\n+\t\treturn -EINVAL;\n+\tif (!et_coalesce->rx_max_coalesced_frames)\n+\t\treturn -EINVAL;\n+\tif (!et_coalesce->tx_max_coalesced_frames)\n+\t\treturn -EINVAL;\n+\n+\tpriv->et_coalesce = *et_coalesce;\n+\n+\treturn 0;\n+}\n+\n+static u32 netsec_et_get_msglevel(struct net_device *dev)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(dev);\n+\n+\treturn priv->msg_enable;\n+}\n+\n+static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(dev);\n+\n+\tpriv->msg_enable = datum;\n+}\n+\n+const struct ethtool_ops netsec_ethtool_ops = {\n+\t.get_drvinfo\t\t= netsec_et_get_drvinfo,\n+\t.get_link_ksettings\t= phy_ethtool_get_link_ksettings,\n+\t.set_link_ksettings\t= phy_ethtool_set_link_ksettings,\n+\t.get_link\t\t= ethtool_op_get_link,\n+\t.get_coalesce\t\t= netsec_et_get_coalesce,\n+\t.set_coalesce\t\t= netsec_et_set_coalesce,\n+\t.get_msglevel\t\t= netsec_et_get_msglevel,\n+\t.set_msglevel\t\t= netsec_et_set_msglevel,\n+};\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c b/drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c\nnew file mode 100644\nindex 0000000..415c7b4\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c\n@@ -0,0 +1,329 @@\n+/**\n+ * drivers/net/ethernet/socionext/netsec/netsec_gmac_access.c\n+ *\n+ * Copyright (C) 2011-2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+#include \"netsec.h\"\n+\n+#define TIMEOUT_SPINS_MAC 1000\n+#define TIMEOUT_SECONDARY_MS_MAC 100\n+\n+static u32 netsec_clk_type(u32 freq)\n+{\n+\tif (freq < 35 * NETSEC_CLK_MHZ)\n+\t\treturn NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;\n+\tif (freq < 60 * NETSEC_CLK_MHZ)\n+\t\treturn NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;\n+\tif (freq < 100 * NETSEC_CLK_MHZ)\n+\t\treturn NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;\n+\tif (freq < 150 * NETSEC_CLK_MHZ)\n+\t\treturn NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;\n+\tif (freq < 250 * NETSEC_CLK_MHZ)\n+\t\treturn NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;\n+\n+\treturn NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;\n+}\n+\n+static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)\n+{\n+\tu32 timeout = TIMEOUT_SPINS_MAC;\n+\n+\twhile (--timeout && netsec_readl(priv, addr) & mask)\n+\t\t;\n+\tif (timeout)\n+\t\treturn 0;\n+\n+\ttimeout = TIMEOUT_SECONDARY_MS_MAC;\n+\twhile (--timeout && netsec_readl(priv, addr) & mask)\n+\t\tusleep_range(1000, 2000);\n+\n+\tif (timeout)\n+\t\treturn 0;\n+\n+\tnetdev_WARN(priv->ndev, \"%s: timeout\\n\", __func__);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)\n+{\n+\tnetsec_writel(priv, MAC_REG_DATA, value);\n+\tnetsec_writel(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);\n+\treturn netsec_wait_while_busy(priv,\n+\t\t\t\t MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);\n+}\n+\n+static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)\n+{\n+\tint ret;\n+\n+\tnetsec_writel(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);\n+\tret = netsec_wait_while_busy(priv,\n+\t\t\t\t MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*read = netsec_readl(priv, MAC_REG_DATA);\n+\n+\treturn 0;\n+}\n+\n+static int netsec_mac_wait_while_busy(struct netsec_priv *priv,\n+\t\t\t\t u32 addr, u32 mask)\n+{\n+\tu32 timeout = TIMEOUT_SPINS_MAC;\n+\tint ret, data;\n+\n+\tdo {\n+\t\tret = netsec_mac_read(priv, addr, &data);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t} while (--timeout && (data & mask));\n+\n+\tif (timeout)\n+\t\treturn 0;\n+\n+\ttimeout = TIMEOUT_SECONDARY_MS_MAC;\n+\tdo {\n+\t\tusleep_range(1000, 2000);\n+\n+\t\tret = netsec_mac_read(priv, addr, &data);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t} while (--timeout && (data & mask));\n+\n+\tif (timeout && !ret)\n+\t\treturn 0;\n+\n+\tnetdev_WARN(priv->ndev, \"%s: timeout\\n\", __func__);\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)\n+{\n+\tstruct phy_device *phydev = priv->ndev->phydev;\n+\tu32 value = 0;\n+\n+\tvalue = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :\n+\t\t\t\t NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;\n+\n+\tif (phydev->speed != SPEED_1000)\n+\t\tvalue |= NETSEC_MCR_PS;\n+\n+\tif ((priv->phy_interface != PHY_INTERFACE_MODE_GMII) &&\n+\t (phydev->speed == SPEED_100))\n+\t\tvalue |= NETSEC_GMAC_MCR_REG_FES;\n+\n+\tvalue |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;\n+\n+\tif (priv->phy_interface == PHY_INTERFACE_MODE_RGMII)\n+\t\tvalue |= NETSEC_GMAC_MCR_REG_IBN;\n+\n+\tif (netsec_mac_write(priv, GMAC_REG_MCR, value))\n+\t\treturn -ETIMEDOUT;\n+\n+\tpriv->actual_link_speed = phydev->speed;\n+\tpriv->actual_duplex = phydev->duplex;\n+\tnetif_info(priv, drv, priv->ndev, \"%s: %uMbps, duplex:%d\\n\",\n+\t\t __func__, phydev->speed, phydev->duplex);\n+\n+\treturn 0;\n+}\n+\n+/* NB netsec_start_gmac() only called from adjust_link */\n+\n+int netsec_start_gmac(struct netsec_priv *priv)\n+{\n+\tstruct phy_device *phydev = priv->ndev->phydev;\n+\tu32 value = 0;\n+\tint ret;\n+\n+\tif (priv->desc_ring[NETSEC_RING_TX].running &&\n+\t priv->desc_ring[NETSEC_RING_RX].running)\n+\t\treturn 0;\n+\n+\tif (!priv->desc_ring[NETSEC_RING_RX].running &&\n+\t !priv->desc_ring[NETSEC_RING_TX].running) {\n+\t\tif (phydev->speed != SPEED_1000)\n+\t\t\tvalue = (NETSEC_GMAC_MCR_REG_CST |\n+\t\t\t\t NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);\n+\n+\t\tif (netsec_mac_write(priv, GMAC_REG_MCR, value))\n+\t\t\treturn -ETIMEDOUT;\n+\t\tif (netsec_mac_write(priv, GMAC_REG_BMR,\n+\t\t\t\t NETSEC_GMAC_BMR_REG_RESET))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\t/* Wait soft reset */\n+\t\tusleep_range(1000, 5000);\n+\n+\t\tret = netsec_mac_read(priv, GMAC_REG_BMR, &value);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tif (value & NETSEC_GMAC_BMR_REG_SWR)\n+\t\t\treturn -EAGAIN;\n+\n+\t\tnetsec_writel(priv, MAC_REG_DESC_SOFT_RST, 1);\n+\t\tif (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tnetsec_writel(priv, MAC_REG_DESC_INIT, 1);\n+\t\tif (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tif (netsec_mac_write(priv, GMAC_REG_BMR,\n+\t\t\t\t NETSEC_GMAC_BMR_REG_COMMON))\n+\t\t\treturn -ETIMEDOUT;\n+\t\tif (netsec_mac_write(priv, GMAC_REG_RDLAR, priv->rdlar_pa))\n+\t\t\treturn -ETIMEDOUT;\n+\t\tif (netsec_mac_write(priv, GMAC_REG_TDLAR, priv->tdlar_pa))\n+\t\t\treturn -ETIMEDOUT;\n+\t\tif (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tret = netsec_mac_update_to_phy_state(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (priv->mac_mode.flow_ctrl_enable_flag) {\n+\t\t\tnetsec_writel(priv, MAC_REG_FLOW_TH,\n+\t\t\t\t (priv->mac_mode.flow_stop_th << 16) |\n+\t\t\t\t priv->mac_mode.flow_start_th);\n+\t\t\tif (netsec_mac_write(priv, GMAC_REG_FCR,\n+\t\t\t\t\t (priv->mac_mode.pause_time << 16) |\n+\t\t\t\t\t NETSEC_FCR_RFE | NETSEC_FCR_TFE))\n+\t\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t}\n+\n+\tret = netsec_mac_read(priv, GMAC_REG_OMR, &value);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!priv->desc_ring[NETSEC_RING_RX].running) {\n+\t\tvalue |= NETSEC_GMAC_OMR_REG_SR;\n+\t\tnetsec_start_desc_ring(priv, NETSEC_RING_RX);\n+\t}\n+\tif (!priv->desc_ring[NETSEC_RING_TX].running) {\n+\t\tvalue |= NETSEC_GMAC_OMR_REG_ST;\n+\t\tnetsec_start_desc_ring(priv, NETSEC_RING_TX);\n+\t}\n+\n+\tif (netsec_mac_write(priv, GMAC_REG_OMR, value))\n+\t\treturn -ETIMEDOUT;\n+\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_SET,\n+\t\t NETSEC_IRQ_TX | NETSEC_IRQ_RX);\n+\n+\treturn 0;\n+}\n+\n+int netsec_stop_gmac(struct netsec_priv *priv)\n+{\n+\tu32 value;\n+\tint ret;\n+\n+\tret = netsec_mac_read(priv, GMAC_REG_OMR, &value);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (priv->desc_ring[NETSEC_RING_RX].running) {\n+\t\tvalue &= ~NETSEC_GMAC_OMR_REG_SR;\n+\t\tnetsec_stop_desc_ring(priv, NETSEC_RING_RX);\n+\t}\n+\tif (priv->desc_ring[NETSEC_RING_TX].running) {\n+\t\tvalue &= ~NETSEC_GMAC_OMR_REG_ST;\n+\t\tnetsec_stop_desc_ring(priv, NETSEC_RING_TX);\n+\t}\n+\n+\tpriv->actual_link_speed = 0;\n+\tpriv->actual_duplex = false;\n+\n+\treturn netsec_mac_write(priv, GMAC_REG_OMR, value);\n+}\n+\n+static int netsec_phy_write(struct mii_bus *bus,\n+\t\t\t int phy_addr, int reg, u16 val)\n+{\n+\tstruct netsec_priv *priv = bus->priv;\n+\n+\tif (netsec_mac_write(priv, GMAC_REG_GDR, val))\n+\t\treturn -ETIMEDOUT;\n+\tif (netsec_mac_write(priv, GMAC_REG_GAR,\n+\t\t\t phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |\n+\t\t\t reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |\n+\t\t\t NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB) |\n+\t\t\t (netsec_clk_type(priv->freq) <<\n+\t\t\t GMAC_REG_SHIFT_CR_GAR))\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,\n+\t\t\t\t\t NETSEC_GMAC_GAR_REG_GB);\n+}\n+\n+static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)\n+{\n+\tstruct netsec_priv *priv = bus->priv;\n+\tu32 data;\n+\tint ret;\n+\n+\tif (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |\n+\t\t\t phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |\n+\t\t\t reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |\n+\t\t\t (netsec_clk_type(priv->freq) <<\n+\t\t\t GMAC_REG_SHIFT_CR_GAR)))\n+\t\treturn -ETIMEDOUT;\n+\n+\tret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,\n+\t\t\t\t\t NETSEC_GMAC_GAR_REG_GB);\n+\tif (ret)\n+\t\treturn 0;\n+\n+\tret = netsec_mac_read(priv, GMAC_REG_GDR, &data);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn data;\n+}\n+\n+int netsec_mii_register(struct netsec_priv *priv)\n+{\n+\tstruct mii_bus *bus = mdiobus_alloc();\n+\tstruct resource res;\n+\tint ret;\n+\n+\tif (!bus)\n+\t\treturn -ENOMEM;\n+\n+\tof_address_to_resource(priv->dev->of_node, 0, &res);\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"%s\", priv->dev->of_node->full_name);\n+\tbus->priv = priv;\n+\tbus->name = \"SNI NETSEC MDIO\";\n+\tbus->read = netsec_phy_read;\n+\tbus->write = netsec_phy_write;\n+\tbus->parent = priv->dev;\n+\tpriv->mii_bus = bus;\n+\n+\tret = of_mdiobus_register(bus, priv->dev->of_node);\n+\tif (ret) {\n+\t\tmdiobus_free(bus);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void netsec_mii_unregister(struct netsec_priv *priv)\n+{\n+\tmdiobus_unregister(priv->mii_bus);\n+\tmdiobus_free(priv->mii_bus);\n+\tpriv->mii_bus = NULL;\n+}\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec_netdev.c b/drivers/net/ethernet/socionext/netsec/netsec_netdev.c\nnew file mode 100644\nindex 0000000..ff418c1\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec_netdev.c\n@@ -0,0 +1,558 @@\n+/**\n+ * drivers/net/ethernet/socionext/netsec/netsec_netdev.c\n+ *\n+ * Copyright (C) 2013-2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+\n+#include <linux/ip.h>\n+#include <linux/ipv6.h>\n+#include <linux/tcp.h>\n+#include <net/tcp.h>\n+#include <net/ip6_checksum.h>\n+#include <linux/pm_runtime.h>\n+\n+#include \"netsec.h\"\n+\n+#define WAIT_FW_RDY_TIMEOUT 50\n+\n+static const u32 desc_ring_irq_status_reg_addr[] = {\n+\tNETSEC_REG_NRM_TX_STATUS,\n+\tNETSEC_REG_NRM_RX_STATUS,\n+};\n+\n+static const u32 desc_ads[] = {\n+\tNETSEC_REG_NRM_TX_CONFIG,\n+\tNETSEC_REG_NRM_RX_CONFIG,\n+};\n+\n+static const u32 netsec_desc_start_reg_addr_up[] = {\n+\tNETSEC_REG_NRM_TX_DESC_START_UP,\n+\tNETSEC_REG_NRM_RX_DESC_START_UP,\n+};\n+\n+static const u32 netsec_desc_start_reg_addr_lw[] = {\n+\tNETSEC_REG_NRM_TX_DESC_START_LW,\n+\tNETSEC_REG_NRM_RX_DESC_START_LW,\n+};\n+\n+static int netsec_wait_for_ring_config_ready(struct netsec_priv *priv, int ring)\n+{\n+\tint timeout = WAIT_FW_RDY_TIMEOUT;\n+\n+\twhile (--timeout && (netsec_readl(priv, desc_ads[ring]) &\n+\t\t\t NETSEC_REG_DESC_RING_CONFIG_CFG_UP))\n+\t\tusleep_range(1000, 2000);\n+\n+\tif (!timeout) {\n+\t\tnetif_err(priv, hw, priv->ndev,\n+\t\t\t \"%s: timeout\\n\", __func__);\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static u32 netsec_calc_pkt_ctrl_reg_param(const struct netsec_pkt_ctrlaram\n+\t\t\t\t\t*pkt_ctrlaram_p)\n+{\n+\tu32 param = NETSEC_PKT_CTRL_REG_MODE_NRM;\n+\n+\tif (pkt_ctrlaram_p->log_chksum_er_flag)\n+\t\tparam |= NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER;\n+\n+\tif (pkt_ctrlaram_p->log_hd_imcomplete_flag)\n+\t\tparam |= NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE;\n+\n+\tif (pkt_ctrlaram_p->log_hd_er_flag)\n+\t\tparam |= NETSEC_PKT_CTRL_REG_LOG_HD_ER;\n+\n+\treturn param;\n+}\n+\n+static int netsec_configure_normal_mode(struct netsec_priv *priv)\n+{\n+\tint ret = 0;\n+\tu32 value;\n+\n+\t/* save scb set value */\n+\tpriv->scb_set_normal_tx_paddr = (phys_addr_t)netsec_readl(priv,\n+\t\t\tnetsec_desc_start_reg_addr_up[NETSEC_RING_TX]) << 32;\n+\tpriv->scb_set_normal_tx_paddr |= (phys_addr_t)netsec_readl(priv,\n+\t\t\tnetsec_desc_start_reg_addr_lw[NETSEC_RING_TX]);\n+\n+\t/* set desc_start addr */\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_up[NETSEC_RING_RX],\n+\t\t priv->desc_ring[NETSEC_RING_RX].desc_phys >> 32);\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_lw[NETSEC_RING_RX],\n+\t\t priv->desc_ring[NETSEC_RING_RX].desc_phys & 0xffffffff);\n+\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_up[NETSEC_RING_TX],\n+\t\t priv->desc_ring[NETSEC_RING_TX].desc_phys >> 32);\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_lw[NETSEC_RING_TX],\n+\t\t priv->desc_ring[NETSEC_RING_TX].desc_phys & 0xffffffff);\n+\n+\t/* set normal tx desc ring config */\n+\tvalue = (cpu_to_le32(1) == 1) << NETSEC_REG_DESC_ENDIAN |\n+\t\tNETSEC_REG_DESC_RING_CONFIG_CFG_UP |\n+\t\tNETSEC_REG_DESC_RING_CONFIG_CH_RST;\n+\tnetsec_writel(priv, desc_ads[NETSEC_RING_TX], value);\n+\n+\tvalue = (cpu_to_le32(1) == 1) << NETSEC_REG_DESC_ENDIAN |\n+\t\tNETSEC_REG_DESC_RING_CONFIG_CFG_UP |\n+\t\tNETSEC_REG_DESC_RING_CONFIG_CH_RST;\n+\tnetsec_writel(priv, desc_ads[NETSEC_RING_RX], value);\n+\n+\tif (netsec_wait_for_ring_config_ready(priv, NETSEC_RING_TX) ||\n+\t netsec_wait_for_ring_config_ready(priv, NETSEC_RING_RX))\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn ret;\n+}\n+\n+static int netsec_change_mode_to_normal(struct netsec_priv *priv)\n+{\n+\tu32 value;\n+\n+\tpriv->scb_pkt_ctrl_reg = netsec_readl(priv, NETSEC_REG_PKT_CTRL);\n+\n+\tvalue = netsec_calc_pkt_ctrl_reg_param(&priv->param.pkt_ctrlaram);\n+\n+\tif (priv->param.use_jumbo_pkt_flag)\n+\t\tvalue |= NETSEC_PKT_CTRL_REG_EN_JUMBO;\n+\n+\tvalue |= NETSEC_PKT_CTRL_REG_MODE_NRM;\n+\n+\t/* change to normal mode */\n+\tnetsec_writel(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);\n+\tnetsec_writel(priv, NETSEC_REG_PKT_CTRL, value);\n+\n+\t/* Wait Change mode Complete */\n+\tusleep_range(2000, 10000);\n+\n+\treturn 0;\n+}\n+\n+static int netsec_change_mode_to_taiki(struct netsec_priv *priv)\n+{\n+\tint ret = 0;\n+\tu32 value;\n+\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_up[NETSEC_RING_TX],\n+\t\t priv->scb_set_normal_tx_paddr >> 32);\n+\tnetsec_writel(priv, netsec_desc_start_reg_addr_lw[NETSEC_RING_TX],\n+\t\t priv->scb_set_normal_tx_paddr & 0xffffffff);\n+\n+\tvalue = NETSEC_REG_DESC_RING_CONFIG_CFG_UP |\n+\t\tNETSEC_REG_DESC_RING_CONFIG_CH_RST;\n+\n+\tnetsec_writel(priv, desc_ads[NETSEC_RING_TX], value);\n+\n+\tif (netsec_wait_for_ring_config_ready(priv, NETSEC_RING_TX))\n+\t\treturn -ETIMEDOUT;\n+\n+\tnetsec_writel(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);\n+\tnetsec_writel(priv, NETSEC_REG_PKT_CTRL, priv->scb_pkt_ctrl_reg);\n+\n+\t/* Wait Change mode Complete */\n+\tusleep_range(2000, 10000);\n+\n+\treturn ret;\n+}\n+\n+static int netsec_clear_modechange_irq(struct netsec_priv *priv, u32 value)\n+{\n+\tnetsec_writel(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS,\n+\t\t (value & (NETSEC_MODE_TRANS_COMP_IRQ_N2T |\n+\t\t NETSEC_MODE_TRANS_COMP_IRQ_T2N)));\n+\treturn 0;\n+}\n+\n+static int netsec_hw_configure_to_normal(struct netsec_priv *priv)\n+{\n+\tint err;\n+\n+\terr = netsec_configure_normal_mode(priv);\n+\tif (err) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: normal conf fail\\n\", __func__);\n+\t\treturn err;\n+\t}\n+\terr = netsec_change_mode_to_normal(priv);\n+\tif (err) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: normal set fail\\n\", __func__);\n+\t\treturn err;\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int netsec_hw_configure_to_taiki(struct netsec_priv *priv)\n+{\n+\tint ret;\n+\n+\tret = netsec_change_mode_to_taiki(priv);\n+\tif (ret) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: taiki set fail\\n\", __func__);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Clear mode change complete IRQ */\n+\tret = netsec_clear_modechange_irq(priv, NETSEC_MODE_TRANS_COMP_IRQ_T2N\n+\t\t\t\t\t | NETSEC_MODE_TRANS_COMP_IRQ_N2T);\n+\n+\tif (ret)\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: clear mode fail\\n\", __func__);\n+\n+\treturn ret;\n+}\n+\n+static void netsec_ring_irq_clr(struct netsec_priv *priv,\n+\t\t\t\tunsigned int id, u32 value)\n+{\n+\tnetsec_writel(priv, desc_ring_irq_status_reg_addr[id],\n+\t\t value & (NETSEC_IRQ_EMPTY | NETSEC_IRQ_ERR));\n+}\n+\n+static void netsec_napi_tx_processing(struct napi_struct *napi_p)\n+{\n+\tstruct netsec_priv *priv = container_of(napi_p,\n+\t\t\t\t\t\tstruct netsec_priv, napi);\n+\n+\tnetsec_ring_irq_clr(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\tnetsec_clean_tx_desc_ring(priv);\n+\n+\tif (netif_queue_stopped(priv->ndev) &&\n+\t netsec_get_tx_avail_num(priv) >= NETSEC_NETDEV_TX_PKT_SCAT_NUM_MAX)\n+\t\tnetif_wake_queue(priv->ndev);\n+}\n+\n+int netsec_netdev_napi_poll(struct napi_struct *napi_p, int budget)\n+{\n+\tstruct netsec_priv *priv = container_of(napi_p,\n+\t\t\t\t\t\tstruct netsec_priv, napi);\n+\tstruct net_device *ndev = priv->ndev;\n+\tstruct netsec_rx_pkt_info rx_info;\n+\tint ret, done = 0, rx_num = 0;\n+\tstruct netsec_frag_info frag;\n+\tstruct sk_buff *skb;\n+\tu16 len;\n+\n+\tnetsec_napi_tx_processing(napi_p);\n+\n+\twhile (done < budget) {\n+\t\tif (!rx_num) {\n+\t\t\trx_num = netsec_get_rx_num(priv);\n+\t\t\tif (!rx_num)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tdone++;\n+\t\trx_num--;\n+\t\tret = netsec_get_rx_pkt_data(priv, &rx_info, &frag, &len, &skb);\n+\t\tif (unlikely(ret == -ENOMEM)) {\n+\t\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t\t \"%s: rx fail %d\\n\", __func__, ret);\n+\t\t\tndev->stats.rx_dropped++;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tdma_unmap_single(priv->dev, frag.dma_addr, frag.len,\n+\t\t\t\t DMA_FROM_DEVICE);\n+\t\tskb_put(skb, len);\n+\t\tskb->protocol = eth_type_trans(skb, priv->ndev);\n+\n+\t\tif (priv->rx_cksum_offload_flag &&\n+\t\t rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)\n+\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n+\n+\t\tnapi_gro_receive(napi_p, skb);\n+\n+\t\tndev->stats.rx_packets++;\n+\t\tndev->stats.rx_bytes += len;\n+\t}\n+\n+\tif (done == budget)\n+\t\treturn budget;\n+\n+\tnapi_complete(napi_p);\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_SET,\n+\t\t NETSEC_IRQ_TX | NETSEC_IRQ_RX);\n+\n+\treturn done;\n+}\n+\n+static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,\n+\t\t\t\t\t struct net_device *ndev)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(ndev);\n+\tstruct netsec_tx_pkt_ctrl tx_ctrl;\n+\tu16 pend_tx, tso_seg_len = 0;\n+\tskb_frag_t *frag;\n+\tint count_frags;\n+\tint ret, i;\n+\n+\tmemset(&tx_ctrl, 0, sizeof(struct netsec_tx_pkt_ctrl));\n+\n+\tnetsec_ring_irq_clr(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\n+\tcount_frags = skb_shinfo(skb)->nr_frags + 1;\n+\n+\tif (skb->ip_summed == CHECKSUM_PARTIAL)\n+\t\ttx_ctrl.cksum_offload_flag = true;\n+\n+\tif (skb_is_gso(skb))\n+\t\ttso_seg_len = skb_shinfo(skb)->gso_size;\n+\n+\tif (tso_seg_len > 0) {\n+\t\tif (skb->protocol == htons(ETH_P_IP)) {\n+\t\t\tip_hdr(skb)->tot_len = 0;\n+\t\t\ttcp_hdr(skb)->check =\n+\t\t\t\t~tcp_v4_check(0, ip_hdr(skb)->saddr,\n+\t\t\t\t\t ip_hdr(skb)->daddr, 0);\n+\t\t} else {\n+\t\t\tipv6_hdr(skb)->payload_len = 0;\n+\t\t\ttcp_hdr(skb)->check =\n+\t\t\t\t~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,\n+\t\t\t\t\t\t &ipv6_hdr(skb)->daddr,\n+\t\t\t\t\t\t 0, IPPROTO_TCP, 0);\n+\t\t}\n+\n+\t\ttx_ctrl.tcp_seg_offload_flag = true;\n+\t\ttx_ctrl.tcp_seg_len = tso_seg_len;\n+\t}\n+\n+\tpriv->tx_info[0].dma_addr = dma_map_single(priv->dev, skb->data,\n+\t\t\t\t\t\t skb_headlen(skb),\n+\t\t\t\t\t\t DMA_TO_DEVICE);\n+\tif (dma_mapping_error(priv->dev, priv->tx_info[0].dma_addr)) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: DMA mapping failed\\n\", __func__);\n+\t\treturn NETDEV_TX_OK;\n+\t}\n+\tpriv->tx_info[0].addr = skb->data;\n+\tpriv->tx_info[0].len = skb_headlen(skb);\n+\n+\tfor (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {\n+\t\tfrag = &skb_shinfo(skb)->frags[i];\n+\t\tpriv->tx_info[i + 1].dma_addr =\n+\t\t\tskb_frag_dma_map(priv->dev, frag, 0,\n+\t\t\t\t\t skb_frag_size(frag), DMA_TO_DEVICE);\n+\t\tpriv->tx_info[i + 1].addr = skb_frag_address(frag);\n+\t\tpriv->tx_info[i + 1].len = frag->size;\n+\t}\n+\n+\tnetsec_mark_skb_type(skb, NETSEC_RING_TX);\n+\n+\tret = netsec_set_tx_pkt_data(priv, &tx_ctrl, count_frags,\n+\t\t\t\t priv->tx_info, skb);\n+\tif (ret) {\n+\t\tnetif_info(priv, drv, priv->ndev,\n+\t\t\t \"set tx pkt failed %d\\n\", ret);\n+\t\tfor (i = 0; i < count_frags; i++)\n+\t\t\tdma_unmap_single(priv->dev, priv->tx_info[i].dma_addr,\n+\t\t\t\t\t priv->tx_info[i].len, DMA_TO_DEVICE);\n+\t\tndev->stats.tx_dropped++;\n+\n+\t\treturn NETDEV_TX_OK;\n+\t}\n+\n+\tnetdev_sent_queue(priv->ndev, skb->len);\n+\n+\tspin_lock(&priv->tx_queue_lock);\n+\tpend_tx = netsec_get_tx_avail_num(priv);\n+\n+\tif (pend_tx < NETSEC_NETDEV_TX_PKT_SCAT_NUM_MAX) {\n+\t\tnetsec_ring_irq_enable(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\t\tnetif_stop_queue(ndev);\n+\t\tgoto err;\n+\t}\n+\tif (pend_tx <= DESC_NUM - 2) {\n+\t\tnetsec_ring_irq_enable(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\t\tgoto err;\n+\t}\n+\tnetsec_ring_irq_disable(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\n+err:\n+\tspin_unlock(&priv->tx_queue_lock);\n+\n+\treturn NETDEV_TX_OK;\n+}\n+\n+static int netsec_netdev_set_features(struct net_device *ndev,\n+\t\t\t\t netdev_features_t features)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(ndev);\n+\n+\tpriv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);\n+\n+\treturn 0;\n+}\n+\n+static void netsec_phy_adjust_link(struct net_device *ndev)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(ndev);\n+\n+\tif (priv->actual_link_speed == ndev->phydev->speed &&\n+\t priv->actual_duplex == ndev->phydev->duplex)\n+\t\treturn;\n+\n+\tnetsec_stop_gmac(priv);\n+\tnetsec_start_gmac(priv);\n+}\n+\n+static irqreturn_t netsec_irq_handler(int irq, void *dev_id)\n+{\n+\tstruct netsec_priv *priv = dev_id;\n+\tu32 status = netsec_readl(priv, NETSEC_REG_TOP_STATUS) &\n+\t\t netsec_readl(priv, NETSEC_REG_TOP_INTEN);\n+\n+\tif (!status)\n+\t\treturn IRQ_NONE;\n+\n+\tif (status & (NETSEC_IRQ_TX | NETSEC_IRQ_RX)) {\n+\t\tnetsec_writel(priv, NETSEC_REG_INTEN_CLR,\n+\t\t\t status & (NETSEC_IRQ_TX | NETSEC_IRQ_RX));\n+\t\tnapi_schedule(&priv->napi);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int netsec_netdev_open(struct net_device *ndev)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(ndev);\n+\tstruct phy_device *phydev = NULL;\n+\tu32 scb_irq_temp;\n+\tint ret, n;\n+\n+\tscb_irq_temp = netsec_readl(priv, NETSEC_REG_TOP_INTEN);\n+\n+\tfor (n = 0; n <= NETSEC_RING_MAX; n++) {\n+\t\tret = netsec_alloc_desc_ring(priv, n);\n+\t\tif (ret) {\n+\t\t\tnetif_err(priv, probe, priv->ndev,\n+\t\t\t\t \"%s: alloc ring failed\\n\", __func__);\n+\t\t\tgoto err;\n+\t\t}\n+\t}\n+\n+\tret = netsec_setup_rx_desc(priv, &priv->desc_ring[NETSEC_RING_RX]);\n+\tif (ret) {\n+\t\tnetif_err(priv, probe, priv->ndev,\n+\t\t\t \"%s: fail setup ring\\n\", __func__);\n+\t\tgoto err1;\n+\t}\n+\n+\tpm_runtime_get_sync(priv->dev);\n+\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_CLR, scb_irq_temp);\n+\n+\tret = netsec_hw_configure_to_normal(priv);\n+\tif (ret) {\n+\t\tnetif_err(priv, probe, priv->ndev,\n+\t\t\t \"%s: normal fail %d\\n\", __func__, ret);\n+\t\tgoto err1;\n+\t}\n+\n+\tret = request_irq(priv->ndev->irq, netsec_irq_handler,\n+\t\t\t IRQF_SHARED, \"netsec\", priv);\n+\tif (ret) {\n+\t\tnetif_err(priv, drv, priv->ndev, \"request_irq failed\\n\");\n+\t\tgoto err1;\n+\t}\n+\tpriv->irq_registered = true;\n+\n+\tret = netsec_clean_rx_desc_ring(priv);\n+\tif (ret) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: clean rx desc fail\\n\", __func__);\n+\t\tgoto err2;\n+\t}\n+\n+\tret = netsec_clean_tx_desc_ring(priv);\n+\tif (ret) {\n+\t\tnetif_err(priv, drv, priv->ndev,\n+\t\t\t \"%s: clean tx desc fail\\n\", __func__);\n+\t\tgoto err2;\n+\t}\n+\n+\tnetsec_ring_irq_clr(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\n+\tphydev = of_phy_connect(priv->ndev, priv->phy_np,\n+\t\t\t\t&netsec_phy_adjust_link, 0,\n+\t\t\t\tpriv->phy_interface);\n+\tif (!phydev) {\n+\t\tnetif_err(priv, link, priv->ndev, \"missing PHY\\n\");\n+\t\tgoto err2;\n+\t}\n+\n+\tphy_start_aneg(phydev);\n+\n+\tnetsec_ring_irq_disable(priv, NETSEC_RING_TX, NETSEC_IRQ_EMPTY);\n+\n+\tnetsec_start_gmac(priv);\n+\tnapi_enable(&priv->napi);\n+\tnetif_start_queue(ndev);\n+\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_SET,\n+\t\t NETSEC_IRQ_TX | NETSEC_IRQ_RX);\n+\n+\treturn 0;\n+\n+err2:\n+\tpm_runtime_put_sync(priv->dev);\n+\tfree_irq(priv->ndev->irq, priv);\n+\tpriv->irq_registered = false;\n+err1:\n+\tfor (n = 0; n <= NETSEC_RING_MAX; n++)\n+\t\tnetsec_free_desc_ring(priv, &priv->desc_ring[n]);\n+err:\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_SET, scb_irq_temp);\n+\n+\tpm_runtime_put_sync(priv->dev);\n+\n+\treturn ret;\n+}\n+\n+static int netsec_netdev_stop(struct net_device *ndev)\n+{\n+\tstruct netsec_priv *priv = netdev_priv(ndev);\n+\tint n;\n+\n+\tphy_stop(ndev->phydev);\n+\tphy_disconnect(ndev->phydev);\n+\n+\tnetif_stop_queue(priv->ndev);\n+\tnapi_disable(&priv->napi);\n+\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_CLR, ~0);\n+\tnetsec_stop_gmac(priv);\n+\tWARN_ON(netsec_hw_configure_to_taiki(priv));\n+\n+\tpm_runtime_put_sync(priv->dev);\n+\n+\tfor (n = 0; n <= NETSEC_RING_MAX; n++)\n+\t\tnetsec_free_desc_ring(priv, &priv->desc_ring[n]);\n+\n+\tfree_irq(priv->ndev->irq, priv);\n+\tpriv->irq_registered = false;\n+\n+\treturn 0;\n+}\n+\n+const struct net_device_ops netsec_netdev_ops = {\n+\t.ndo_open\t\t= netsec_netdev_open,\n+\t.ndo_stop\t\t= netsec_netdev_stop,\n+\t.ndo_start_xmit\t\t= netsec_netdev_start_xmit,\n+\t.ndo_set_features\t= netsec_netdev_set_features,\n+\t.ndo_set_mac_address = eth_mac_addr,\n+\t.ndo_validate_addr\t= eth_validate_addr,\n+};\ndiff --git a/drivers/net/ethernet/socionext/netsec/netsec_platform.c b/drivers/net/ethernet/socionext/netsec/netsec_platform.c\nnew file mode 100644\nindex 0000000..d5c19f7\n--- /dev/null\n+++ b/drivers/net/ethernet/socionext/netsec/netsec_platform.c\n@@ -0,0 +1,330 @@\n+/**\n+ * drivers/net/ethernet/socionext/netsec/netsec_platform.c\n+ *\n+ * Copyright (C) 2013-2014 Fujitsu Semiconductor Limited.\n+ * Copyright (C) 2014 Linaro Ltd Andy Green <andy.green@linaro.org>\n+ * All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/ctype.h>\n+#include <linux/netdevice.h>\n+#include <linux/types.h>\n+#include <linux/bitops.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/module.h>\n+#include <linux/sizes.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/of_net.h>\n+#include <linux/io.h>\n+#include <linux/pm_runtime.h>\n+\n+#include \"netsec.h\"\n+\n+#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) (x & 0xffff0000)\n+\n+static int napi_weight = 64;\n+unsigned short pause_time = 256;\n+\n+static int netsec_probe(struct platform_device *pdev)\n+{\n+\tstruct net_device *ndev;\n+\tstruct netsec_priv *priv;\n+\tstruct resource *res;\n+\tconst void *mac;\n+\tbool use_jumbo;\n+\tu32 hw_ver;\n+\tint err;\n+\tint ret;\n+\n+\tndev = alloc_etherdev(sizeof(*priv));\n+\tif (!ndev)\n+\t\treturn -ENOMEM;\n+\n+\tpriv = netdev_priv(ndev);\n+\tpriv->ndev = ndev;\n+\tSET_NETDEV_DEV(ndev, &pdev->dev);\n+\tplatform_set_drvdata(pdev, priv);\n+\tpriv->dev = &pdev->dev;\n+\n+\tpriv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |\n+\t\t\t NETIF_MSG_LINK | NETIF_MSG_PROBE;\n+\n+\tmac = of_get_mac_address(pdev->dev.of_node);\n+\tif (mac)\n+\t\tether_addr_copy(ndev->dev_addr, mac);\n+\n+\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\t\teth_hw_addr_random(ndev);\n+\t\tdev_warn(&pdev->dev, \"No MAC address found, using random\\n\");\n+\t}\n+\n+\tpriv->phy_np = of_parse_phandle(pdev->dev.of_node, \"phy-handle\", 0);\n+\tif (!priv->phy_np) {\n+\t\tnetif_err(priv, probe, ndev, \"missing phy in DT\\n\");\n+\t\tgoto err1;\n+\t}\n+\n+\tpriv->phy_interface = of_get_phy_mode(pdev->dev.of_node);\n+\tif (priv->phy_interface < 0) {\n+\t\tnetif_err(priv, probe, ndev,\n+\t\t\t \"%s: bad phy-if\\n\", __func__);\n+\t\tgoto err1;\n+\t}\n+\n+\tpriv->ioaddr = of_iomap(priv->dev->of_node, 0);\n+\tif (!priv->ioaddr) {\n+\t\tnetif_err(priv, probe, ndev, \"of_iomap() failed\\n\");\n+\t\terr = -EINVAL;\n+\t\tgoto err1;\n+\t}\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\tif (!res) {\n+\t\tnetif_err(priv, probe, ndev,\n+\t\t\t \"Missing rdlar resource\\n\");\n+\t\tgoto err1;\n+\t}\n+\tpriv->rdlar_pa = res->start;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 2);\n+\tif (!res) {\n+\t\tnetif_err(priv, probe, ndev,\n+\t\t\t \"Missing tdlar resource\\n\");\n+\t\tgoto err1;\n+\t}\n+\tpriv->tdlar_pa = res->start;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);\n+\tif (!res) {\n+\t\tnetif_err(priv, probe, ndev,\n+\t\t\t \"Missing IRQ resource\\n\");\n+\t\tgoto err2;\n+\t}\n+\tndev->irq = res->start;\n+\n+\twhile (priv->clock_count < ARRAY_SIZE(priv->clk)) {\n+\t\tpriv->clk[priv->clock_count] =\n+\t\t\tof_clk_get(pdev->dev.of_node, priv->clock_count);\n+\t\tif (IS_ERR(priv->clk[priv->clock_count])) {\n+\t\t\tif (!priv->clock_count) {\n+\t\t\t\tnetif_err(priv, probe, ndev,\n+\t\t\t\t\t \"Failed to get clock\\n\");\n+\t\t\t\tgoto err3;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\t\tpriv->clock_count++;\n+\t}\n+\n+\t/* disable by default */\n+\tpriv->et_coalesce.rx_coalesce_usecs = 0;\n+\tpriv->et_coalesce.rx_max_coalesced_frames = 1;\n+\tpriv->et_coalesce.tx_coalesce_usecs = 0;\n+\tpriv->et_coalesce.tx_max_coalesced_frames = 1;\n+\n+\tuse_jumbo = of_property_read_bool(pdev->dev.of_node, \"use-jumbo\");\n+\tpriv->param.use_jumbo_pkt_flag = use_jumbo;\n+\n+\tif (priv->param.use_jumbo_pkt_flag)\n+\t\tpriv->rx_pkt_buf_len = NETSEC_RX_JUMBO_PKT_BUF_LEN;\n+\telse\n+\t\tpriv->rx_pkt_buf_len = NETSEC_RX_PKT_BUF_LEN;\n+\n+\tpm_runtime_enable(&pdev->dev);\n+\t/* runtime_pm coverage just for probe, open/close also cover it */\n+\tpm_runtime_get_sync(&pdev->dev);\n+\n+\thw_ver = netsec_readl(priv, NETSEC_REG_F_TAIKI_VER);\n+\t/* this driver only supports F_TAIKI style NETSEC */\n+\tif (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=\n+\t NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {\n+\t\tret = -ENODEV;\n+\t\tgoto err3;\n+\t}\n+\n+\tdev_info(&pdev->dev, \"IP rev %d.%d\\n\", hw_ver >> 16, hw_ver & 0xffff);\n+\n+\tpriv->mac_mode.flow_start_th = NETSEC_FLOW_CONTROL_START_THRESHOLD;\n+\tpriv->mac_mode.flow_stop_th = NETSEC_FLOW_CONTROL_STOP_THRESHOLD;\n+\tpriv->mac_mode.pause_time = pause_time;\n+\tpriv->mac_mode.flow_ctrl_enable_flag = false;\n+\tpriv->freq = clk_get_rate(priv->clk[0]);\n+\n+\tnetif_napi_add(ndev, &priv->napi, netsec_netdev_napi_poll,\n+\t\t napi_weight);\n+\n+\t/* MTU range */\n+\tndev->min_mtu = ETH_MIN_MTU;\n+\tndev->max_mtu = NETSEC_RX_JUMBO_PKT_BUF_LEN;\n+\n+\tndev->netdev_ops = &netsec_netdev_ops;\n+\tndev->ethtool_ops = &netsec_ethtool_ops;\n+\tndev->features = NETIF_F_SG | NETIF_F_IP_CSUM |\n+\t\t\t NETIF_F_IPV6_CSUM | NETIF_F_TSO |\n+\t\t\t NETIF_F_TSO6 | NETIF_F_GSO |\n+\t\t\t NETIF_F_HIGHDMA | NETIF_F_RXCSUM;\n+\tndev->hw_features = ndev->features;\n+\n+\tpriv->rx_cksum_offload_flag = true;\n+\tspin_lock_init(&priv->tx_queue_lock);\n+\n+\terr = netsec_mii_register(priv);\n+\tif (err) {\n+\t\tnetif_err(priv, probe, ndev,\n+\t\t\t \"mii bus registration failed %d\\n\", err);\n+\t\tgoto err3;\n+\t}\n+\n+\t/* disable all other interrupt sources */\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_CLR, ~0);\n+\tnetsec_writel(priv, NETSEC_REG_INTEN_SET,\n+\t\t NETSEC_IRQ_TX | NETSEC_IRQ_RX);\n+\n+\terr = register_netdev(ndev);\n+\tif (err) {\n+\t\tnetif_err(priv, probe, ndev, \"register_netdev() failed\\n\");\n+\t\tgoto err4;\n+\t}\n+\n+\tpm_runtime_put_sync_suspend(&pdev->dev);\n+\n+\tnetif_info(priv, probe, ndev, \"initialized\\n\");\n+\n+\treturn 0;\n+\n+err4:\n+\tnetsec_mii_unregister(priv);\n+\n+err3:\n+\tpm_runtime_put_sync_suspend(&pdev->dev);\n+\tpm_runtime_disable(&pdev->dev);\n+\twhile (priv->clock_count > 0) {\n+\t\tpriv->clock_count--;\n+\t\tclk_put(priv->clk[priv->clock_count]);\n+\t}\n+err2:\n+\tiounmap(priv->ioaddr);\n+err1:\n+\tfree_netdev(ndev);\n+\n+\tdev_err(&pdev->dev, \"init failed\\n\");\n+\n+\treturn ret;\n+}\n+\n+static int netsec_remove(struct platform_device *pdev)\n+{\n+\tstruct netsec_priv *priv = platform_get_drvdata(pdev);\n+\n+\tunregister_netdev(priv->ndev);\n+\tnetsec_mii_unregister(priv);\n+\tpm_runtime_disable(&pdev->dev);\n+\tiounmap(priv->ioaddr);\n+\tfree_netdev(priv->ndev);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_PM\n+static int netsec_runtime_suspend(struct device *dev)\n+{\n+\tstruct netsec_priv *priv = dev_get_drvdata(dev);\n+\tint n;\n+\n+\tnetif_dbg(priv, drv, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (priv->irq_registered)\n+\t\tdisable_irq(priv->ndev->irq);\n+\n+\tnetsec_writel(priv, NETSEC_REG_CLK_EN, 0);\n+\n+\tfor (n = priv->clock_count - 1; n >= 0; n--)\n+\t\tclk_disable_unprepare(priv->clk[n]);\n+\n+\treturn 0;\n+}\n+\n+static int netsec_runtime_resume(struct device *dev)\n+{\n+\tstruct netsec_priv *priv = dev_get_drvdata(dev);\n+\tint n;\n+\n+\tnetif_dbg(priv, drv, priv->ndev, \"%s\\n\", __func__);\n+\n+\t/* first let the clocks back on */\n+\n+\tfor (n = 0; n < priv->clock_count; n++)\n+\t\tclk_prepare_enable(priv->clk[n]);\n+\n+\tnetsec_writel(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |\n+\t\t\tNETSEC_CLK_EN_REG_DOM_C | NETSEC_CLK_EN_REG_DOM_G);\n+\n+\tif (priv->irq_registered)\n+\t\tenable_irq(priv->ndev->irq);\n+\n+\treturn 0;\n+}\n+\n+static int netsec_pm_suspend(struct device *dev)\n+{\n+\tstruct netsec_priv *priv = dev_get_drvdata(dev);\n+\n+\tnetif_dbg(priv, drv, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (pm_runtime_status_suspended(dev))\n+\t\treturn 0;\n+\n+\treturn netsec_runtime_suspend(dev);\n+}\n+\n+static int netsec_pm_resume(struct device *dev)\n+{\n+\tstruct netsec_priv *priv = dev_get_drvdata(dev);\n+\n+\tnetif_dbg(priv, drv, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (pm_runtime_status_suspended(dev))\n+\t\treturn 0;\n+\n+\treturn netsec_runtime_resume(dev);\n+}\n+#endif\n+\n+static const struct dev_pm_ops netsec_pm_ops = {\n+\tSET_SYSTEM_SLEEP_PM_OPS(netsec_pm_suspend, netsec_pm_resume)\n+\tSET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)\n+};\n+\n+static const struct of_device_id netsec_dt_ids[] = {\n+\t{.compatible = \"socionext,netsecv5\"},\n+\t{ /* sentinel */ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, netsec_dt_ids);\n+\n+static struct platform_driver netsec_driver = {\n+\t.probe = netsec_probe,\n+\t.remove = netsec_remove,\n+\t.driver = {\n+\t\t.name = \"netsec\",\n+\t\t.of_match_table = netsec_dt_ids,\n+\t\t.pm = &netsec_pm_ops,\n+\t},\n+};\n+\n+module_platform_driver(netsec_driver);\n+\n+MODULE_AUTHOR(\"Socionext Inc\");\n+MODULE_DESCRIPTION(\"NETSEC Ethernet driver\");\n+MODULE_LICENSE(\"GPL\");\n+\n+MODULE_ALIAS(\"platform:netsec\");\n", "prefixes": [ "net-next", "PATCHv6", "2/2" ] }