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GET /api/patches/807572/?format=api
{ "id": 807572, "url": "http://patchwork.ozlabs.org/api/patches/807572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830101550.16821-3-fbarrat@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170830101550.16821-3-fbarrat@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170830101550.16821-3-fbarrat@linux.vnet.ibm.com/", "date": "2017-08-30T10:15:50", "name": "[v2,3/3] cxl: Enable global TLBIs for cxl contexts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d57b4d213e43c776a0368c5aa9166323e4a0ffa2", "submitter": { "id": 67555, "url": "http://patchwork.ozlabs.org/api/people/67555/?format=api", "name": "Frederic Barrat", "email": "fbarrat@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830101550.16821-3-fbarrat@linux.vnet.ibm.com/mbox/", "series": [ { "id": 576, "url": "http://patchwork.ozlabs.org/api/series/576/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=576", "date": "2017-08-30T10:15:48", "name": "[v2,1/3] powerpc/mm: Export flush_all_mm()", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/576/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807572/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807572/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xj1kn6x67z9s9Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 20:21:37 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xj1kn4jgPzDqRM\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 20:21:37 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xj1cQ1VD0zDqT0\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 20:16:06 +1000 (AEST)", "from pps.filterd (m0098396.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7UAFQbI087831\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 30 Aug 2017 06:16:04 -0400", "from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cnpaeb9cr-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 30 Aug 2017 06:16:03 -0400", "from localhost\n\tby e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <fbarrat@linux.vnet.ibm.com>;\n\tWed, 30 Aug 2017 11:16:01 +0100", "from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194)\n\tby e06smtp10.uk.ibm.com (192.168.101.140) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tWed, 30 Aug 2017 11:15:58 +0100", "from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com\n\t[9.149.105.59])\n\tby b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7UAFwCD24838390; Wed, 30 Aug 2017 10:15:58 GMT", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 6A0DDA4057;\n\tWed, 30 Aug 2017 11:12:26 +0100 (BST)", "from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 89C8FA4051;\n\tWed, 30 Aug 2017 11:12:25 +0100 (BST)", "from localhost.localdomain (unknown [9.164.182.241])\n\tby d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tWed, 30 Aug 2017 11:12:25 +0100 (BST)" ], "From": "Frederic Barrat <fbarrat@linux.vnet.ibm.com>", "To": "mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,\n\tbenh@kernel.crashing.org, andrew.donnellan@au1.ibm.com,\n\tclombard@linux.vnet.ibm.com, vaibhav@linux.vnet.ibm.com", "Subject": "[PATCH v2 3/3] cxl: Enable global TLBIs for cxl contexts", "Date": "Wed, 30 Aug 2017 12:15:50 +0200", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170830101550.16821-1-fbarrat@linux.vnet.ibm.com>", "References": "<20170830101550.16821-1-fbarrat@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17083010-0040-0000-0000-000003D4557E", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17083010-0041-0000-0000-000025D4C546", "Message-Id": "<20170830101550.16821-3-fbarrat@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-30_04:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708300154", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "alistair@popple.id.au", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The PSL and nMMU need to see all TLB invalidations for the memory\ncontexts used on the adapter. For the hash memory model, it is done by\nmaking all TLBIs global as soon as the cxl driver is in use. For\nradix, we need something similar, but we can refine and only convert\nto global the invalidations for contexts actually used by the device.\n\nSo increment the 'active_cpus' count for the contexts attached to the\ncxl adapter. As soon as there's more than 1 active cpu, the TLBIs for\nthe context become global. Active cpu count must be decremented when\ndetaching to restore locality if possible and to avoid overflowing the\ncounter.\n\nSigned-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>\n---\nChangelog:\nv2: Replace flush_tlb_mm() by the new flush_all_mm() to flush the TLBs\nand PWCs (thanks to Ben)\n\n arch/powerpc/include/asm/mmu_context.h | 35 ++++++++++++++++++++++++++++++++++\n arch/powerpc/mm/mmu_context.c | 9 ---------\n drivers/misc/cxl/api.c | 22 ++++++++++++++++++---\n drivers/misc/cxl/context.c | 3 +++\n drivers/misc/cxl/file.c | 19 ++++++++++++++++--\n 5 files changed, 74 insertions(+), 14 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h\nindex 309592589e30..71a1d01ff206 100644\n--- a/arch/powerpc/include/asm/mmu_context.h\n+++ b/arch/powerpc/include/asm/mmu_context.h\n@@ -77,6 +77,41 @@ extern void switch_cop(struct mm_struct *next);\n extern int use_cop(unsigned long acop, struct mm_struct *mm);\n extern void drop_cop(unsigned long acop, struct mm_struct *mm);\n \n+#ifdef CONFIG_PPC_BOOK3S_64\n+static inline void inc_mm_active_cpus(struct mm_struct *mm)\n+{\n+\tatomic_inc(&mm->context.active_cpus);\n+}\n+\n+static inline void dec_mm_active_cpus(struct mm_struct *mm)\n+{\n+\tatomic_dec(&mm->context.active_cpus);\n+}\n+\n+static inline void mm_context_add_copro(struct mm_struct *mm)\n+{\n+\tinc_mm_active_cpus(mm);\n+}\n+\n+static inline void mm_context_remove_copro(struct mm_struct *mm)\n+{\n+\t/*\n+\t * Need to broadcast a global flush of the full mm before\n+\t * decrementing active_cpus count, as the next TLBI may be\n+\t * local and the nMMU and/or PSL need to be cleaned up.\n+\t * Should be rare enough so that it's acceptable.\n+\t */\n+\tflush_all_mm(mm);\n+\tdec_mm_active_cpus(mm);\n+}\n+#else\n+static inline void inc_mm_active_cpus(struct mm_struct *mm) { }\n+static inline void dec_mm_active_cpus(struct mm_struct *mm) { }\n+static inline void mm_context_add_copro(struct mm_struct *mm) { }\n+static inline void mm_context_remove_copro(struct mm_struct *mm) { }\n+#endif\n+\n+\n extern void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,\n \t\t\t struct task_struct *tsk);\n \ndiff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c\nindex 0f613bc63c50..d60a62bf4fc7 100644\n--- a/arch/powerpc/mm/mmu_context.c\n+++ b/arch/powerpc/mm/mmu_context.c\n@@ -34,15 +34,6 @@ static inline void switch_mm_pgdir(struct task_struct *tsk,\n \t\t\t\t struct mm_struct *mm) { }\n #endif\n \n-#ifdef CONFIG_PPC_BOOK3S_64\n-static inline void inc_mm_active_cpus(struct mm_struct *mm)\n-{\n-\tatomic_inc(&mm->context.active_cpus);\n-}\n-#else\n-static inline void inc_mm_active_cpus(struct mm_struct *mm) { }\n-#endif\n-\n void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,\n \t\t\tstruct task_struct *tsk)\n {\ndiff --git a/drivers/misc/cxl/api.c b/drivers/misc/cxl/api.c\nindex a0c44d16bf30..1137a2cc1d3e 100644\n--- a/drivers/misc/cxl/api.c\n+++ b/drivers/misc/cxl/api.c\n@@ -15,6 +15,7 @@\n #include <linux/module.h>\n #include <linux/mount.h>\n #include <linux/sched/mm.h>\n+#include <linux/mmu_context.h>\n \n #include \"cxl.h\"\n \n@@ -331,9 +332,12 @@ int cxl_start_context(struct cxl_context *ctx, u64 wed,\n \t\t/* ensure this mm_struct can't be freed */\n \t\tcxl_context_mm_count_get(ctx);\n \n-\t\t/* decrement the use count */\n-\t\tif (ctx->mm)\n+\t\tif (ctx->mm) {\n+\t\t\t/* decrement the use count from above */\n \t\t\tmmput(ctx->mm);\n+\t\t\t/* make TLBIs for this context global */\n+\t\t\tmm_context_add_copro(ctx->mm);\n+\t\t}\n \t}\n \n \t/*\n@@ -342,13 +346,25 @@ int cxl_start_context(struct cxl_context *ctx, u64 wed,\n \t */\n \tcxl_ctx_get();\n \n+\t/*\n+\t * Barrier is needed to make sure all TLBIs are global before\n+\t * we attach and the context starts being used by the adapter.\n+\t *\n+\t * Needed after mm_context_add_copro() for radix and\n+\t * cxl_ctx_get() for hash/p8\n+\t */\n+\tsmp_mb();\n+\n \tif ((rc = cxl_ops->attach_process(ctx, kernel, wed, 0))) {\n \t\tput_pid(ctx->pid);\n \t\tctx->pid = NULL;\n \t\tcxl_adapter_context_put(ctx->afu->adapter);\n \t\tcxl_ctx_put();\n-\t\tif (task)\n+\t\tif (task) {\n \t\t\tcxl_context_mm_count_put(ctx);\n+\t\t\tif (ctx->mm)\n+\t\t\t\tmm_context_remove_copro(ctx->mm);\n+\t\t}\n \t\tgoto out;\n \t}\n \ndiff --git a/drivers/misc/cxl/context.c b/drivers/misc/cxl/context.c\nindex 8c32040b9c09..12a41b2753f0 100644\n--- a/drivers/misc/cxl/context.c\n+++ b/drivers/misc/cxl/context.c\n@@ -18,6 +18,7 @@\n #include <linux/slab.h>\n #include <linux/idr.h>\n #include <linux/sched/mm.h>\n+#include <linux/mmu_context.h>\n #include <asm/cputable.h>\n #include <asm/current.h>\n #include <asm/copro.h>\n@@ -267,6 +268,8 @@ int __detach_context(struct cxl_context *ctx)\n \n \t/* Decrease the mm count on the context */\n \tcxl_context_mm_count_put(ctx);\n+\tif (ctx->mm)\n+\t\tmm_context_remove_copro(ctx->mm);\n \tctx->mm = NULL;\n \n \treturn 0;\ndiff --git a/drivers/misc/cxl/file.c b/drivers/misc/cxl/file.c\nindex 4bfad9f6dc9f..84b801b5d0e5 100644\n--- a/drivers/misc/cxl/file.c\n+++ b/drivers/misc/cxl/file.c\n@@ -19,6 +19,7 @@\n #include <linux/mm.h>\n #include <linux/slab.h>\n #include <linux/sched/mm.h>\n+#include <linux/mmu_context.h>\n #include <asm/cputable.h>\n #include <asm/current.h>\n #include <asm/copro.h>\n@@ -220,9 +221,12 @@ static long afu_ioctl_start_work(struct cxl_context *ctx,\n \t/* ensure this mm_struct can't be freed */\n \tcxl_context_mm_count_get(ctx);\n \n-\t/* decrement the use count */\n-\tif (ctx->mm)\n+\tif (ctx->mm) {\n+\t\t/* decrement the use count from above */\n \t\tmmput(ctx->mm);\n+\t\t/* make TLBIs for this context global */\n+\t\tmm_context_add_copro(ctx->mm);\n+\t}\n \n \t/*\n \t * Increment driver use count. Enables global TLBIs for hash\n@@ -230,6 +234,15 @@ static long afu_ioctl_start_work(struct cxl_context *ctx,\n \t */\n \tcxl_ctx_get();\n \n+\t/*\n+\t * Barrier is needed to make sure all TLBIs are global before\n+\t * we attach and the context starts being used by the adapter.\n+\t *\n+\t * Needed after mm_context_add_copro() for radix and\n+\t * cxl_ctx_get() for hash/p8\n+\t */\n+\tsmp_mb();\n+\n \ttrace_cxl_attach(ctx, work.work_element_descriptor, work.num_interrupts, amr);\n \n \tif ((rc = cxl_ops->attach_process(ctx, false, work.work_element_descriptor,\n@@ -240,6 +253,8 @@ static long afu_ioctl_start_work(struct cxl_context *ctx,\n \t\tctx->pid = NULL;\n \t\tcxl_ctx_put();\n \t\tcxl_context_mm_count_put(ctx);\n+\t\tif (ctx->mm)\n+\t\t\tmm_context_remove_copro(ctx->mm);\n \t\tgoto out;\n \t}\n \n", "prefixes": [ "v2", "3/3" ] }