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GET /api/patches/807489/?format=api
{ "id": 807489, "url": "http://patchwork.ozlabs.org/api/patches/807489/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830082702.3011-13-Sergio.G.DelReal@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830082702.3011-13-Sergio.G.DelReal@gmail.com>", "list_archive_url": null, "date": "2017-08-30T08:27:01", "name": "[v2,12/13] hvf: refactor event injection code for hvf", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f3c56bf23a04c80c014c3c00f3036762045801d2", "submitter": { "id": 70675, "url": "http://patchwork.ozlabs.org/api/people/70675/?format=api", "name": "Sergio Andres Gomez Del Real", "email": "sergio.g.delreal@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830082702.3011-13-Sergio.G.DelReal@gmail.com/mbox/", "series": [ { "id": 548, "url": "http://patchwork.ozlabs.org/api/series/548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=548", "date": "2017-08-30T08:26:49", "name": "add support for Hypervisor.framework in QEMU", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/548/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807489/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807489/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"FXvFt0Zh\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhzPC5R6dz9sRq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 18:36:15 +1000 (AEST)", "from localhost ([::1]:49018 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmyTt-0000en-7b\n\tfor incoming@patchwork.ozlabs.org; Wed, 30 Aug 2017 04:36:13 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:60613)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dmyLt-0002gC-NO\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:59 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dmyLo-0000Rd-PK\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:57 -0400", "from mail-ua0-x241.google.com ([2607:f8b0:400c:c08::241]:36834)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sergio.g.delreal@gmail.com>)\n\tid 1dmyLo-0000RO-KH\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:52 -0400", "by mail-ua0-x241.google.com with SMTP id y50so2343537uay.3\n\tfor <qemu-devel@nongnu.org>; Wed, 30 Aug 2017 01:27:52 -0700 (PDT)", "from localhost.localdomain ([191.109.6.85])\n\tby smtp.gmail.com with ESMTPSA id\n\th74sm1079197vka.8.2017.08.30.01.27.50\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 30 Aug 2017 01:27:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=ZIoZdBTzJ9H0gTkrnKYADQv2unG3u7/JnkNWM+c5q3g=;\n\tb=FXvFt0ZhFgCdgHPKbdq9L+wLZvX5BcFFCJ3gZJ/JEuotK83HRqmui+KFpFzSU63B0o\n\tfWB8pNsmSAyK5A18C2JRTeeIWxfdhaIKu6tyENtuM0Qt7k1dv9167zErYHMW+8RWzp7s\n\t+41kbE+YgDUj/qny7d7TSuc0NKgZfi1UITeLgeNmF7yi4uP1qrkEnY735MJ63ssiCt4o\n\tkBoGuH27pon6c8olfVr6+wMvTVBa0nysI1S2qwqIdQWCxuxMh1IABgZOLdklmdfFtZDb\n\tsqRUAgPV5wtqmmb/+LofwCgPiVIkze8rwI3vHggV/LUAtqf7lD/V/G+QdyiBwl72nHoR\n\tplIg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ZIoZdBTzJ9H0gTkrnKYADQv2unG3u7/JnkNWM+c5q3g=;\n\tb=MSqvuuhzgKS0c4muupvkGg0uVa5J5MhtDJe0p+/jFIDhslEGFGoQLtX3FxVY8uNFqO\n\torm2gPDI1UNdmjSal85H6eDw0bakB4O1aY6xd44vSbA3NUgAoB9G4Y3clVUsH0qVSsB4\n\tHafSXx3VlqgQ/dSuBL/yrLM5MTQ29SHtEXji8+97Q+vTp/aeW6N/kQVL30gKWz3Bd8pp\n\t5idS0JR+dzWdterlfYzBqZ00pTv1EP+gu1yv++OvlxGIecnRVPjwOso8eF6c5H0xczu4\n\tOd0iRbbYkyP0xgFwgbKA/T1B7hBLrNe86b3RmtEp/yGS7iYaXR+QGYhUeFZvWkE6QD6u\n\t0JPA==", "X-Gm-Message-State": "AHPjjUizWRdt5h1/rkAL+1ZK+QedUwXbrZNecZSzrAR61+ftH0vGIzKZ\n\t7S4OLGqNCsdDN3ic", "X-Received": "by 10.159.50.78 with SMTP id y14mr482255uad.123.1504081671822;\n\tWed, 30 Aug 2017 01:27:51 -0700 (PDT)", "From": "Sergio Andres Gomez Del Real <sergio.g.delreal@gmail.com>", "X-Google-Original-From": "Sergio Andres Gomez Del Real\n\t<Sergio.G.DelReal@gmail.com>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 30 Aug 2017 03:27:01 -0500", "Message-Id": "<20170830082702.3011-13-Sergio.G.DelReal@gmail.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170830082702.3011-1-Sergio.G.DelReal@gmail.com>", "References": "<20170830082702.3011-1-Sergio.G.DelReal@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400c:c08::241", "Subject": "[Qemu-devel] [PATCH v2 12/13] hvf: refactor event injection code\n\tfor hvf", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This commit refactors the event-injection code for hvf through using the\nappropriate fields already provided by CPUX86State. At vmexit, it fills\nthese fields so that hvf_inject_interrupts can just retrieve them without\ncalling into hvf.\n\nSigned-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>\n---\n target/i386/cpu.c | 3 ++\n target/i386/hvf-all.c | 57 ++++++++++++++++++++++++++++++++++----\n target/i386/hvf-utils/vmcs.h | 3 ++\n target/i386/hvf-utils/vmx.h | 8 ++++++\n target/i386/hvf-utils/x86hvf.c | 63 ++++++++++++++++++++----------------------\n target/i386/kvm.c | 2 --\n 6 files changed, 96 insertions(+), 40 deletions(-)", "diff": "diff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex 01957411bd..63d960ceb3 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -3251,6 +3251,9 @@ static void x86_cpu_reset(CPUState *s)\n memset(env->mtrr_var, 0, sizeof(env->mtrr_var));\n memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));\n \n+ env->interrupt_injected = -1;\n+ env->exception_injected = -1;\n+ env->nmi_injected = false;\n #if !defined(CONFIG_USER_ONLY)\n /* We hard-wire the BSP to the first CPU. */\n apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);\ndiff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c\nindex b3885e5f84..430affd9ce 100644\n--- a/target/i386/hvf-all.c\n+++ b/target/i386/hvf-all.c\n@@ -762,6 +762,55 @@ void hvf_disable(int shouldDisable)\n hvf_disabled = shouldDisable;\n }\n \n+static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info)\n+{\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+\n+ env->exception_injected = -1;\n+ env->interrupt_injected = -1;\n+ env->nmi_injected = false;\n+ if (idtvec_info & VMCS_IDT_VEC_VALID) {\n+ switch (idtvec_info & VMCS_IDT_VEC_TYPE) {\n+ case VMCS_IDT_VEC_HWINTR:\n+ case VMCS_IDT_VEC_SWINTR:\n+ env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;\n+ break;\n+ case VMCS_IDT_VEC_NMI:\n+ env->nmi_injected = true;\n+ break;\n+ case VMCS_IDT_VEC_HWEXCEPTION:\n+ case VMCS_IDT_VEC_SWEXCEPTION:\n+ env->exception_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;\n+ break;\n+ case VMCS_IDT_VEC_PRIV_SWEXCEPTION:\n+ default:\n+ abort();\n+ }\n+ if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION ||\n+ (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) {\n+ env->ins_len = ins_len;\n+ }\n+ if (idtvec_info & VMCS_INTR_DEL_ERRCODE) {\n+ env->has_error_code = true;\n+ env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR);\n+ }\n+ }\n+ if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &\n+ VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {\n+ env->hflags2 |= HF2_NMI_MASK;\n+ } else {\n+ env->hflags2 &= ~HF2_NMI_MASK;\n+ }\n+ if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &\n+ (VMCS_INTERRUPTIBILITY_STI_BLOCKING |\n+ VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {\n+ env->hflags |= HF_INHIBIT_IRQ_MASK;\n+ } else {\n+ env->hflags &= ~HF_INHIBIT_IRQ_MASK;\n+ }\n+}\n+\n int hvf_vcpu_exec(CPUState *cpu)\n {\n X86CPU *x86_cpu = X86_CPU(cpu);\n@@ -781,11 +830,6 @@ int hvf_vcpu_exec(CPUState *cpu)\n cpu->vcpu_dirty = false;\n }\n \n- env->hvf_emul->interruptable =\n- !(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &\n- (VMCS_INTERRUPTIBILITY_STI_BLOCKING |\n- VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));\n-\n hvf_inject_interrupts(cpu);\n vmx_update_tpr(cpu);\n \n@@ -804,7 +848,10 @@ int hvf_vcpu_exec(CPUState *cpu)\n uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);\n uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd,\n VMCS_EXIT_INSTRUCTION_LENGTH);\n+\n uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);\n+\n+ hvf_store_events(cpu, ins_len, idtvec_info);\n rip = rreg(cpu->hvf_fd, HV_X86_RIP);\n RFLAGS(env) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);\n env->eflags = RFLAGS(env);\ndiff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h\nindex c410dcfaaa..0fae73dce5 100644\n--- a/target/i386/hvf-utils/vmcs.h\n+++ b/target/i386/hvf-utils/vmcs.h\n@@ -299,6 +299,7 @@\n /*\n * VMCS IDT-Vectoring information fields\n */\n+#define VMCS_IDT_VEC_VECNUM 0xFF\n #define VMCS_IDT_VEC_VALID (1U << 31)\n #define VMCS_IDT_VEC_TYPE 0x700\n #define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)\n@@ -306,6 +307,8 @@\n #define VMCS_IDT_VEC_NMI (2 << 8)\n #define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)\n #define VMCS_IDT_VEC_SWINTR (4 << 8)\n+#define VMCS_IDT_VEC_PRIV_SWEXCEPTION (5 << 8)\n+#define VMCS_IDT_VEC_SWEXCEPTION (6 << 8)\n \n /*\n * VMCS Guest interruptibility field\ndiff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h\nindex d086c8d253..6d557045a5 100644\n--- a/target/i386/hvf-utils/vmx.h\n+++ b/target/i386/hvf-utils/vmx.h\n@@ -181,6 +181,10 @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)\n \n static inline void vmx_clear_nmi_blocking(CPUState *cpu)\n {\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+\n+ env->hflags2 &= ~HF2_NMI_MASK;\n uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);\n gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;\n wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);\n@@ -188,6 +192,10 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu)\n \n static inline void vmx_set_nmi_blocking(CPUState *cpu)\n {\n+ X86CPU *x86_cpu = X86_CPU(cpu);\n+ CPUX86State *env = &x86_cpu->env;\n+\n+ env->hflags2 |= HF2_NMI_MASK;\n uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);\n gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;\n wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);\ndiff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c\nindex 8986b4e5e5..3a50548817 100644\n--- a/target/i386/hvf-utils/x86hvf.c\n+++ b/target/i386/hvf-utils/x86hvf.c\n@@ -356,50 +356,47 @@ void vmx_clear_int_window_exiting(CPUState *cpu)\n \n void hvf_inject_interrupts(CPUState *cpu_state)\n {\n- int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &\n- VMCS_INTERRUPTIBILITY_NMI_BLOCKING);\n X86CPU *x86cpu = X86_CPU(cpu_state);\n CPUX86State *env = &x86cpu->env;\n \n- uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);\n- uint64_t info = 0;\n-\n- if (idt_info & VMCS_IDT_VEC_VALID) {\n- uint8_t vector = idt_info & 0xff;\n- uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;\n- info = idt_info;\n+ uint8_t vector;\n+ uint64_t intr_type;\n+ bool have_event = true;\n+ if (env->interrupt_injected != -1) {\n+ vector = env->interrupt_injected;\n+ intr_type = VMCS_INTR_T_SWINTR;\n+ } else if (env->exception_injected != -1) {\n+ vector = env->exception_injected;\n+ if (vector == EXCP03_INT3 || vector == EXCP04_INTO) {\n+ intr_type = VMCS_INTR_T_SWEXCEPTION;\n+ } else {\n+ intr_type = VMCS_INTR_T_HWEXCEPTION;\n+ }\n+ } else if (env->nmi_injected) {\n+ vector = NMI_VEC;\n+ intr_type = VMCS_INTR_T_NMI;\n+ } else {\n+ have_event = false;\n+ }\n \n+ uint64_t info = 0;\n+ if (have_event) {\n+ info = vector | intr_type | VMCS_INTR_VALID;\n uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);\n- if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {\n- allow_nmi = 1;\n+ if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) {\n vmx_clear_nmi_blocking(cpu_state);\n }\n \n- if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {\n+ if (!(env->hflags2 & HF2_NMI_MASK) || intr_type != VMCS_INTR_T_NMI) {\n info &= ~(1 << 12); /* clear undefined bit */\n if (intr_type == VMCS_INTR_T_SWINTR ||\n- intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||\n intr_type == VMCS_INTR_T_SWEXCEPTION) {\n- uint64_t ins_len = rvmcs(cpu_state->hvf_fd,\n- VMCS_EXIT_INSTRUCTION_LENGTH);\n- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);\n- }\n- if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {\n- /*\n- * VT-x requires #BP and #OF to be injected as software\n- * exceptions.\n- */\n- info &= ~VMCS_INTR_T_MASK;\n- info |= VMCS_INTR_T_SWEXCEPTION;\n- uint64_t ins_len = rvmcs(cpu_state->hvf_fd,\n- VMCS_EXIT_INSTRUCTION_LENGTH);\n- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);\n+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);\n }\n \n- uint64_t err = 0;\n- if (idt_info & VMCS_INTR_DEL_ERRCODE) {\n- err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);\n- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);\n+ if (env->has_error_code) {\n+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR,\n+ env->error_code);\n }\n /*printf(\"reinject %lx err %d\\n\", info, err);*/\n wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);\n@@ -407,7 +404,7 @@ void hvf_inject_interrupts(CPUState *cpu_state)\n }\n \n if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {\n- if (allow_nmi && !(info & VMCS_INTR_VALID)) {\n+ if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) {\n cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;\n info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC;\n wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);\n@@ -416,7 +413,7 @@ void hvf_inject_interrupts(CPUState *cpu_state)\n }\n }\n \n- if (env->hvf_emul->interruptable &&\n+ if (!(env->hflags & HF_INHIBIT_IRQ_MASK) &&\n (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&\n (EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) {\n int line = cpu_get_pic_interrupt(&x86cpu->env);\ndiff --git a/target/i386/kvm.c b/target/i386/kvm.c\nindex 6db7783edc..a695b8cd4e 100644\n--- a/target/i386/kvm.c\n+++ b/target/i386/kvm.c\n@@ -1030,8 +1030,6 @@ void kvm_arch_reset_vcpu(X86CPU *cpu)\n {\n CPUX86State *env = &cpu->env;\n \n- env->exception_injected = -1;\n- env->interrupt_injected = -1;\n env->xcr0 = 1;\n if (kvm_irqchip_in_kernel()) {\n env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :\n", "prefixes": [ "v2", "12/13" ] }