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GET /api/patches/807480/?format=api
{ "id": 807480, "url": "http://patchwork.ozlabs.org/api/patches/807480/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830082702.3011-9-Sergio.G.DelReal@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170830082702.3011-9-Sergio.G.DelReal@gmail.com>", "list_archive_url": null, "date": "2017-08-30T08:26:57", "name": "[v2,08/13] hvf: implement hvf_get_supported_cpuid", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ded40ea4c564b4f81b954bf9cf9d064c3b32b27", "submitter": { "id": 70675, "url": "http://patchwork.ozlabs.org/api/people/70675/?format=api", "name": "Sergio Andres Gomez Del Real", "email": "sergio.g.delreal@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830082702.3011-9-Sergio.G.DelReal@gmail.com/mbox/", "series": [ { "id": 548, "url": "http://patchwork.ozlabs.org/api/series/548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=548", "date": "2017-08-30T08:26:49", "name": "add support for Hypervisor.framework in QEMU", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/548/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807480/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807480/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"YQu4SlNq\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhzL41N37z9t1t\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 18:33:32 +1000 (AEST)", "from localhost ([::1]:49005 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmyRF-0006hM-TJ\n\tfor incoming@patchwork.ozlabs.org; Wed, 30 Aug 2017 04:33:29 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:60521)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dmyLi-0002UD-JN\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:47 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dmyLh-0000OC-6a\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:46 -0400", "from mail-ua0-x244.google.com ([2607:f8b0:400c:c08::244]:33570)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sergio.g.delreal@gmail.com>)\n\tid 1dmyLh-0000Nm-1h\n\tfor qemu-devel@nongnu.org; Wed, 30 Aug 2017 04:27:45 -0400", "by mail-ua0-x244.google.com with SMTP id m24so2359752uai.0\n\tfor <qemu-devel@nongnu.org>; Wed, 30 Aug 2017 01:27:44 -0700 (PDT)", "from localhost.localdomain ([191.109.6.85])\n\tby smtp.gmail.com with ESMTPSA id\n\th74sm1079197vka.8.2017.08.30.01.27.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 30 Aug 2017 01:27:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=JDNr00+kseds7WeG3uLO8cQ8lChWzOqvMzS6dyJeg48=;\n\tb=YQu4SlNqHy2z+l+P/UCy7s9JRACx6vujYGWRJaTWNh2pDkQYJjNLryqS6Dq0Cqk7iL\n\tO5VVNg8eqo0aNUo+pfQitGLgMCw3+sqUF6By+BHrV8wE7QKfZLIrexlD8pv4aflghdiw\n\t66IOQ6KrJ1AUZy5vkAqv7+CJbWeVCNzKoTyn170w+UFyi5ujPCVr28TnRJpkuVSJh4Tb\n\t+jcHrZ4UjyHwaiUVDtZwRQTl3PxCq/pVBiWE8FU+Tz5EDV3IVC2QWHfKcqEwqPAxZdfe\n\tUbC9gRMm+rB395DiUjLAbTv/mPybwfRdusDVPvDVjyNNqXMUAONkzcAcO944tlvKPcnb\n\tKuhA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=JDNr00+kseds7WeG3uLO8cQ8lChWzOqvMzS6dyJeg48=;\n\tb=GEqy0tj7Ht33tOG+/y/ZvDITeu/biNE9YEGvraP/SGvgP3B/8EZUjAO3/yhMle242g\n\tIqPXBzA3n9mGf+tGBoxrX3hGbhdJ7M7cuQSH6yFZlWSK6i2WGas2NgZ62e+cf6c2LNQp\n\taD0Xvp+D2rhYuW3G+19gyuNoiGaERXsuYyDkNziD20fXzMcYPg/scSI6eGexqm1CWx8v\n\t/SHXQdPemKcTP4dxveo/pEeTxGDh3En2fA2PcAs9CFaqSnFoRsLI39zmdyoCD9E7L8EU\n\tF7huyu3jKQSb3ftzoBc2rFyztGPuDfW0fQJKdDvM9nIi+bOwKwb91AdC0AiNtpk3rgHE\n\t0c3w==", "X-Gm-Message-State": "AHPjjUiLwFKrg8OLOFvOyWEkwQm3/O0R4LJdWnDlfDd+RXv6PlCOEAMq\n\ti88qJBQis+EvrOVJ", "X-Received": "by 10.176.9.21 with SMTP id w21mr533524uag.100.1504081664330;\n\tWed, 30 Aug 2017 01:27:44 -0700 (PDT)", "From": "Sergio Andres Gomez Del Real <sergio.g.delreal@gmail.com>", "X-Google-Original-From": "Sergio Andres Gomez Del Real\n\t<Sergio.G.DelReal@gmail.com>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 30 Aug 2017 03:26:57 -0500", "Message-Id": "<20170830082702.3011-9-Sergio.G.DelReal@gmail.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170830082702.3011-1-Sergio.G.DelReal@gmail.com>", "References": "<20170830082702.3011-1-Sergio.G.DelReal@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400c:c08::244", "Subject": "[Qemu-devel] [PATCH v2 08/13] hvf: implement hvf_get_supported_cpuid", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This commit implements hvf_get_supported_cpuid, which returns the set of\nfeatures supported by both the host processor and the hypervisor.\n\nSigned-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>\n---\n target/i386/hvf-utils/x86_cpuid.c | 138 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 138 insertions(+)", "diff": "diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c\nindex 5d63bca8fd..6d405cd9dd 100644\n--- a/target/i386/hvf-utils/x86_cpuid.c\n+++ b/target/i386/hvf-utils/x86_cpuid.c\n@@ -24,6 +24,7 @@\n #include \"x86_cpuid.h\"\n #include \"x86.h\"\n #include \"vmx.h\"\n+#include \"sysemu/hvf.h\"\n \n #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \\\n CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \\\n@@ -94,6 +95,27 @@ struct x86_cpuid builtin_cpus[] = {\n \n static struct x86_cpuid *_cpuid;\n \n+static uint64_t xgetbv(uint32_t xcr)\n+{\n+ uint32_t eax, edx;\n+\n+ __asm__ volatile (\"xgetbv\"\n+ : \"=a\" (eax), \"=d\" (edx)\n+ : \"c\" (xcr));\n+\n+ return (((uint64_t)edx) << 32) | eax;\n+}\n+\n+static bool vmx_mpx_supported()\n+{\n+ uint64_t cap_exit, cap_entry;\n+\n+ hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cap_entry);\n+ hv_vmx_read_capability(HV_VMX_CAP_EXIT, &cap_exit);\n+\n+ return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16)));\n+}\n+\n void init_cpuid(struct CPUState *cpu)\n {\n _cpuid = &builtin_cpus[2]; /* core2duo */\n@@ -277,3 +299,119 @@ void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,\n break;\n }\n }\n+\n+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,\n+ int reg)\n+{\n+ uint64_t cap;\n+ uint32_t eax, ebx, ecx, edx;\n+\n+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);\n+\n+ switch (func) {\n+ case 0:\n+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;\n+ break;\n+ case 1:\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |\n+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;\n+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |\n+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |\n+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |\n+ CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |\n+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;\n+ break;\n+ case 6:\n+ eax = 4;\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ break;\n+ case 7:\n+ if (idx == 0) {\n+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |\n+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |\n+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |\n+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |\n+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |\n+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |\n+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |\n+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |\n+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |\n+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |\n+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |\n+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX;\n+\n+ if (!vmx_mpx_supported()) {\n+ ebx &= ~CPUID_7_0_EBX_MPX;\n+ }\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ if (!(cap & CPU_BASED2_INVPCID)) {\n+ ebx &= ~CPUID_7_0_EBX_INVPCID;\n+ }\n+\n+ ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;\n+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;\n+ } else {\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ }\n+ eax = 0;\n+ break;\n+ case 0xD:\n+ if (idx == 0) {\n+ uint64_t host_xcr0 = xgetbv(0);\n+ uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK |\n+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK |\n+ XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |\n+ XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK);\n+ eax &= supp_xcr0;\n+ if (!vmx_mpx_supported()) {\n+ eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK);\n+ }\n+ } else if (idx == 1) {\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;\n+ if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) {\n+ eax &= ~CPUID_XSAVE_XSAVES;\n+ }\n+ }\n+ break;\n+ case 0x80000001:\n+ /* LM only if HVF in 64-bit mode */\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |\n+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |\n+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);\n+ if (!(cap & CPU_BASED_TSC_OFFSET)) {\n+ edx &= ~CPUID_EXT2_RDTSCP;\n+ }\n+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |\n+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |\n+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |\n+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;\n+ break;\n+ default:\n+ return 0;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\n", "prefixes": [ "v2", "08/13" ] }