Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/807408/?format=api
{ "id": 807408, "url": "http://patchwork.ozlabs.org/api/patches/807408/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-17-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504066360-30128-17-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504066360-30128-17-git-send-email-paulus@ozlabs.org/", "date": "2017-08-30T04:12:39", "name": "[v3,16/17] powerpc: Separate out load/store emulation into its own function", "commit_ref": "a53d5182e24c22986ad0e99e52f8fe343ee7d7ac", "pull_url": null, "state": "accepted", "archived": false, "hash": "e8c845d20660b0b9fec430dd8f2b503441b0cddf", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-17-git-send-email-paulus@ozlabs.org/mbox/", "series": [ { "id": 522, "url": "http://patchwork.ozlabs.org/api/series/522/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=522", "date": "2017-08-30T04:12:25", "name": "powerpc: Do alignment fixups using analyse_instr etc.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/522/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807408/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807408/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhtFs4tYYz9sN7\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:44:33 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhtFs3jNHzDq5b\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:44:33 +1000 (AEST)", "from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYK6vLlzDqGG\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 14:12:53 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhsYK67gfz9sP5; Wed, 30 Aug 2017 14:12:53 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xhsYK4xWyz9sNc\n\tfor <linuxppc-dev@ozlabs.org>; Wed, 30 Aug 2017 14:12:53 +1000 (AEST)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"jOclku97\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"jOclku97\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"jOclku97\"; \n\tdkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066373; bh=I6nfHL12hkmBhObSmAw15gulAL9YvVeLHeIM+Ya48zA=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=jOclku97QAmZw1pDFeBlYlWNhUH/sk157Bz2+m2Wa4uGicRkYJizKhG0tXLg4u6TU\n\tAXlqtAqboL0BR4GGAswiV5Lh/fUXhjWBBx9LK+pqsg0PPZ84Mm3eJS6pThfET1rCiz\n\t1t9TNvPE6SG1anQ1B3Q4MKowTkwRqU+jZ7KEeZ4U82PLrAoGrQbwqgEX3Z5t9qGorW\n\tQCTgPFO0zZrQZi9SoIP6XbYChzk5p7A6nMGAQsS+FsvATTDwrXSdbaTYbjXNlmUt3s\n\tNkZf3AL9PbHembDNLbXEntWYcnXK+z+OR29eacH2e2JOxapJAUhex57upqAVeTsU2L\n\tQlEdsN5kWW8YA==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v3 16/17] powerpc: Separate out load/store emulation into its\n\town function", "Date": "Wed, 30 Aug 2017 14:12:39 +1000", "Message-Id": "<1504066360-30128-17-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "References": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This moves the parts of emulate_step() that deal with emulating\nload and store instructions into a new function called\nemulate_loadstore(). This is to make it possible to reuse this\ncode in the alignment handler.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/include/asm/sstep.h | 9 ++\n arch/powerpc/lib/sstep.c | 258 ++++++++++++++++++++++-----------------\n 2 files changed, 154 insertions(+), 113 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h\nindex 958c2c5..309d1c5 100644\n--- a/arch/powerpc/include/asm/sstep.h\n+++ b/arch/powerpc/include/asm/sstep.h\n@@ -152,6 +152,15 @@ void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);\n */\n extern int emulate_step(struct pt_regs *regs, unsigned int instr);\n \n+/*\n+ * Emulate a load or store instruction by reading/writing the\n+ * memory of the current process. FP/VMX/VSX registers are assumed\n+ * to hold live values if the appropriate enable bit in regs->msr is\n+ * set; otherwise this will use the saved values in the thread struct\n+ * for user-mode accesses.\n+ */\n+extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op);\n+\n extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n \t\t\t const void *mem, bool cross_endian);\n extern void emulate_vsx_store(struct instruction_op *op,\ndiff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 810b5f2..24031ca 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -2667,76 +2667,35 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)\n }\n \n /*\n- * Emulate instructions that cause a transfer of control,\n- * loads and stores, and a few other instructions.\n- * Returns 1 if the step was emulated, 0 if not,\n- * or -1 if the instruction is one that should not be stepped,\n- * such as an rfid, or a mtmsrd that would clear MSR_RI.\n+ * Emulate a previously-analysed load or store instruction.\n+ * Return values are:\n+ * 0 = instruction emulated successfully\n+ * -EFAULT = address out of range or access faulted (regs->dar\n+ *\t contains the faulting address)\n+ * -EACCES = misaligned access, instruction requires alignment\n+ * -EINVAL = unknown operation in *op\n */\n-int emulate_step(struct pt_regs *regs, unsigned int instr)\n+int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)\n {\n-\tstruct instruction_op op;\n-\tint r, err, size, type;\n-\tunsigned long val;\n-\tunsigned int cr;\n+\tint err, size, type;\n \tint i, rd, nb;\n+\tunsigned int cr;\n+\tunsigned long val;\n \tunsigned long ea;\n \tbool cross_endian;\n \n-\tr = analyse_instr(&op, regs, instr);\n-\tif (r < 0)\n-\t\treturn r;\n-\tif (r > 0) {\n-\t\temulate_update_regs(regs, &op);\n-\t\treturn 0;\n-\t}\n-\n \terr = 0;\n-\tsize = GETSIZE(op.type);\n-\ttype = op.type & INSTR_TYPE_MASK;\n+\tsize = GETSIZE(op->type);\n+\ttype = op->type & INSTR_TYPE_MASK;\n \tcross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);\n-\n-\tea = op.ea;\n-\tif (OP_IS_LOAD_STORE(type) || type == CACHEOP)\n-\t\tea = truncate_if_32bit(regs->msr, op.ea);\n+\tea = truncate_if_32bit(regs->msr, op->ea);\n \n \tswitch (type) {\n-\tcase CACHEOP:\n-\t\tif (!address_ok(regs, ea, 8))\n-\t\t\treturn 0;\n-\t\tswitch (op.type & CACHEOP_MASK) {\n-\t\tcase DCBST:\n-\t\t\t__cacheop_user_asmx(ea, err, \"dcbst\");\n-\t\t\tbreak;\n-\t\tcase DCBF:\n-\t\t\t__cacheop_user_asmx(ea, err, \"dcbf\");\n-\t\t\tbreak;\n-\t\tcase DCBTST:\n-\t\t\tif (op.reg == 0)\n-\t\t\t\tprefetchw((void *) ea);\n-\t\t\tbreak;\n-\t\tcase DCBT:\n-\t\t\tif (op.reg == 0)\n-\t\t\t\tprefetch((void *) ea);\n-\t\t\tbreak;\n-\t\tcase ICBI:\n-\t\t\t__cacheop_user_asmx(ea, err, \"icbi\");\n-\t\t\tbreak;\n-\t\tcase DCBZ:\n-\t\t\terr = emulate_dcbz(ea, regs);\n-\t\t\tbreak;\n-\t\t}\n-\t\tif (err) {\n-\t\t\tregs->dar = ea;\n-\t\t\treturn 0;\n-\t\t}\n-\t\tgoto instr_done;\n-\n \tcase LARX:\n \t\tif (ea & (size - 1))\n-\t\t\tbreak;\t\t/* can't handle misaligned */\n+\t\t\treturn -EACCES;\t\t/* can't handle misaligned */\n \t\tif (!address_ok(regs, ea, size))\n-\t\t\treturn 0;\n+\t\t\treturn -EFAULT;\n \t\terr = 0;\n \t\tswitch (size) {\n #ifdef __powerpc64__\n@@ -2755,49 +2714,49 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\t__get_user_asmx(val, ea, err, \"ldarx\");\n \t\t\tbreak;\n \t\tcase 16:\n-\t\t\terr = do_lqarx(ea, ®s->gpr[op.reg]);\n+\t\t\terr = do_lqarx(ea, ®s->gpr[op->reg]);\n \t\t\tbreak;\n #endif\n \t\tdefault:\n-\t\t\treturn 0;\n+\t\t\treturn -EINVAL;\n \t\t}\n \t\tif (err) {\n \t\t\tregs->dar = ea;\n-\t\t\treturn 0;\n+\t\t\tbreak;\n \t\t}\n \t\tif (size < 16)\n-\t\t\tregs->gpr[op.reg] = val;\n-\t\tgoto ldst_done;\n+\t\t\tregs->gpr[op->reg] = val;\n+\t\tbreak;\n \n \tcase STCX:\n \t\tif (ea & (size - 1))\n-\t\t\tbreak;\t\t/* can't handle misaligned */\n+\t\t\treturn -EACCES;\t\t/* can't handle misaligned */\n \t\tif (!address_ok(regs, ea, size))\n-\t\t\treturn 0;\n+\t\t\treturn -EFAULT;\n \t\terr = 0;\n \t\tswitch (size) {\n #ifdef __powerpc64__\n \t\tcase 1:\n-\t\t\t__put_user_asmx(op.val, ea, err, \"stbcx.\", cr);\n+\t\t\t__put_user_asmx(op->val, ea, err, \"stbcx.\", cr);\n \t\t\tbreak;\n \t\tcase 2:\n-\t\t\t__put_user_asmx(op.val, ea, err, \"stbcx.\", cr);\n+\t\t\t__put_user_asmx(op->val, ea, err, \"stbcx.\", cr);\n \t\t\tbreak;\n #endif\n \t\tcase 4:\n-\t\t\t__put_user_asmx(op.val, ea, err, \"stwcx.\", cr);\n+\t\t\t__put_user_asmx(op->val, ea, err, \"stwcx.\", cr);\n \t\t\tbreak;\n #ifdef __powerpc64__\n \t\tcase 8:\n-\t\t\t__put_user_asmx(op.val, ea, err, \"stdcx.\", cr);\n+\t\t\t__put_user_asmx(op->val, ea, err, \"stdcx.\", cr);\n \t\t\tbreak;\n \t\tcase 16:\n-\t\t\terr = do_stqcx(ea, regs->gpr[op.reg],\n-\t\t\t\t regs->gpr[op.reg + 1], &cr);\n+\t\t\terr = do_stqcx(ea, regs->gpr[op->reg],\n+\t\t\t\t regs->gpr[op->reg + 1], &cr);\n \t\t\tbreak;\n #endif\n \t\tdefault:\n-\t\t\treturn 0;\n+\t\t\treturn -EINVAL;\n \t\t}\n \t\tif (!err)\n \t\t\tregs->ccr = (regs->ccr & 0x0fffffff) |\n@@ -2805,23 +2764,23 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\t\t((regs->xer >> 3) & 0x10000000);\n \t\telse\n \t\t\tregs->dar = ea;\n-\t\tgoto ldst_done;\n+\t\tbreak;\n \n \tcase LOAD:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_lq(regs, ea, op.reg, cross_endian);\n-\t\t\tgoto ldst_done;\n+\t\t\terr = emulate_lq(regs, ea, op->reg, cross_endian);\n+\t\t\tbreak;\n \t\t}\n #endif\n-\t\terr = read_mem(®s->gpr[op.reg], ea, size, regs);\n+\t\terr = read_mem(®s->gpr[op->reg], ea, size, regs);\n \t\tif (!err) {\n-\t\t\tif (op.type & SIGNEXT)\n-\t\t\t\tdo_signext(®s->gpr[op.reg], size);\n-\t\t\tif ((op.type & BYTEREV) == (cross_endian ? 0 : BYTEREV))\n-\t\t\t\tdo_byterev(®s->gpr[op.reg], size);\n+\t\t\tif (op->type & SIGNEXT)\n+\t\t\t\tdo_signext(®s->gpr[op->reg], size);\n+\t\t\tif ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))\n+\t\t\t\tdo_byterev(®s->gpr[op->reg], size);\n \t\t}\n-\t\tgoto ldst_done;\n+\t\tbreak;\n \n #ifdef CONFIG_PPC_FPU\n \tcase LOAD_FP:\n@@ -2833,15 +2792,15 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t */\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_load(op.reg, ea, size, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_fp_load(op->reg, ea, size, regs, cross_endian);\n+\t\tbreak;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase LOAD_VMX:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_load(op.reg, ea, size, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_vec_load(op->reg, ea, size, regs, cross_endian);\n+\t\tbreak;\n #endif\n #ifdef CONFIG_VSX\n \tcase LOAD_VSX: {\n@@ -2851,18 +2810,18 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX\n \t\t * when the target of the instruction is a vector register.\n \t\t */\n-\t\tif (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))\n+\t\tif (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\terr = do_vsx_load(&op, ea, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_vsx_load(op, ea, regs, cross_endian);\n+\t\tbreak;\n \t}\n #endif\n \tcase LOAD_MULTI:\n \t\tif (!address_ok(regs, ea, size))\n \t\t\treturn -EFAULT;\n-\t\trd = op.reg;\n+\t\trd = op->reg;\n \t\tfor (i = 0; i < size; i += 4) {\n \t\t\tunsigned int v32 = 0;\n \n@@ -2871,47 +2830,47 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\t\tnb = 4;\n \t\t\terr = copy_mem_in((u8 *) &v32, ea, nb, regs);\n \t\t\tif (err)\n-\t\t\t\treturn 0;\n+\t\t\t\tbreak;\n \t\t\tif (unlikely(cross_endian))\n \t\t\t\tv32 = byterev_4(v32);\n \t\t\tregs->gpr[rd] = v32;\n \t\t\tea += 4;\n \t\t\t++rd;\n \t\t}\n-\t\tgoto instr_done;\n+\t\tbreak;\n \n \tcase STORE:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_stq(regs, ea, op.reg, cross_endian);\n-\t\t\tgoto ldst_done;\n+\t\t\terr = emulate_stq(regs, ea, op->reg, cross_endian);\n+\t\t\tbreak;\n \t\t}\n #endif\n-\t\tif ((op.type & UPDATE) && size == sizeof(long) &&\n-\t\t op.reg == 1 && op.update_reg == 1 &&\n+\t\tif ((op->type & UPDATE) && size == sizeof(long) &&\n+\t\t op->reg == 1 && op->update_reg == 1 &&\n \t\t !(regs->msr & MSR_PR) &&\n \t\t ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {\n \t\t\terr = handle_stack_update(ea, regs);\n-\t\t\tgoto ldst_done;\n+\t\t\tbreak;\n \t\t}\n \t\tif (unlikely(cross_endian))\n-\t\t\tdo_byterev(&op.val, size);\n-\t\terr = write_mem(op.val, ea, size, regs);\n-\t\tgoto ldst_done;\n+\t\t\tdo_byterev(&op->val, size);\n+\t\terr = write_mem(op->val, ea, size, regs);\n+\t\tbreak;\n \n #ifdef CONFIG_PPC_FPU\n \tcase STORE_FP:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_store(op.reg, ea, size, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_fp_store(op->reg, ea, size, regs, cross_endian);\n+\t\tbreak;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase STORE_VMX:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_store(op.reg, ea, size, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_vec_store(op->reg, ea, size, regs, cross_endian);\n+\t\tbreak;\n #endif\n #ifdef CONFIG_VSX\n \tcase STORE_VSX: {\n@@ -2921,18 +2880,18 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX\n \t\t * when the target of the instruction is a vector register.\n \t\t */\n-\t\tif (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))\n+\t\tif (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\terr = do_vsx_store(&op, ea, regs, cross_endian);\n-\t\tgoto ldst_done;\n+\t\terr = do_vsx_store(op, ea, regs, cross_endian);\n+\t\tbreak;\n \t}\n #endif\n \tcase STORE_MULTI:\n \t\tif (!address_ok(regs, ea, size))\n \t\t\treturn -EFAULT;\n-\t\trd = op.reg;\n+\t\trd = op->reg;\n \t\tfor (i = 0; i < size; i += 4) {\n \t\t\tunsigned int v32 = regs->gpr[rd];\n \n@@ -2943,10 +2902,89 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\t\tv32 = byterev_4(v32);\n \t\t\terr = copy_mem_out((u8 *) &v32, ea, nb, regs);\n \t\t\tif (err)\n-\t\t\t\treturn 0;\n+\t\t\t\tbreak;\n \t\t\tea += 4;\n \t\t\t++rd;\n \t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (op->type & UPDATE)\n+\t\tregs->gpr[op->update_reg] = op->ea;\n+\n+\treturn 0;\n+}\n+NOKPROBE_SYMBOL(emulate_loadstore);\n+\n+/*\n+ * Emulate instructions that cause a transfer of control,\n+ * loads and stores, and a few other instructions.\n+ * Returns 1 if the step was emulated, 0 if not,\n+ * or -1 if the instruction is one that should not be stepped,\n+ * such as an rfid, or a mtmsrd that would clear MSR_RI.\n+ */\n+int emulate_step(struct pt_regs *regs, unsigned int instr)\n+{\n+\tstruct instruction_op op;\n+\tint r, err, type;\n+\tunsigned long val;\n+\tunsigned long ea;\n+\n+\tr = analyse_instr(&op, regs, instr);\n+\tif (r < 0)\n+\t\treturn r;\n+\tif (r > 0) {\n+\t\temulate_update_regs(regs, &op);\n+\t\treturn 0;\n+\t}\n+\n+\terr = 0;\n+\ttype = op.type & INSTR_TYPE_MASK;\n+\n+\tif (OP_IS_LOAD_STORE(type)) {\n+\t\terr = emulate_loadstore(regs, &op);\n+\t\tif (err)\n+\t\t\treturn 0;\n+\t\tgoto instr_done;\n+\t}\n+\n+\tswitch (type) {\n+\tcase CACHEOP:\n+\t\tea = truncate_if_32bit(regs->msr, op.ea);\n+\t\tif (!address_ok(regs, ea, 8))\n+\t\t\treturn 0;\n+\t\tswitch (op.type & CACHEOP_MASK) {\n+\t\tcase DCBST:\n+\t\t\t__cacheop_user_asmx(ea, err, \"dcbst\");\n+\t\t\tbreak;\n+\t\tcase DCBF:\n+\t\t\t__cacheop_user_asmx(ea, err, \"dcbf\");\n+\t\t\tbreak;\n+\t\tcase DCBTST:\n+\t\t\tif (op.reg == 0)\n+\t\t\t\tprefetchw((void *) ea);\n+\t\t\tbreak;\n+\t\tcase DCBT:\n+\t\t\tif (op.reg == 0)\n+\t\t\t\tprefetch((void *) ea);\n+\t\t\tbreak;\n+\t\tcase ICBI:\n+\t\t\t__cacheop_user_asmx(ea, err, \"icbi\");\n+\t\t\tbreak;\n+\t\tcase DCBZ:\n+\t\t\terr = emulate_dcbz(ea, regs);\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (err) {\n+\t\t\tregs->dar = ea;\n+\t\t\treturn 0;\n+\t\t}\n \t\tgoto instr_done;\n \n \tcase MFMSR:\n@@ -2989,12 +3027,6 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t}\n \treturn 0;\n \n- ldst_done:\n-\tif (err)\n-\t\treturn 0;\n-\tif (op.type & UPDATE)\n-\t\tregs->gpr[op.update_reg] = op.ea;\n-\n instr_done:\n \tregs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);\n \treturn 1;\n", "prefixes": [ "v3", "16/17" ] }