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GET /api/patches/807407/?format=api
{ "id": 807407, "url": "http://patchwork.ozlabs.org/api/patches/807407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-16-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504066360-30128-16-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504066360-30128-16-git-send-email-paulus@ozlabs.org/", "date": "2017-08-30T04:12:38", "name": "[v3,15/17] powerpc: Handle opposite-endian processes in emulation code", "commit_ref": "d955189ae42796621fb439e5e778ccaeebc2a1e7", "pull_url": null, "state": "accepted", "archived": false, "hash": "700754f78df0e55546bff1155012ef7029565c3a", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-16-git-send-email-paulus@ozlabs.org/mbox/", "series": [ { "id": 522, "url": "http://patchwork.ozlabs.org/api/series/522/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=522", "date": "2017-08-30T04:12:25", "name": "powerpc: Do alignment fixups using analyse_instr etc.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/522/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807407/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807407/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhtCq53Wrz9sN7\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:42:47 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhtCq3nsbzDqJ3\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:42:47 +1000 (AEST)", "from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYK5FZwzDqGG\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 14:12:53 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhsYK4NrSz9sPt; Wed, 30 Aug 2017 14:12:53 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xhsYK2dmzz9sP5\n\tfor <linuxppc-dev@ozlabs.org>; Wed, 30 Aug 2017 14:12:53 +1000 (AEST)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"I7ge7qi1\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"I7ge7qi1\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"I7ge7qi1\"; \n\tdkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066373; bh=6PGyFdo1Mik8tQjnBa4Js/FryS2688McZP8We7O1MCM=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=I7ge7qi1i9JKCYNlm+cNA21thrDy2uhMAD7kd3PmqinaCJ2w9k2TCqDWLE+KwJk9t\n\tbiN9G1jMeeV0UcTNWtM2UZdnBFKhAjIAHGwbV+G6jxPkO1+Y1VWZLpN2apYg8dgF1k\n\ty2LkSxVOPC5/lsC5Delf+zmEmVpbkr17fJB/b20QrILGSFriw7/JD9711E+wSGVSB2\n\tVEMSjfUn7YBg8w2O1c/9L6FvFI8HIfEfUgfiPIYfmyDr0dWaBQQW0fODgAdQmssZmq\n\tFuVLknwWoEZr5mtaD4rTlAGrP66iML+OmhajwXFmfK1H9j+zaDAUA0fV1N9peQHuSY\n\tur1yBW7X3M+QQ==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v3 15/17] powerpc: Handle opposite-endian processes in\n\temulation code", "Date": "Wed, 30 Aug 2017 14:12:38 +1000", "Message-Id": "<1504066360-30128-16-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "References": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This adds code to the load and store emulation code to byte-swap\nthe data appropriately when the process being emulated is set to\nthe opposite endianness to that of the kernel.\n\nThis also enables the emulation for the multiple-register loads\nand stores (lmw, stmw, lswi, stswi, lswx, stswx) to work for\nlittle-endian. In little-endian mode, the partial word at the\nend of a transfer for lsw*/stsw* (when the byte count is not a\nmultiple of 4) is loaded/stored at the least-significant end of\nthe register. Additionally, this fixes a bug in the previous\ncode in that it could call read_mem/write_mem with a byte count\nthat was not 1, 2, 4 or 8.\n\nNote that this only works correctly on processors with \"true\"\nlittle-endian mode, such as IBM POWER processors from POWER6 on, not\nthe so-called \"PowerPC\" little-endian mode that uses address swizzling\nas implemented on the old 32-bit 603, 604, 740/750, 74xx CPUs.\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/include/asm/sstep.h | 7 +-\n arch/powerpc/lib/sstep.c | 184 +++++++++++++++++++++++++++------------\n 2 files changed, 131 insertions(+), 60 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h\nindex 793639a..958c2c5 100644\n--- a/arch/powerpc/include/asm/sstep.h\n+++ b/arch/powerpc/include/asm/sstep.h\n@@ -153,7 +153,8 @@ void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);\n extern int emulate_step(struct pt_regs *regs, unsigned int instr);\n \n extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n-\t\t\t const void *mem);\n-extern void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,\n-\t\t\t void *mem);\n+\t\t\t const void *mem, bool cross_endian);\n+extern void emulate_vsx_store(struct instruction_op *op,\n+\t\t\t const union vsx_reg *reg, void *mem,\n+\t\t\t bool cross_endian);\n extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);\ndiff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 5c0f50b..810b5f2 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -217,6 +217,33 @@ static nokprobe_inline unsigned long byterev_8(unsigned long x)\n }\n #endif\n \n+static nokprobe_inline void do_byte_reverse(void *ptr, int nb)\n+{\n+\tswitch (nb) {\n+\tcase 2:\n+\t\t*(u16 *)ptr = byterev_2(*(u16 *)ptr);\n+\t\tbreak;\n+\tcase 4:\n+\t\t*(u32 *)ptr = byterev_4(*(u32 *)ptr);\n+\t\tbreak;\n+#ifdef __powerpc64__\n+\tcase 8:\n+\t\t*(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);\n+\t\tbreak;\n+\tcase 16: {\n+\t\tunsigned long *up = (unsigned long *)ptr;\n+\t\tunsigned long tmp;\n+\t\ttmp = byterev_8(up[0]);\n+\t\tup[0] = byterev_8(up[1]);\n+\t\tup[1] = tmp;\n+\t\tbreak;\n+\t}\n+#endif\n+\tdefault:\n+\t\tWARN_ON_ONCE(1);\n+\t}\n+}\n+\n static nokprobe_inline int read_mem_aligned(unsigned long *dest,\n \t\t\t\t\t unsigned long ea, int nb,\n \t\t\t\t\t struct pt_regs *regs)\n@@ -430,7 +457,8 @@ NOKPROBE_SYMBOL(write_mem);\n * These access either the real FP register or the image in the\n * thread_struct, depending on regs->msr & MSR_FP.\n */\n-static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n+static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n+\t\t bool cross_endian)\n {\n \tint err;\n \tunion {\n@@ -445,6 +473,11 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \terr = copy_mem_in(u.b, ea, nb, regs);\n \tif (err)\n \t\treturn err;\n+\tif (unlikely(cross_endian)) {\n+\t\tdo_byte_reverse(u.b, min(nb, 8));\n+\t\tif (nb == 16)\n+\t\t\tdo_byte_reverse(&u.b[8], 8);\n+\t}\n \tpreempt_disable();\n \tif (nb == 4)\n \t\tconv_sp_to_dp(&u.f, &u.d[0]);\n@@ -465,7 +498,8 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n }\n NOKPROBE_SYMBOL(do_fp_load);\n \n-static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n+static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n+\t\t bool cross_endian)\n {\n \tunion {\n \t\tfloat f;\n@@ -491,6 +525,11 @@ static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \t\t\tu.l[1] = current->thread.TS_FPR(rn);\n \t}\n \tpreempt_enable();\n+\tif (unlikely(cross_endian)) {\n+\t\tdo_byte_reverse(u.b, min(nb, 8));\n+\t\tif (nb == 16)\n+\t\t\tdo_byte_reverse(&u.b[8], 8);\n+\t}\n \treturn copy_mem_out(u.b, ea, nb, regs);\n }\n NOKPROBE_SYMBOL(do_fp_store);\n@@ -499,7 +538,8 @@ NOKPROBE_SYMBOL(do_fp_store);\n #ifdef CONFIG_ALTIVEC\n /* For Altivec/VMX, no need to worry about alignment */\n static nokprobe_inline int do_vec_load(int rn, unsigned long ea,\n-\t\t\t\t int size, struct pt_regs *regs)\n+\t\t\t\t int size, struct pt_regs *regs,\n+\t\t\t\t bool cross_endian)\n {\n \tint err;\n \tunion {\n@@ -514,7 +554,8 @@ static nokprobe_inline int do_vec_load(int rn, unsigned long ea,\n \terr = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);\n \tif (err)\n \t\treturn err;\n-\n+\tif (unlikely(cross_endian))\n+\t\tdo_byte_reverse(&u.b[ea & 0xf], size);\n \tpreempt_disable();\n \tif (regs->msr & MSR_VEC)\n \t\tput_vr(rn, &u.v);\n@@ -525,7 +566,8 @@ static nokprobe_inline int do_vec_load(int rn, unsigned long ea,\n }\n \n static nokprobe_inline int do_vec_store(int rn, unsigned long ea,\n-\t\t\t\t\tint size, struct pt_regs *regs)\n+\t\t\t\t\tint size, struct pt_regs *regs,\n+\t\t\t\t\tbool cross_endian)\n {\n \tunion {\n \t\t__vector128 v;\n@@ -543,49 +585,60 @@ static nokprobe_inline int do_vec_store(int rn, unsigned long ea,\n \telse\n \t\tu.v = current->thread.vr_state.vr[rn];\n \tpreempt_enable();\n+\tif (unlikely(cross_endian))\n+\t\tdo_byte_reverse(&u.b[ea & 0xf], size);\n \treturn copy_mem_out(&u.b[ea & 0xf], ea, size, regs);\n }\n #endif /* CONFIG_ALTIVEC */\n \n #ifdef __powerpc64__\n static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,\n-\t\t\t\t int reg)\n+\t\t\t\t int reg, bool cross_endian)\n {\n \tint err;\n \n \tif (!address_ok(regs, ea, 16))\n \t\treturn -EFAULT;\n \t/* if aligned, should be atomic */\n-\tif ((ea & 0xf) == 0)\n-\t\treturn do_lq(ea, ®s->gpr[reg]);\n-\n-\terr = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);\n-\tif (!err)\n-\t\terr = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);\n+\tif ((ea & 0xf) == 0) {\n+\t\terr = do_lq(ea, ®s->gpr[reg]);\n+\t} else {\n+\t\terr = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);\n+\t\tif (!err)\n+\t\t\terr = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);\n+\t}\n+\tif (!err && unlikely(cross_endian))\n+\t\tdo_byte_reverse(®s->gpr[reg], 16);\n \treturn err;\n }\n \n static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,\n-\t\t\t\t int reg)\n+\t\t\t\t int reg, bool cross_endian)\n {\n \tint err;\n+\tunsigned long vals[2];\n \n \tif (!address_ok(regs, ea, 16))\n \t\treturn -EFAULT;\n+\tvals[0] = regs->gpr[reg];\n+\tvals[1] = regs->gpr[reg + 1];\n+\tif (unlikely(cross_endian))\n+\t\tdo_byte_reverse(vals, 16);\n+\n \t/* if aligned, should be atomic */\n \tif ((ea & 0xf) == 0)\n-\t\treturn do_stq(ea, regs->gpr[reg], regs->gpr[reg + 1]);\n+\t\treturn do_stq(ea, vals[0], vals[1]);\n \n-\terr = write_mem(regs->gpr[reg + IS_LE], ea, 8, regs);\n+\terr = write_mem(vals[IS_LE], ea, 8, regs);\n \tif (!err)\n-\t\terr = write_mem(regs->gpr[reg + IS_BE], ea + 8, 8, regs);\n+\t\terr = write_mem(vals[IS_BE], ea + 8, 8, regs);\n \treturn err;\n }\n #endif /* __powerpc64 */\n \n #ifdef CONFIG_VSX\n void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n-\t\t const void *mem)\n+\t\t const void *mem, bool rev)\n {\n \tint size, read_size;\n \tint i, j;\n@@ -602,19 +655,18 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n \t\tif (size == 0)\n \t\t\tbreak;\n \t\tmemcpy(reg, mem, size);\n-\t\tif (IS_LE && (op->vsx_flags & VSX_LDLEFT)) {\n-\t\t\t/* reverse 16 bytes */\n-\t\t\tunsigned long tmp;\n-\t\t\ttmp = byterev_8(reg->d[0]);\n-\t\t\treg->d[0] = byterev_8(reg->d[1]);\n-\t\t\treg->d[1] = tmp;\n-\t\t}\n+\t\tif (IS_LE && (op->vsx_flags & VSX_LDLEFT))\n+\t\t\trev = !rev;\n+\t\tif (rev)\n+\t\t\tdo_byte_reverse(reg, 16);\n \t\tbreak;\n \tcase 8:\n \t\t/* scalar loads, lxvd2x, lxvdsx */\n \t\tread_size = (size >= 8) ? 8 : size;\n \t\ti = IS_LE ? 8 : 8 - read_size;\n \t\tmemcpy(®->b[i], mem, read_size);\n+\t\tif (rev)\n+\t\t\tdo_byte_reverse(®->b[i], 8);\n \t\tif (size < 8) {\n \t\t\tif (op->type & SIGNEXT) {\n \t\t\t\t/* size == 4 is the only case here */\n@@ -626,9 +678,10 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n \t\t\t\tpreempt_enable();\n \t\t\t}\n \t\t} else {\n-\t\t\tif (size == 16)\n-\t\t\t\treg->d[IS_BE] = *(unsigned long *)(mem + 8);\n-\t\t\telse if (op->vsx_flags & VSX_SPLAT)\n+\t\t\tif (size == 16) {\n+\t\t\t\tunsigned long v = *(unsigned long *)(mem + 8);\n+\t\t\t\treg->d[IS_BE] = !rev ? v : byterev_8(v);\n+\t\t\t} else if (op->vsx_flags & VSX_SPLAT)\n \t\t\t\treg->d[IS_BE] = reg->d[IS_LE];\n \t\t}\n \t\tbreak;\n@@ -637,7 +690,7 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n \t\twp = mem;\n \t\tfor (j = 0; j < size / 4; ++j) {\n \t\t\ti = IS_LE ? 3 - j : j;\n-\t\t\treg->w[i] = *wp++;\n+\t\t\treg->w[i] = !rev ? *wp++ : byterev_4(*wp++);\n \t\t}\n \t\tif (op->vsx_flags & VSX_SPLAT) {\n \t\t\tu32 val = reg->w[IS_LE ? 3 : 0];\n@@ -652,7 +705,7 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,\n \t\thp = mem;\n \t\tfor (j = 0; j < size / 2; ++j) {\n \t\t\ti = IS_LE ? 7 - j : j;\n-\t\t\treg->h[i] = *hp++;\n+\t\t\treg->h[i] = !rev ? *hp++ : byterev_2(*hp++);\n \t\t}\n \t\tbreak;\n \tcase 1:\n@@ -669,7 +722,7 @@ EXPORT_SYMBOL_GPL(emulate_vsx_load);\n NOKPROBE_SYMBOL(emulate_vsx_load);\n \n void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,\n-\t\t void *mem)\n+\t\t void *mem, bool rev)\n {\n \tint size, write_size;\n \tint i, j;\n@@ -685,7 +738,9 @@ void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,\n \t\t/* stxv, stxvx, stxvl, stxvll */\n \t\tif (size == 0)\n \t\t\tbreak;\n-\t\tif (IS_LE && (op->vsx_flags & VSX_LDLEFT)) {\n+\t\tif (IS_LE && (op->vsx_flags & VSX_LDLEFT))\n+\t\t\trev = !rev;\n+\t\tif (rev) {\n \t\t\t/* reverse 16 bytes */\n \t\t\tbuf.d[0] = byterev_8(reg->d[1]);\n \t\t\tbuf.d[1] = byterev_8(reg->d[0]);\n@@ -707,13 +762,18 @@ void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,\n \t\tmemcpy(mem, ®->b[i], write_size);\n \t\tif (size == 16)\n \t\t\tmemcpy(mem + 8, ®->d[IS_BE], 8);\n+\t\tif (unlikely(rev)) {\n+\t\t\tdo_byte_reverse(mem, write_size);\n+\t\t\tif (size == 16)\n+\t\t\t\tdo_byte_reverse(mem + 8, 8);\n+\t\t}\n \t\tbreak;\n \tcase 4:\n \t\t/* stxvw4x */\n \t\twp = mem;\n \t\tfor (j = 0; j < size / 4; ++j) {\n \t\t\ti = IS_LE ? 3 - j : j;\n-\t\t\t*wp++ = reg->w[i];\n+\t\t\t*wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);\n \t\t}\n \t\tbreak;\n \tcase 2:\n@@ -721,7 +781,7 @@ void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,\n \t\thp = mem;\n \t\tfor (j = 0; j < size / 2; ++j) {\n \t\t\ti = IS_LE ? 7 - j : j;\n-\t\t\t*hp++ = reg->h[i];\n+\t\t\t*hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);\n \t\t}\n \t\tbreak;\n \tcase 1:\n@@ -738,7 +798,8 @@ EXPORT_SYMBOL_GPL(emulate_vsx_store);\n NOKPROBE_SYMBOL(emulate_vsx_store);\n \n static nokprobe_inline int do_vsx_load(struct instruction_op *op,\n-\t\t\t\t unsigned long ea, struct pt_regs *regs)\n+\t\t\t\t unsigned long ea, struct pt_regs *regs,\n+\t\t\t\t bool cross_endian)\n {\n \tint reg = op->reg;\n \tu8 mem[16];\n@@ -748,7 +809,7 @@ static nokprobe_inline int do_vsx_load(struct instruction_op *op,\n \tif (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))\n \t\treturn -EFAULT;\n \n-\temulate_vsx_load(op, &buf, mem);\n+\temulate_vsx_load(op, &buf, mem, cross_endian);\n \tpreempt_disable();\n \tif (reg < 32) {\n \t\t/* FP regs + extensions */\n@@ -769,7 +830,8 @@ static nokprobe_inline int do_vsx_load(struct instruction_op *op,\n }\n \n static nokprobe_inline int do_vsx_store(struct instruction_op *op,\n-\t\t\t\t\tunsigned long ea, struct pt_regs *regs)\n+\t\t\t\t\tunsigned long ea, struct pt_regs *regs,\n+\t\t\t\t\tbool cross_endian)\n {\n \tint reg = op->reg;\n \tu8 mem[16];\n@@ -795,7 +857,7 @@ static nokprobe_inline int do_vsx_store(struct instruction_op *op,\n \t\t\tbuf.v = current->thread.vr_state.vr[reg - 32];\n \t}\n \tpreempt_enable();\n-\temulate_vsx_store(op, &buf, mem);\n+\temulate_vsx_store(op, &buf, mem, cross_endian);\n \treturn copy_mem_out(mem, ea, size, regs);\n }\n #endif /* CONFIG_VSX */\n@@ -2619,6 +2681,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tunsigned int cr;\n \tint i, rd, nb;\n \tunsigned long ea;\n+\tbool cross_endian;\n \n \tr = analyse_instr(&op, regs, instr);\n \tif (r < 0)\n@@ -2631,6 +2694,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \terr = 0;\n \tsize = GETSIZE(op.type);\n \ttype = op.type & INSTR_TYPE_MASK;\n+\tcross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);\n \n \tea = op.ea;\n \tif (OP_IS_LOAD_STORE(type) || type == CACHEOP)\n@@ -2746,7 +2810,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tcase LOAD:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_lq(regs, ea, op.reg);\n+\t\t\terr = emulate_lq(regs, ea, op.reg, cross_endian);\n \t\t\tgoto ldst_done;\n \t\t}\n #endif\n@@ -2754,7 +2818,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\tif (!err) {\n \t\t\tif (op.type & SIGNEXT)\n \t\t\t\tdo_signext(®s->gpr[op.reg], size);\n-\t\t\tif (op.type & BYTEREV)\n+\t\t\tif ((op.type & BYTEREV) == (cross_endian ? 0 : BYTEREV))\n \t\t\t\tdo_byterev(®s->gpr[op.reg], size);\n \t\t}\n \t\tgoto ldst_done;\n@@ -2769,14 +2833,14 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t */\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_load(op.reg, ea, size, regs);\n+\t\terr = do_fp_load(op.reg, ea, size, regs, cross_endian);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase LOAD_VMX:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_load(op.reg, ea, size, regs);\n+\t\terr = do_vec_load(op.reg, ea, size, regs, cross_endian);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n@@ -2791,23 +2855,26 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\terr = do_vsx_load(&op, ea, regs);\n+\t\terr = do_vsx_load(&op, ea, regs, cross_endian);\n \t\tgoto ldst_done;\n \t}\n #endif\n \tcase LOAD_MULTI:\n-\t\tif (regs->msr & MSR_LE)\n-\t\t\treturn 0;\n+\t\tif (!address_ok(regs, ea, size))\n+\t\t\treturn -EFAULT;\n \t\trd = op.reg;\n \t\tfor (i = 0; i < size; i += 4) {\n+\t\t\tunsigned int v32 = 0;\n+\n \t\t\tnb = size - i;\n \t\t\tif (nb > 4)\n \t\t\t\tnb = 4;\n-\t\t\terr = read_mem(®s->gpr[rd], ea, nb, regs);\n+\t\t\terr = copy_mem_in((u8 *) &v32, ea, nb, regs);\n \t\t\tif (err)\n \t\t\t\treturn 0;\n-\t\t\tif (nb < 4)\t/* left-justify last bytes */\n-\t\t\t\tregs->gpr[rd] <<= 32 - 8 * nb;\n+\t\t\tif (unlikely(cross_endian))\n+\t\t\t\tv32 = byterev_4(v32);\n+\t\t\tregs->gpr[rd] = v32;\n \t\t\tea += 4;\n \t\t\t++rd;\n \t\t}\n@@ -2816,7 +2883,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tcase STORE:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_stq(regs, ea, op.reg);\n+\t\t\terr = emulate_stq(regs, ea, op.reg, cross_endian);\n \t\t\tgoto ldst_done;\n \t\t}\n #endif\n@@ -2827,6 +2894,8 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\terr = handle_stack_update(ea, regs);\n \t\t\tgoto ldst_done;\n \t\t}\n+\t\tif (unlikely(cross_endian))\n+\t\t\tdo_byterev(&op.val, size);\n \t\terr = write_mem(op.val, ea, size, regs);\n \t\tgoto ldst_done;\n \n@@ -2834,14 +2903,14 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tcase STORE_FP:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_store(op.reg, ea, size, regs);\n+\t\terr = do_fp_store(op.reg, ea, size, regs, cross_endian);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase STORE_VMX:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_store(op.reg, ea, size, regs);\n+\t\terr = do_vec_store(op.reg, ea, size, regs, cross_endian);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n@@ -2856,22 +2925,23 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\terr = do_vsx_store(&op, ea, regs);\n+\t\terr = do_vsx_store(&op, ea, regs, cross_endian);\n \t\tgoto ldst_done;\n \t}\n #endif\n \tcase STORE_MULTI:\n-\t\tif (regs->msr & MSR_LE)\n-\t\t\treturn 0;\n+\t\tif (!address_ok(regs, ea, size))\n+\t\t\treturn -EFAULT;\n \t\trd = op.reg;\n \t\tfor (i = 0; i < size; i += 4) {\n-\t\t\tval = regs->gpr[rd];\n+\t\t\tunsigned int v32 = regs->gpr[rd];\n+\n \t\t\tnb = size - i;\n \t\t\tif (nb > 4)\n \t\t\t\tnb = 4;\n-\t\t\telse\n-\t\t\t\tval >>= 32 - 8 * nb;\n-\t\t\terr = write_mem(val, ea, nb, regs);\n+\t\t\tif (unlikely(cross_endian))\n+\t\t\t\tv32 = byterev_4(v32);\n+\t\t\terr = copy_mem_out((u8 *) &v32, ea, nb, regs);\n \t\t\tif (err)\n \t\t\t\treturn 0;\n \t\t\tea += 4;\n", "prefixes": [ "v3", "15/17" ] }