Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/807395/?format=api
{ "id": 807395, "url": "http://patchwork.ozlabs.org/api/patches/807395/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-6-git-send-email-paulus@ozlabs.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504066360-30128-6-git-send-email-paulus@ozlabs.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504066360-30128-6-git-send-email-paulus@ozlabs.org/", "date": "2017-08-30T04:12:28", "name": "[v3,05/17] powerpc/64: Fix update forms of loads and stores to write 64-bit EA", "commit_ref": "d120cdbce68c3739f94f733bec376460fb9cbc14", "pull_url": null, "state": "accepted", "archived": false, "hash": "50c9a9a50c545d4dbb9fdf008e9c3f895c54be05", "submitter": { "id": 67079, "url": "http://patchwork.ozlabs.org/api/people/67079/?format=api", "name": "Paul Mackerras", "email": "paulus@ozlabs.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-6-git-send-email-paulus@ozlabs.org/mbox/", "series": [ { "id": 522, "url": "http://patchwork.ozlabs.org/api/series/522/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=522", "date": "2017-08-30T04:12:25", "name": "powerpc: Do alignment fixups using analyse_instr etc.", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/522/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807395/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807395/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhsnW2CQvz9s9Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:23:27 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhsnW13VjzDqHx\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 14:23:27 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYG5t8FzDqGG\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 14:12:50 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhsYG4zk9z9sNc; Wed, 30 Aug 2017 14:12:50 +1000 (AEST)", "from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xhsYG3D0Nz9sPt\n\tfor <linuxppc-dev@ozlabs.org>; Wed, 30 Aug 2017 14:12:50 +1000 (AEST)" ], "Authentication-Results": [ "ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"CoSm5JnE\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"CoSm5JnE\";\n\tdkim-atps=neutral", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"CoSm5JnE\"; \n\tdkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066370; bh=FyOZPCAs4Ly4WMStZB0LDXhl2ewZED1qmVi5G46d9Ew=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=CoSm5JnEZeV89P3AuRT1t0Qyztr2wyc4csgMpp0GSvEsosxba3dtYbiXrJPcxgVmN\n\tifahU/lVfqsciatZlQ4wl+HpTe7gcSXRMocHt4qnJTVYIfkg1QjK9EQVOzbUzY1pSc\n\taa3vZvQTQMvHZqJ44sbAKhz2VCCYPd78MjGglpFSMkBYBD9UY9gUb78n3K8do5CXJz\n\tD9pordY6f5/Wq1Lelf6gEtlz5qlnlDWX5BYZi8vBV/7RiZ+doyONT4zIkjitB24lTx\n\tu5GCSbVwbLknCViWmrc0yTEUoZZWraQLmg3OswF33KgQxFvRNhlxD8wMdZAb2cGr38\n\ti/WHKwh9WSZww==", "From": "Paul Mackerras <paulus@ozlabs.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v3 05/17] powerpc/64: Fix update forms of loads and stores to\n\twrite 64-bit EA", "Date": "Wed, 30 Aug 2017 14:12:28 +1000", "Message-Id": "<1504066360-30128-6-git-send-email-paulus@ozlabs.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "References": "<1504066360-30128-1-git-send-email-paulus@ozlabs.org>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "When a 64-bit processor is executing in 32-bit mode, the update forms\nof load and store instructions are required by the architecture to\nwrite the full 64-bit effective address into the RA register, though\nonly the bottom 32 bits are used to address memory. Currently,\nthe instruction emulation code writes the truncated address to the\nRA register. This fixes it by keeping the full 64-bit EA in the\ninstruction_op structure, truncating the address in emulate_step()\nwhere it is used to address memory, rather than in the address\ncomputations in analyse_instr().\n\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/include/asm/sstep.h | 4 +-\n arch/powerpc/lib/sstep.c | 109 ++++++++++++++++++++-------------------\n 2 files changed, 58 insertions(+), 55 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h\nindex 9801970..4fcc2c9 100644\n--- a/arch/powerpc/include/asm/sstep.h\n+++ b/arch/powerpc/include/asm/sstep.h\n@@ -25,7 +25,7 @@ struct pt_regs;\n \n enum instruction_type {\n \tCOMPUTE,\t\t/* arith/logical/CR op, etc. */\n-\tLOAD,\n+\tLOAD,\t\t\t/* load and store types need to be contiguous */\n \tLOAD_MULTI,\n \tLOAD_FP,\n \tLOAD_VMX,\n@@ -52,6 +52,8 @@ enum instruction_type {\n \n #define INSTR_TYPE_MASK\t0x1f\n \n+#define OP_IS_LOAD_STORE(type)\t(LOAD <= (type) && (type) <= STCX)\n+\n /* Compute flags, ORed in with type */\n #define SETREG\t\t0x20\n #define SETCC\t\t0x40\ndiff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 88c7487..e20f2b4 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -126,7 +126,7 @@ static nokprobe_inline unsigned long dform_ea(unsigned int instr,\n \tif (ra)\n \t\tea += regs->gpr[ra];\n \n-\treturn truncate_if_32bit(regs->msr, ea);\n+\treturn ea;\n }\n \n #ifdef __powerpc64__\n@@ -144,7 +144,7 @@ static nokprobe_inline unsigned long dsform_ea(unsigned int instr,\n \tif (ra)\n \t\tea += regs->gpr[ra];\n \n-\treturn truncate_if_32bit(regs->msr, ea);\n+\treturn ea;\n }\n \n /*\n@@ -161,7 +161,7 @@ static nokprobe_inline unsigned long dqform_ea(unsigned int instr,\n \tif (ra)\n \t\tea += regs->gpr[ra];\n \n-\treturn truncate_if_32bit(regs->msr, ea);\n+\treturn ea;\n }\n #endif /* __powerpc64 */\n \n@@ -180,7 +180,7 @@ static nokprobe_inline unsigned long xform_ea(unsigned int instr,\n \tif (ra)\n \t\tea += regs->gpr[ra];\n \n-\treturn truncate_if_32bit(regs->msr, ea);\n+\treturn ea;\n }\n \n /*\n@@ -1789,10 +1789,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\tif (rb == 0)\n \t\t\t\trb = 32;\t/* # bytes to load */\n \t\t\top->type = MKOP(LOAD_MULTI, 0, rb);\n-\t\t\top->ea = 0;\n-\t\t\tif (ra)\n-\t\t\t\top->ea = truncate_if_32bit(regs->msr,\n-\t\t\t\t\t\t\t regs->gpr[ra]);\n+\t\t\top->ea = ra ? regs->gpr[ra] : 0;\n \t\t\tbreak;\n \n #ifdef CONFIG_PPC_FPU\n@@ -1837,10 +1834,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\tif (rb == 0)\n \t\t\t\trb = 32;\t/* # bytes to store */\n \t\t\top->type = MKOP(STORE_MULTI, 0, rb);\n-\t\t\top->ea = 0;\n-\t\t\tif (ra)\n-\t\t\t\top->ea = truncate_if_32bit(regs->msr,\n-\t\t\t\t\t\t\t regs->gpr[ra]);\n+\t\t\top->ea = ra ? regs->gpr[ra] : 0;\n \t\t\tbreak;\n \n \t\tcase 790:\t/* lhbrx */\n@@ -2407,10 +2401,11 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)\n int emulate_step(struct pt_regs *regs, unsigned int instr)\n {\n \tstruct instruction_op op;\n-\tint r, err, size;\n+\tint r, err, size, type;\n \tunsigned long val;\n \tunsigned int cr;\n \tint i, rd, nb;\n+\tunsigned long ea;\n \n \tr = analyse_instr(&op, regs, instr);\n \tif (r < 0)\n@@ -2422,27 +2417,33 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \n \terr = 0;\n \tsize = GETSIZE(op.type);\n-\tswitch (op.type & INSTR_TYPE_MASK) {\n+\ttype = op.type & INSTR_TYPE_MASK;\n+\n+\tea = op.ea;\n+\tif (OP_IS_LOAD_STORE(type) || type == CACHEOP)\n+\t\tea = truncate_if_32bit(regs->msr, op.ea);\n+\n+\tswitch (type) {\n \tcase CACHEOP:\n-\t\tif (!address_ok(regs, op.ea, 8))\n+\t\tif (!address_ok(regs, ea, 8))\n \t\t\treturn 0;\n \t\tswitch (op.type & CACHEOP_MASK) {\n \t\tcase DCBST:\n-\t\t\t__cacheop_user_asmx(op.ea, err, \"dcbst\");\n+\t\t\t__cacheop_user_asmx(ea, err, \"dcbst\");\n \t\t\tbreak;\n \t\tcase DCBF:\n-\t\t\t__cacheop_user_asmx(op.ea, err, \"dcbf\");\n+\t\t\t__cacheop_user_asmx(ea, err, \"dcbf\");\n \t\t\tbreak;\n \t\tcase DCBTST:\n \t\t\tif (op.reg == 0)\n-\t\t\t\tprefetchw((void *) op.ea);\n+\t\t\t\tprefetchw((void *) ea);\n \t\t\tbreak;\n \t\tcase DCBT:\n \t\t\tif (op.reg == 0)\n-\t\t\t\tprefetch((void *) op.ea);\n+\t\t\t\tprefetch((void *) ea);\n \t\t\tbreak;\n \t\tcase ICBI:\n-\t\t\t__cacheop_user_asmx(op.ea, err, \"icbi\");\n+\t\t\t__cacheop_user_asmx(ea, err, \"icbi\");\n \t\t\tbreak;\n \t\t}\n \t\tif (err)\n@@ -2450,29 +2451,29 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\tgoto instr_done;\n \n \tcase LARX:\n-\t\tif (op.ea & (size - 1))\n+\t\tif (ea & (size - 1))\n \t\t\tbreak;\t\t/* can't handle misaligned */\n-\t\tif (!address_ok(regs, op.ea, size))\n+\t\tif (!address_ok(regs, ea, size))\n \t\t\treturn 0;\n \t\terr = 0;\n \t\tswitch (size) {\n #ifdef __powerpc64__\n \t\tcase 1:\n-\t\t\t__get_user_asmx(val, op.ea, err, \"lbarx\");\n+\t\t\t__get_user_asmx(val, ea, err, \"lbarx\");\n \t\t\tbreak;\n \t\tcase 2:\n-\t\t\t__get_user_asmx(val, op.ea, err, \"lharx\");\n+\t\t\t__get_user_asmx(val, ea, err, \"lharx\");\n \t\t\tbreak;\n #endif\n \t\tcase 4:\n-\t\t\t__get_user_asmx(val, op.ea, err, \"lwarx\");\n+\t\t\t__get_user_asmx(val, ea, err, \"lwarx\");\n \t\t\tbreak;\n #ifdef __powerpc64__\n \t\tcase 8:\n-\t\t\t__get_user_asmx(val, op.ea, err, \"ldarx\");\n+\t\t\t__get_user_asmx(val, ea, err, \"ldarx\");\n \t\t\tbreak;\n \t\tcase 16:\n-\t\t\terr = do_lqarx(op.ea, ®s->gpr[op.reg]);\n+\t\t\terr = do_lqarx(ea, ®s->gpr[op.reg]);\n \t\t\tgoto ldst_done;\n #endif\n \t\tdefault:\n@@ -2483,29 +2484,29 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\tgoto ldst_done;\n \n \tcase STCX:\n-\t\tif (op.ea & (size - 1))\n+\t\tif (ea & (size - 1))\n \t\t\tbreak;\t\t/* can't handle misaligned */\n-\t\tif (!address_ok(regs, op.ea, size))\n+\t\tif (!address_ok(regs, ea, size))\n \t\t\treturn 0;\n \t\terr = 0;\n \t\tswitch (size) {\n #ifdef __powerpc64__\n \t\tcase 1:\n-\t\t\t__put_user_asmx(op.val, op.ea, err, \"stbcx.\", cr);\n+\t\t\t__put_user_asmx(op.val, ea, err, \"stbcx.\", cr);\n \t\t\tbreak;\n \t\tcase 2:\n-\t\t\t__put_user_asmx(op.val, op.ea, err, \"stbcx.\", cr);\n+\t\t\t__put_user_asmx(op.val, ea, err, \"stbcx.\", cr);\n \t\t\tbreak;\n #endif\n \t\tcase 4:\n-\t\t\t__put_user_asmx(op.val, op.ea, err, \"stwcx.\", cr);\n+\t\t\t__put_user_asmx(op.val, ea, err, \"stwcx.\", cr);\n \t\t\tbreak;\n #ifdef __powerpc64__\n \t\tcase 8:\n-\t\t\t__put_user_asmx(op.val, op.ea, err, \"stdcx.\", cr);\n+\t\t\t__put_user_asmx(op.val, ea, err, \"stdcx.\", cr);\n \t\t\tbreak;\n \t\tcase 16:\n-\t\t\terr = do_stqcx(op.ea, regs->gpr[op.reg],\n+\t\t\terr = do_stqcx(ea, regs->gpr[op.reg],\n \t\t\t\t regs->gpr[op.reg + 1], &cr);\n \t\t\tbreak;\n #endif\n@@ -2521,11 +2522,11 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tcase LOAD:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_lq(regs, op.ea, op.reg);\n+\t\t\terr = emulate_lq(regs, ea, op.reg);\n \t\t\tgoto ldst_done;\n \t\t}\n #endif\n-\t\terr = read_mem(®s->gpr[op.reg], op.ea, size, regs);\n+\t\terr = read_mem(®s->gpr[op.reg], ea, size, regs);\n \t\tif (!err) {\n \t\t\tif (op.type & SIGNEXT)\n \t\t\t\tdo_signext(®s->gpr[op.reg], size);\n@@ -2539,16 +2540,16 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\tif (!(regs->msr & MSR_FP))\n \t\t\treturn 0;\n \t\tif (size == 4)\n-\t\t\terr = do_fp_load(op.reg, do_lfs, op.ea, size, regs);\n+\t\t\terr = do_fp_load(op.reg, do_lfs, ea, size, regs);\n \t\telse\n-\t\t\terr = do_fp_load(op.reg, do_lfd, op.ea, size, regs);\n+\t\t\terr = do_fp_load(op.reg, do_lfd, ea, size, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase LOAD_VMX:\n \t\tif (!(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_load(op.reg, do_lvx, op.ea, regs);\n+\t\terr = do_vec_load(op.reg, do_lvx, ea, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n@@ -2565,8 +2566,8 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\tif (!address_ok(regs, op.ea, size) ||\n-\t\t __copy_from_user(mem, (void __user *)op.ea, size))\n+\t\tif (!address_ok(regs, ea, size) ||\n+\t\t __copy_from_user(mem, (void __user *)ea, size))\n \t\t\treturn 0;\n \n \t\temulate_vsx_load(&op, &buf, mem);\n@@ -2582,12 +2583,12 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\tnb = size - i;\n \t\t\tif (nb > 4)\n \t\t\t\tnb = 4;\n-\t\t\terr = read_mem(®s->gpr[rd], op.ea, nb, regs);\n+\t\t\terr = read_mem(®s->gpr[rd], ea, nb, regs);\n \t\t\tif (err)\n \t\t\t\treturn 0;\n \t\t\tif (nb < 4)\t/* left-justify last bytes */\n \t\t\t\tregs->gpr[rd] <<= 32 - 8 * nb;\n-\t\t\top.ea += 4;\n+\t\t\tea += 4;\n \t\t\t++rd;\n \t\t}\n \t\tgoto instr_done;\n@@ -2595,18 +2596,18 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \tcase STORE:\n #ifdef __powerpc64__\n \t\tif (size == 16) {\n-\t\t\terr = emulate_stq(regs, op.ea, op.reg);\n+\t\t\terr = emulate_stq(regs, ea, op.reg);\n \t\t\tgoto ldst_done;\n \t\t}\n #endif\n \t\tif ((op.type & UPDATE) && size == sizeof(long) &&\n \t\t op.reg == 1 && op.update_reg == 1 &&\n \t\t !(regs->msr & MSR_PR) &&\n-\t\t op.ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {\n-\t\t\terr = handle_stack_update(op.ea, regs);\n+\t\t ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {\n+\t\t\terr = handle_stack_update(ea, regs);\n \t\t\tgoto ldst_done;\n \t\t}\n-\t\terr = write_mem(op.val, op.ea, size, regs);\n+\t\terr = write_mem(op.val, ea, size, regs);\n \t\tgoto ldst_done;\n \n #ifdef CONFIG_PPC_FPU\n@@ -2614,16 +2615,16 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\tif (!(regs->msr & MSR_FP))\n \t\t\treturn 0;\n \t\tif (size == 4)\n-\t\t\terr = do_fp_store(op.reg, do_stfs, op.ea, size, regs);\n+\t\t\terr = do_fp_store(op.reg, do_stfs, ea, size, regs);\n \t\telse\n-\t\t\terr = do_fp_store(op.reg, do_stfd, op.ea, size, regs);\n+\t\t\terr = do_fp_store(op.reg, do_stfd, ea, size, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase STORE_VMX:\n \t\tif (!(regs->msr & MSR_VEC))\n \t\t\treturn 0;\n-\t\terr = do_vec_store(op.reg, do_stvx, op.ea, regs);\n+\t\terr = do_vec_store(op.reg, do_stvx, ea, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n@@ -2640,12 +2641,12 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\tmsrbit = MSR_VEC;\n \t\tif (!(regs->msr & msrbit))\n \t\t\treturn 0;\n-\t\tif (!address_ok(regs, op.ea, size))\n+\t\tif (!address_ok(regs, ea, size))\n \t\t\treturn 0;\n \n \t\tstore_vsrn(op.reg, &buf);\n \t\temulate_vsx_store(&op, &buf, mem);\n-\t\tif (__copy_to_user((void __user *)op.ea, mem, size))\n+\t\tif (__copy_to_user((void __user *)ea, mem, size))\n \t\t\treturn 0;\n \t\tgoto ldst_done;\n \t}\n@@ -2661,10 +2662,10 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \t\t\t\tnb = 4;\n \t\t\telse\n \t\t\t\tval >>= 32 - 8 * nb;\n-\t\t\terr = write_mem(val, op.ea, nb, regs);\n+\t\t\terr = write_mem(val, ea, nb, regs);\n \t\t\tif (err)\n \t\t\t\treturn 0;\n-\t\t\top.ea += 4;\n+\t\t\tea += 4;\n \t\t\t++rd;\n \t\t}\n \t\tgoto instr_done;\n", "prefixes": [ "v3", "05/17" ] }