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GET /api/patches/807378/?format=api
{ "id": 807378, "url": "http://patchwork.ozlabs.org/api/patches/807378/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830023856.GC26152@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170830023856.GC26152@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170830023856.GC26152@us.ibm.com/", "date": "2017-08-30T02:38:56", "name": "[RFC] Interface to set SPRN_TIDR", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": false, "hash": "8837d8ccbe8ab436b80c29485dcd56214eb9da3b", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830023856.GC26152@us.ibm.com/mbox/", "series": [ { "id": 514, "url": "http://patchwork.ozlabs.org/api/series/514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=514", "date": "2017-08-30T02:38:56", "name": "[RFC] Interface to set SPRN_TIDR", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/514/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807378/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807378/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhqVD01NSz9sMN\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 12:40:04 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhqVC6FLkzDqSb\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 12:40:03 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhqT41hf8zDqGG\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 12:39:04 +1000 (AEST)", "from pps.filterd (m0098394.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7U2d27c046620\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 29 Aug 2017 22:39:02 -0400", "from e13.ny.us.ibm.com (e13.ny.us.ibm.com [129.33.205.203])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cnby3rfq3-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 29 Aug 2017 22:39:01 -0400", "from localhost\n\tby e13.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <sukadev@linux.vnet.ibm.com>;\n\tTue, 29 Aug 2017 22:39:00 -0400", "from b01cxnp23034.gho.pok.ibm.com (9.57.198.29)\n\tby e13.ny.us.ibm.com (146.89.104.200) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tTue, 29 Aug 2017 22:38:58 -0400", "from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com\n\t[9.57.199.107])\n\tby b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7U2cwZ321626916; Wed, 30 Aug 2017 02:38:58 GMT", "from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 0C986124035;\n\tTue, 29 Aug 2017 22:36:18 -0400 (EDT)", "from suka-w540.localdomain (unknown [9.70.94.25])\n\tby b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id B742C12403D;\n\tTue, 29 Aug 2017 22:36:17 -0400 (EDT)", "by suka-w540.localdomain (Postfix, from userid 1000)\n\tid 6025022611A; Tue, 29 Aug 2017 19:38:56 -0700 (PDT)" ], "Date": "Tue, 29 Aug 2017 19:38:56 -0700", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>,\n\tBenjamin Herrenschmidt <benh@kernel.crashing.org>,\n\tmichael.neuling@au1.ibm.com, npiggin@gmail.com", "Subject": "[PATCH RFC] Interface to set SPRN_TIDR", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "X-Operating-System": "Linux 2.0.32 on an i486", "User-Agent": "Mutt/1.7.1 (2016-10-04)", "X-TM-AS-GCONF": "00", "x-cbid": "17083002-0008-0000-0000-0000027674E1", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007634; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909522; UDB=6.00456165;\n\tIPR=6.00689807; \n\tBA=6.00005560; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016924;\n\tXFM=3.00000015; UTC=2017-08-30 02:39:00", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17083002-0009-0000-0000-0000368876F2", "Message-Id": "<20170830023856.GC26152@us.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-30_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708300039", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@lists.ozlabs.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "We need the SPRN_TIDR to be set for use with fast thread-wakeup\n(core-to-core wakeup) in VAS. Each user thread that has a receive\nwindow setup and expects to be notified when a sender issues a paste\nneeds to have a unique SPRN_TIDR value.\n\nThe SPRN_TIDR value only needs to unique within the process but for\nnow we use a globally unique thread id as described below.\n\nSigned-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>\n---\nChangelog[v2]\n\t- Michael Ellerman: Use an interface to assign TIDR so it is\n\t assigned to only threads that need it; move assignment to\n\t restore_sprs(). Drop lint from rebase;\n\n\n arch/powerpc/include/asm/processor.h | 4 ++\n arch/powerpc/include/asm/switch_to.h | 3 ++\n arch/powerpc/kernel/process.c | 97 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 104 insertions(+)", "diff": "diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h\nindex fab7ff8..bf6ba63 100644\n--- a/arch/powerpc/include/asm/processor.h\n+++ b/arch/powerpc/include/asm/processor.h\n@@ -232,6 +232,10 @@ struct debug_reg {\n struct thread_struct {\n \tunsigned long\tksp;\t\t/* Kernel stack pointer */\n \n+#ifdef CONFIG_PPC_VAS\n+\tunsigned long\ttidr;\n+#endif\n+\n #ifdef CONFIG_PPC64\n \tunsigned long\tksp_vsid;\n #endif\ndiff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h\nindex 17c8380..4962455 100644\n--- a/arch/powerpc/include/asm/switch_to.h\n+++ b/arch/powerpc/include/asm/switch_to.h\n@@ -91,4 +91,7 @@ static inline void clear_task_ebb(struct task_struct *t)\n #endif\n }\n \n+extern void set_thread_tidr(struct task_struct *t);\n+extern void clear_thread_tidr(struct task_struct *t);\n+\n #endif /* _ASM_POWERPC_SWITCH_TO_H */\ndiff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c\nindex 1f0fd36..13abb22 100644\n--- a/arch/powerpc/kernel/process.c\n+++ b/arch/powerpc/kernel/process.c\n@@ -1132,6 +1132,10 @@ static inline void restore_sprs(struct thread_struct *old_thread,\n \t\t\tmtspr(SPRN_TAR, new_thread->tar);\n \t}\n #endif\n+#ifdef CONFIG_PPC_VAS\n+\tif (old_thread->tidr != new_thread->tidr)\n+\t\tmtspr(SPRN_TIDR, new_thread->tidr);\n+#endif\n }\n \n #ifdef CONFIG_PPC_BOOK3S_64\n@@ -1446,9 +1450,97 @@ void flush_thread(void)\n #endif /* CONFIG_HAVE_HW_BREAKPOINT */\n }\n \n+#ifdef CONFIG_PPC_VAS\n+static DEFINE_SPINLOCK(vas_thread_id_lock);\n+static DEFINE_IDA(vas_thread_ida);\n+\n+/*\n+ * We need to assign an unique thread id to each thread in a process. This\n+ * thread id is intended to be used with the Fast Thread-wakeup (aka Core-\n+ * to-core wakeup) mechanism being implemented on top of Virtual Accelerator\n+ * Switchboard (VAS).\n+ *\n+ * To get a unique thread-id per process we could simply use task_pid_nr()\n+ * but the problem is that task_pid_nr() is not yet available for the thread\n+ * when copy_thread() is called. Fixing that would require changing more\n+ * intrusive arch-neutral code in code path in copy_process()?.\n+ *\n+ * Further, to assign unique thread ids within each process, we need an\n+ * atomic field (or an IDR) in task_struct, which again intrudes into the\n+ * arch-neutral code.\n+ *\n+ * So try to assign globally unique thraed ids for now.\n+ *\n+ * NOTE: TIDR 0 indicates that the thread does not need a TIDR value.\n+ * \t For now, only threads that expect to be notified by the VAS\n+ * \t hardware need a TIDR value and we assign values > 0 for those.\n+ */\n+#define MAX_THREAD_CONTEXT\t((1 << 15) - 2)\n+static int assign_thread_tidr(void)\n+{\n+\tint index;\n+\tint err;\n+\n+again:\n+\tif (!ida_pre_get(&vas_thread_ida, GFP_KERNEL))\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock(&vas_thread_id_lock);\n+\terr = ida_get_new_above(&vas_thread_ida, 1, &index);\n+\tspin_unlock(&vas_thread_id_lock);\n+\n+\tif (err == -EAGAIN)\n+\t\tgoto again;\n+\telse if (err)\n+\t\treturn err;\n+\n+\tif (index > MAX_THREAD_CONTEXT) {\n+\t\tspin_lock(&vas_thread_id_lock);\n+\t\tida_remove(&vas_thread_ida, index);\n+\t\tspin_unlock(&vas_thread_id_lock);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn index;\n+}\n+\n+static void free_thread_tidr(int id)\n+{\n+\tspin_lock(&vas_thread_id_lock);\n+\tida_remove(&vas_thread_ida, id);\n+\tspin_unlock(&vas_thread_id_lock);\n+}\n+\n+void clear_thread_tidr(struct task_struct *t)\n+{\n+\tif (t->thread.tidr) {\n+\t\tfree_thread_tidr(t->thread.tidr);\n+\t\tt->thread.tidr = 0;\n+\t\tmtspr(SPRN_TIDR, 0);\n+\t}\n+}\n+\n+/*\n+ * Assign an unique thread id for this thread and set it in the\n+ * thread structure. For now, we need this interface only for\n+ * the current task.\n+ */\n+void set_thread_tidr(struct task_struct *t)\n+{\n+\tWARN_ON(t != current);\n+\tt->thread.tidr = assign_thread_tidr();\n+\tmtspr(SPRN_TIDR, t->thread.tidr);\n+}\n+\n+#endif /* CONFIG_PPC_VAS */\n+\n+\n void\n release_thread(struct task_struct *t)\n {\n+#ifdef CONFIG_PPC_VAS\n+\tclear_thread_tidr(t);\n+#endif\n }\n \n /*\n@@ -1474,6 +1566,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)\n \n \tclear_task_ebb(dst);\n \n+\tdst->thread.tidr = 0;\n+\n \treturn 0;\n }\n \n@@ -1584,6 +1678,9 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,\n #endif\n \n \tsetup_ksp_vsid(p, sp);\n+#ifdef CONFIG_PPC_VAS\n+\tp->thread.tidr = 0;\n+#endif\n \n #ifdef CONFIG_PPC64 \n \tif (cpu_has_feature(CPU_FTR_DSCR)) {\n", "prefixes": [ "RFC" ] }