Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/807337/?format=api
{ "id": 807337, "url": "http://patchwork.ozlabs.org/api/patches/807337/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504045082-16178-2-git-send-email-joserz@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504045082-16178-2-git-send-email-joserz@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504045082-16178-2-git-send-email-joserz@linux.vnet.ibm.com/", "date": "2017-08-29T22:18:02", "name": "[RFC] KVM: PPC: Book3S: Add MMIO emulation for VMX instructions", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "98d30ad85633b8e3a466798dbd1db2f2ec61a5d9", "submitter": { "id": 70266, "url": "http://patchwork.ozlabs.org/api/people/70266/?format=api", "name": "Jose Ricardo Ziviani", "email": "joserz@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504045082-16178-2-git-send-email-joserz@linux.vnet.ibm.com/mbox/", "series": [ { "id": 496, "url": "http://patchwork.ozlabs.org/api/series/496/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=496", "date": "2017-08-29T22:18:02", "name": "[RFC] KVM: PPC: Book3S: Add MMIO emulation for VMX instructions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/496/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807337/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807337/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhjlJ2dkSz9sN7\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 08:21:00 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhjlJ1c2hzDqYY\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 08:21:00 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhjhh49p6zDqGV\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 30 Aug 2017 08:18:44 +1000 (AEST)", "from pps.filterd (m0098409.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7TMF4CO145468\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 29 Aug 2017 18:18:42 -0400", "from e15.ny.us.ibm.com (e15.ny.us.ibm.com [129.33.205.205])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cna03m8rq-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Tue, 29 Aug 2017 18:18:39 -0400", "from localhost\n\tby e15.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <joserz@linux.vnet.ibm.com>; \n\tTue, 29 Aug 2017 18:18:38 -0400", "from b01cxnp22034.gho.pok.ibm.com (9.57.198.24)\n\tby e15.ny.us.ibm.com (146.89.104.202) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tTue, 29 Aug 2017 18:18:35 -0400", "from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com\n\t[9.57.199.111])\n\tby b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7TMIZUh22806566; Tue, 29 Aug 2017 22:18:35 GMT", "from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id BE47CAC04A;\n\tTue, 29 Aug 2017 18:18:59 -0400 (EDT)", "from pacoca.ibm.com (unknown [9.85.162.40])\n\tby b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 77C90AC046;\n\tTue, 29 Aug 2017 18:18:58 -0400 (EDT)" ], "From": "Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH RFC] KVM: PPC: Book3S: Add MMIO emulation for VMX\n\tinstructions", "Date": "Tue, 29 Aug 2017 19:18:02 -0300", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504045082-16178-1-git-send-email-joserz@linux.vnet.ibm.com>", "References": "<1504045082-16178-1-git-send-email-joserz@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17082922-0036-0000-0000-00000260BB10", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007633; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909435; UDB=6.00456113;\n\tIPR=6.00689720; \n\tBA=6.00005560; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016923;\n\tXFM=3.00000015; UTC=2017-08-29 22:18:37", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082922-0037-0000-0000-00004198C60D", "Message-Id": "<1504045082-16178-2-git-send-email-joserz@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_10:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290336", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "paulus@samba.org, agraf@suse.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "This patch provides the MMIO load/store vector indexed\nX-Form emulation.\n\nInstructions implemented: lvx, stvx\n\nSigned-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>\n---\n arch/powerpc/include/asm/kvm_host.h | 2 +\n arch/powerpc/include/asm/kvm_ppc.h | 4 +\n arch/powerpc/include/asm/ppc-opcode.h | 6 ++\n arch/powerpc/kvm/emulate_loadstore.c | 32 +++++++\n arch/powerpc/kvm/powerpc.c | 162 ++++++++++++++++++++++++++++++----\n 5 files changed, 189 insertions(+), 17 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h\nindex 8b3f123..5835163 100644\n--- a/arch/powerpc/include/asm/kvm_host.h\n+++ b/arch/powerpc/include/asm/kvm_host.h\n@@ -697,6 +697,7 @@ struct kvm_vcpu_arch {\n \tu8 mmio_vsx_offset;\n \tu8 mmio_vsx_copy_type;\n \tu8 mmio_vsx_tx_sx_enabled;\n+\tu8 mmio_vmx_copy_nums;\n \tu8 osi_needed;\n \tu8 osi_enabled;\n \tu8 papr_enabled;\n@@ -807,6 +808,7 @@ struct kvm_vcpu_arch {\n #define KVM_MMIO_REG_QPR\t0x0040\n #define KVM_MMIO_REG_FQPR\t0x0060\n #define KVM_MMIO_REG_VSX\t0x0080\n+#define KVM_MMIO_REG_VMX\t0x00a0\n \n #define __KVM_HAVE_ARCH_WQP\n #define __KVM_HAVE_CREATE_DEVICE\ndiff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h\nindex ba5fadd..c444d16 100644\n--- a/arch/powerpc/include/asm/kvm_ppc.h\n+++ b/arch/powerpc/include/asm/kvm_ppc.h\n@@ -81,6 +81,10 @@ extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu,\n extern int kvmppc_handle_vsx_load(struct kvm_run *run, struct kvm_vcpu *vcpu,\n \t\t\t\tunsigned int rt, unsigned int bytes,\n \t\t\tint is_default_endian, int mmio_sign_extend);\n+extern int kvmppc_handle_load128_by2x64(struct kvm_run *run,\n+\t\tstruct kvm_vcpu *vcpu, unsigned int rt, int is_default_endian);\n+extern int kvmppc_handle_store128_by2x64(struct kvm_run *run,\n+\t\tstruct kvm_vcpu *vcpu, unsigned int rs, int is_default_endian);\n extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,\n \t\t\t u64 val, unsigned int bytes,\n \t\t\t int is_default_endian);\ndiff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h\nindex fa9ebae..ea9bf37 100644\n--- a/arch/powerpc/include/asm/ppc-opcode.h\n+++ b/arch/powerpc/include/asm/ppc-opcode.h\n@@ -156,6 +156,12 @@\n #define OP_31_XOP_LFDX 599\n #define OP_31_XOP_LFDUX\t\t631\n \n+/* VMX Vector Load Instructions */\n+#define OP_31_XOP_LVX 103\n+\n+/* VMX Vector Store Instructions */\n+#define OP_31_XOP_STVX 231\n+\n #define OP_LWZ 32\n #define OP_STFS 52\n #define OP_STFSU 53\ndiff --git a/arch/powerpc/kvm/emulate_loadstore.c b/arch/powerpc/kvm/emulate_loadstore.c\nindex af83353..40fbc14 100644\n--- a/arch/powerpc/kvm/emulate_loadstore.c\n+++ b/arch/powerpc/kvm/emulate_loadstore.c\n@@ -58,6 +58,18 @@ static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)\n }\n #endif /* CONFIG_VSX */\n \n+#ifdef CONFIG_ALTIVEC\n+static bool kvmppc_check_altivec_disabled(struct kvm_vcpu *vcpu)\n+{\n+\tif (!(kvmppc_get_msr(vcpu) & MSR_VEC)) {\n+\t\tkvmppc_core_queue_vec_unavail(vcpu);\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+#endif /* CONFIG_ALTIVEC */\n+\n /*\n * XXX to do:\n * lfiwax, lfiwzx\n@@ -98,6 +110,7 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \tvcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_NONE;\n \tvcpu->arch.mmio_sp64_extend = 0;\n \tvcpu->arch.mmio_sign_extend = 0;\n+\tvcpu->arch.mmio_vmx_copy_nums = 0;\n \n \tswitch (get_op(inst)) {\n \tcase 31:\n@@ -459,6 +472,25 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)\n \t\t\t\t\t\t\t rs, 4, 1);\n \t\t\tbreak;\n #endif /* CONFIG_VSX */\n+\n+#ifdef CONFIG_ALTIVEC\n+\t\tcase OP_31_XOP_LVX:\n+\t\t\tif (kvmppc_check_altivec_disabled(vcpu))\n+\t\t\t\treturn EMULATE_DONE;\n+\t\t\tvcpu->arch.mmio_vmx_copy_nums = 2;\n+\t\t\temulated = kvmppc_handle_load128_by2x64(run, vcpu,\n+\t\t\t\t\tKVM_MMIO_REG_VMX|rt, 1);\n+\t\t\tbreak;\n+\n+\t\tcase OP_31_XOP_STVX:\n+\t\t\tif (kvmppc_check_altivec_disabled(vcpu))\n+\t\t\t\treturn EMULATE_DONE;\n+\t\t\tvcpu->arch.mmio_vmx_copy_nums = 2;\n+\t\t\temulated = kvmppc_handle_store128_by2x64(run, vcpu,\n+\t\t\t\t\trs, 1);\n+\t\t\tbreak;\n+#endif /* CONFIG_ALTIVEC */\n+\n \t\tdefault:\n \t\t\temulated = EMULATE_FAIL;\n \t\t\tbreak;\ndiff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c\nindex 1a75c0b..dc3611b 100644\n--- a/arch/powerpc/kvm/powerpc.c\n+++ b/arch/powerpc/kvm/powerpc.c\n@@ -828,23 +828,7 @@ void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,\n \t\tkvm->arch.kvm_ops->irq_bypass_del_producer(cons, prod);\n }\n \n-#ifdef CONFIG_VSX\n-static inline int kvmppc_get_vsr_dword_offset(int index)\n-{\n-\tint offset;\n-\n-\tif ((index != 0) && (index != 1))\n-\t\treturn -1;\n-\n-#ifdef __BIG_ENDIAN\n-\toffset = index;\n-#else\n-\toffset = 1 - index;\n-#endif\n-\n-\treturn offset;\n-}\n-\n+#ifdef CONFIG_ALTIVEC\n static inline int kvmppc_get_vsr_word_offset(int index)\n {\n \tint offset;\n@@ -860,6 +844,40 @@ static inline int kvmppc_get_vsr_word_offset(int index)\n \treturn offset;\n }\n \n+static inline void kvmppc_set_vmx_dword(struct kvm_vcpu *vcpu,\n+\t\tu64 gpr)\n+{\n+\tint index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;\n+\tu64 hi = gpr >> 32;\n+\tu64 lo = gpr & 0xffffffff;\n+\n+\tif (vcpu->arch.mmio_vmx_copy_nums == 1) {\n+\t\tVCPU_VSX_VR(vcpu, index).u[kvmppc_get_vsr_word_offset(2)] = hi;\n+\t\tVCPU_VSX_VR(vcpu, index).u[kvmppc_get_vsr_word_offset(3)] = lo;\n+\t} else if (vcpu->arch.mmio_vmx_copy_nums == 2) {\n+\t\tVCPU_VSX_VR(vcpu, index).u[kvmppc_get_vsr_word_offset(0)] = hi;\n+\t\tVCPU_VSX_VR(vcpu, index).u[kvmppc_get_vsr_word_offset(1)] = lo;\n+\t}\n+}\n+#endif /* CONFIG_ALTIVEC */\n+\n+#ifdef CONFIG_VSX\n+static inline int kvmppc_get_vsr_dword_offset(int index)\n+{\n+\tint offset;\n+\n+\tif ((index != 0) && (index != 1))\n+\t\treturn -1;\n+\n+#ifdef __BIG_ENDIAN\n+\toffset = index;\n+#else\n+\toffset = 1 - index;\n+#endif\n+\n+\treturn offset;\n+}\n+\n static inline void kvmppc_set_vsr_dword(struct kvm_vcpu *vcpu,\n \tu64 gpr)\n {\n@@ -1024,6 +1042,11 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,\n \t\t\tkvmppc_set_vsr_dword_dump(vcpu, gpr);\n \t\tbreak;\n #endif\n+#ifdef CONFIG_ALTIVEC\n+\tcase KVM_MMIO_REG_VMX:\n+\t\tkvmppc_set_vmx_dword(vcpu, gpr);\n+\t\tbreak;\n+#endif\n \tdefault:\n \t\tBUG();\n \t}\n@@ -1303,6 +1326,99 @@ static int kvmppc_emulate_mmio_vsx_loadstore(struct kvm_vcpu *vcpu,\n }\n #endif /* CONFIG_VSX */\n \n+#ifdef CONFIG_ALTIVEC\n+/* handle quadword load access in two halves */\n+int kvmppc_handle_load128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu,\n+\t\tunsigned int rt, int is_default_endian)\n+{\n+\tenum emulation_result emulated = EMULATE_DONE;\n+\n+\twhile (vcpu->arch.mmio_vmx_copy_nums) {\n+\t\temulated = __kvmppc_handle_load(run, vcpu, rt, 8,\n+\t\t\t\tis_default_endian, 0);\n+\t\tif (emulated != EMULATE_DONE)\n+\t\t\tbreak;\n+\n+\t\tvcpu->arch.mmio_vmx_copy_nums--;\n+\t}\n+\treturn emulated;\n+}\n+\n+static inline int kvmppc_get_vmx_data(struct kvm_vcpu *vcpu, int rs, u64 *val)\n+{\n+\n+\tif (vcpu->arch.mmio_vmx_copy_nums == 1) {\n+\t\t*val = VCPU_VSX_VR(vcpu, rs).u[kvmppc_get_vsr_word_offset(2)];\n+\t\t*val = (*val << 32) | VCPU_VSX_VR(vcpu, rs).\n+\t\t\tu[kvmppc_get_vsr_word_offset(3)];\n+\t\treturn 0;\n+\t} else if (vcpu->arch.mmio_vmx_copy_nums == 2) {\n+\t\t*val = VCPU_VSX_VR(vcpu, rs).u[kvmppc_get_vsr_word_offset(0)];\n+\t\t*val = (*val << 32) | VCPU_VSX_VR(vcpu, rs).\n+\t\t\tu[kvmppc_get_vsr_word_offset(1)];\n+\t\treturn 0;\n+\t}\n+\treturn -1;\n+}\n+\n+/* handle quadword store in two halves */\n+int kvmppc_handle_store128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu,\n+\t\tunsigned int rs, int is_default_endian)\n+{\n+\tu64 val = 0;\n+\tenum emulation_result emulated = EMULATE_DONE;\n+\n+\tvcpu->arch.io_gpr = rs;\n+\n+\twhile (vcpu->arch.mmio_vmx_copy_nums) {\n+\t\tif (kvmppc_get_vmx_data(vcpu, rs, &val) == -1)\n+\t\t\treturn EMULATE_FAIL;\n+\n+\t\temulated = kvmppc_handle_store(run, vcpu, val, 8,\n+\t\t\t\tis_default_endian);\n+\t\tif (emulated != EMULATE_DONE)\n+\t\t\tbreak;\n+\n+\t\tvcpu->arch.mmio_vmx_copy_nums--;\n+\t}\n+\treturn emulated;\n+}\n+\n+static int kvmppc_emulate_mmio_vmx_loadstore(struct kvm_vcpu *vcpu,\n+\t\tstruct kvm_run *run)\n+{\n+\tenum emulation_result emulated = EMULATE_FAIL;\n+\tint r;\n+\n+\tvcpu->arch.paddr_accessed += run->mmio.len;\n+\n+\tif (!vcpu->mmio_is_write) {\n+\t\temulated = kvmppc_handle_load128_by2x64(run, vcpu,\n+\t\t\t\tvcpu->arch.io_gpr, 1);\n+\t} else {\n+\t\temulated = kvmppc_handle_store128_by2x64(run, vcpu,\n+\t\t\t\tvcpu->arch.io_gpr, 1);\n+\t}\n+\n+\tswitch (emulated) {\n+\tcase EMULATE_DO_MMIO:\n+\t\trun->exit_reason = KVM_EXIT_MMIO;\n+\t\tr = RESUME_HOST;\n+\t\tbreak;\n+\tcase EMULATE_FAIL:\n+\t\tpr_info(\"KVM: MMIO emulation failed (VMX repeat)\\n\");\n+\t\trun->exit_reason = KVM_EXIT_INTERNAL_ERROR;\n+\t\trun->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;\n+\t\tr = RESUME_HOST;\n+\t\tbreak;\n+\tdefault:\n+\t\tr = RESUME_GUEST;\n+\t\tbreak;\n+\t}\n+\treturn r;\n+}\n+#endif /* CONFIG_ALTIVEC */\n+\n int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)\n {\n \tint r = 0;\n@@ -1423,6 +1539,18 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)\n \t\t\t}\n \t\t}\n #endif\n+#ifdef CONFIG_ALTIVEC\n+\t\tif (vcpu->arch.mmio_vmx_copy_nums > 0)\n+\t\t\tvcpu->arch.mmio_vmx_copy_nums--;\n+\n+\t\tif (vcpu->arch.mmio_vmx_copy_nums > 0) {\n+\t\t\tr = kvmppc_emulate_mmio_vmx_loadstore(vcpu, run);\n+\t\t\tif (r == RESUME_HOST) {\n+\t\t\t\tvcpu->mmio_needed = 1;\n+\t\t\t\treturn r;\n+\t\t\t}\n+\t\t}\n+#endif\n \t} else if (vcpu->arch.osi_needed) {\n \t\tu64 *gprs = run->osi.gprs;\n \t\tint i;\n", "prefixes": [ "RFC" ] }