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GET /api/patches/807299/?format=api
{ "id": 807299, "url": "http://patchwork.ozlabs.org/api/patches/807299/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829204759.6853-3-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170829204759.6853-3-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-08-29T20:47:53", "name": "[2/8] tcg/s390: Merge cmpi facilities check to tcg_target_op_def", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "037291e7179e0c15cfca05eba2be1e95e1c6004e", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829204759.6853-3-richard.henderson@linaro.org/mbox/", "series": [ { "id": 471, "url": "http://patchwork.ozlabs.org/api/series/471/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=471", "date": "2017-08-29T20:47:53", "name": null, "version": 1, "mbox": "http://patchwork.ozlabs.org/series/471/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807299/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807299/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"iMIjUXj5\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhgj23lS1z9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 06:48:53 +1000 (AEST)", "from localhost ([::1]:46889 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmnRL-0002RH-2k\n\tfor incoming@patchwork.ozlabs.org; Tue, 29 Aug 2017 16:48:51 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:49460)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dmnQe-0002Qj-Ce\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:10 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dmnQc-0001Tn-TK\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:08 -0400", "from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:38035)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dmnQc-0001TR-M5\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:06 -0400", "by mail-pg0-x22e.google.com with SMTP id b8so13996915pgn.5\n\tfor <qemu-devel@nongnu.org>; Tue, 29 Aug 2017 13:48:06 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\ti84sm6633646pfj.139.2017.08.29.13.48.03\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 29 Aug 2017 13:48:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=IkhOz8fuRRbqd88aKtALrzqnsmouosc8HzWR3BAvgGo=;\n\tb=iMIjUXj5JgBytASQIkrvzL+ci3mugMs0cs9RVGei3DZAWe8yXJvz2k/LfVgqxHk7cv\n\tFP0mwRVJlwvt45Ir7RCEL6+i/xyIw3FPkAOEGnyvrN/taQlIf3Dc8IqssFF/bIs9mV8/\n\t90jW/CLMh7UninvYgiZzwf0dtdM2+qVUVmi9c=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=IkhOz8fuRRbqd88aKtALrzqnsmouosc8HzWR3BAvgGo=;\n\tb=WBV5S7mq+SYdcbV/E3wwmq4Dhklos/fIH4yXf6nwZ1trpSQEuV04AYdak9SABvVOTc\n\tSxzUmPQK9Ge/kvC1taOzGzhyVsSl/OzEWKLylL2O0LjrLEizQK0HEFXSGxo4XnXrL3E1\n\t19/+k4t7yMZqibGGvWDlWHBbPGsiTbYymtj/mTyVKqu2l2qbChhOiqgmnMLJTlQNoZQ+\n\tWqnnsNwEUDp/YXlVggEDQ23A+ZK1wFj4fsrdSNUKb2NvcRBYK/GsvffzjVoxCRinWAVN\n\tQQHEVX5mDFKSopb77c2WdbwCbjfRYzYNr+pvAfrNavP00qm4MfkTHSXFlR5KZB+Oo+nc\n\tEz1w==", "X-Gm-Message-State": "AHYfb5hPD+NguLN6tbhYPQcjIfzZMzWT/Z53O6ZvizHrxXtqmacvl4QO\n\tGNHb3iw1Sw0PLJH6DhzvAA==", "X-Received": "by 10.99.0.211 with SMTP id 202mr1448497pga.405.1504039685335;\n\tTue, 29 Aug 2017 13:48:05 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Tue, 29 Aug 2017 13:47:53 -0700", "Message-Id": "<20170829204759.6853-3-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170829204759.6853-1-richard.henderson@linaro.org>", "References": "<20170829204759.6853-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22e", "Subject": "[Qemu-devel] [PATCH 2/8] tcg/s390: Merge cmpi facilities check to\n\ttcg_target_op_def", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de,\n\tRichard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n tcg/s390/tcg-target.inc.c | 68 +++++++++++++++++++++--------------------------\n 1 file changed, 30 insertions(+), 38 deletions(-)", "diff": "diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex d34649eb13..e075b4844a 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -41,7 +41,7 @@\n #define TCG_CT_CONST_MULI 0x100\n #define TCG_CT_CONST_ORI 0x200\n #define TCG_CT_CONST_XORI 0x400\n-#define TCG_CT_CONST_CMPI 0x800\n+#define TCG_CT_CONST_U31 0x800\n #define TCG_CT_CONST_ADLI 0x1000\n #define TCG_CT_CONST_ZERO 0x2000\n \n@@ -398,7 +398,18 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n ct->ct |= TCG_CT_CONST_XORI;\n break;\n case 'C':\n- ct->ct |= TCG_CT_CONST_CMPI;\n+ /* ??? We have no insight here into whether the comparison is\n+ signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n+ signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses\n+ a 32-bit unsigned immediate. If we were to use the (semi)\n+ obvious \"val == (int32_t)val\" we would be enabling unsigned\n+ comparisons vs very large numbers. The only solution is to\n+ take the intersection of the ranges. */\n+ /* ??? Another possible solution is to simply lie and allow all\n+ constants here and force the out-of-range values into a temp\n+ register in tgen_cmp when we have knowledge of the actual\n+ comparison code in use. */\n+ ct->ct |= TCG_CT_CONST_U31;\n break;\n case 'Z':\n ct->ct |= TCG_CT_CONST_ZERO;\n@@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_long val)\n return 1;\n }\n \n-/* Imediates to be used with comparisons. */\n-\n-static int tcg_match_cmpi(TCGType type, tcg_target_long val)\n-{\n- if (s390_facilities & FACILITY_EXT_IMM) {\n- /* The COMPARE IMMEDIATE instruction is available. */\n- if (type == TCG_TYPE_I32) {\n- /* We have a 32-bit immediate and can compare against anything. */\n- return 1;\n- } else {\n- /* ??? We have no insight here into whether the comparison is\n- signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n- signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses\n- a 32-bit unsigned immediate. If we were to use the (semi)\n- obvious \"val == (int32_t)val\" we would be enabling unsigned\n- comparisons vs very large numbers. The only solution is to\n- take the intersection of the ranges. */\n- /* ??? Another possible solution is to simply lie and allow all\n- constants here and force the out-of-range values into a temp\n- register in tgen_cmp when we have knowledge of the actual\n- comparison code in use. */\n- return val >= 0 && val <= 0x7fffffff;\n- }\n- } else {\n- /* Only the LOAD AND TEST instruction is available. */\n- return val == 0;\n- }\n-}\n-\n /* Immediates to be used with add2/sub2. */\n \n static int tcg_match_add2i(TCGType type, tcg_target_long val)\n@@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return tcg_match_ori(type, val);\n } else if (ct & TCG_CT_CONST_XORI) {\n return tcg_match_xori(type, val);\n- } else if (ct & TCG_CT_CONST_CMPI) {\n- return tcg_match_cmpi(type, val);\n+ } else if (ct & TCG_CT_CONST_U31) {\n+ return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n return val == 0;\n }\n@@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_r = { .args_ct_str = { \"r\", \"r\" } };\n static const TCGTargetOpDef r_L = { .args_ct_str = { \"r\", \"L\" } };\n static const TCGTargetOpDef L_L = { .args_ct_str = { \"L\", \"L\" } };\n+ static const TCGTargetOpDef r_ri = { .args_ct_str = { \"r\", \"ri\" } };\n static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n+ static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rK = { .args_ct_str = { \"r\", \"0\", \"rK\" } };\n@@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r_ri;\n \n case INDEX_op_brcond_i32:\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ);\n case INDEX_op_brcond_i64:\n- return &r_rC;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ);\n \n case INDEX_op_bswap16_i32:\n case INDEX_op_bswap16_i64:\n@@ -2366,16 +2352,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_setcond_i32:\n case INDEX_op_setcond_i64:\n {\n- static const TCGTargetOpDef setc\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ static const TCGTargetOpDef setc_z\n+ = { .args_ct_str = { \"r\", \"r\", \"rZ\" } };\n+ static const TCGTargetOpDef setc_c\n = { .args_ct_str = { \"r\", \"r\", \"rC\" } };\n- return &setc;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z);\n }\n case INDEX_op_movcond_i32:\n case INDEX_op_movcond_i64:\n {\n- static const TCGTargetOpDef movc\n+ /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n+ static const TCGTargetOpDef movc_z\n+ = { .args_ct_str = { \"r\", \"r\", \"rZ\", \"r\", \"0\" } };\n+ static const TCGTargetOpDef movc_c\n = { .args_ct_str = { \"r\", \"r\", \"rC\", \"r\", \"0\" } };\n- return &movc;\n+ return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z);\n }\n case INDEX_op_div2_i32:\n case INDEX_op_div2_i64:\n", "prefixes": [ "2/8" ] }