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GET /api/patches/807249/?format=api
{ "id": 807249, "url": "http://patchwork.ozlabs.org/api/patches/807249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1504034731-31613-1-git-send-email-f.fainelli@gmail.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504034731-31613-1-git-send-email-f.fainelli@gmail.com>", "list_archive_url": null, "date": "2017-08-29T19:25:31", "name": "[net-next,v2] net: bcmgenet: Use correct I/O accessors", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8349289b1fe1c6c7702748dc63ed3f0b9def558c", "submitter": { "id": 2800, "url": "http://patchwork.ozlabs.org/api/people/2800/?format=api", "name": "Florian Fainelli", "email": "f.fainelli@gmail.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1504034731-31613-1-git-send-email-f.fainelli@gmail.com/mbox/", "series": [ { "id": 451, "url": "http://patchwork.ozlabs.org/api/series/451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=451", "date": "2017-08-29T19:25:31", "name": "[net-next,v2] net: bcmgenet: Use correct I/O accessors", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/451/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Ai0HrCAr\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhdzg54Nfz9sRV\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 30 Aug 2017 05:31:27 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751453AbdH2TbZ (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tTue, 29 Aug 2017 15:31:25 -0400", "from mail-wr0-f196.google.com ([209.85.128.196]:37167 \"EHLO\n\tmail-wr0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751233AbdH2TbY (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Tue, 29 Aug 2017 15:31:24 -0400", "by mail-wr0-f196.google.com with SMTP id k9so160110wre.4\n\tfor <netdev@vger.kernel.org>; Tue, 29 Aug 2017 12:31:23 -0700 (PDT)", "from stb-bld-04.irv.broadcom.com ([192.19.255.250])\n\tby smtp.gmail.com with ESMTPSA id\n\t95sm2714891wrm.33.2017.08.29.12.31.19\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 29 Aug 2017 12:31:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id;\n\tbh=v1fdNmnUpJ3a/1etqtE/novFxmdB8t6xm1uoxOjKiKQ=;\n\tb=Ai0HrCArHOuonYtxCFrwwNjEREVztib9bwM+zRGNTglOWGYLqqOFDDS+F82FUIOIEI\n\toox9GYcG0aETIyIyYiqPRyuQOroK88xwyEbHscOtSTq17nJnJ+jIVZHChXHzybqV/C2V\n\t/6j+l57rVFlkZpCJ11jbd6agfy1OPLWeGSQeRSUG4RY4ak6m4kS79gOer/Fj4sZA3Nq2\n\t4FOlwIJZiyzLdoDMMIngIe7dFYp9Lx/CiXSY4YHKZ9v8hySPEm2JmMAs+Hg/t0ZTTnds\n\tlP7tqTNByvKQxTHYNg4yqOTr/l/miU4GgLJzHJXe0hu+wA5517pG4nFdtJU/MdbNL+cF\n\tWcrg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=v1fdNmnUpJ3a/1etqtE/novFxmdB8t6xm1uoxOjKiKQ=;\n\tb=XvHorQeM0FE2DDZ7b7mQxNEu9kmmG/Iz0lY63RJYU/XOO5iJeRhmjxHUSOr1xnssFD\n\tk8RHVpdVGTwKhtm+3gzUWibZ4loL06pJ+G9/jnvqLBuGodcBODg2T0BXXJtB2uv63kIF\n\te/ggpSsckrWdyxhoZPMd+EI6Yf9Alb0SH9MYyHjV6gA04sf7LfiC+erpvt7GTYcIXtAZ\n\tFqN0XkCb9p3fsJETmQxnyfLoEQe6by05dhYXLmVwGt5GsqHQfuuoCjLKKShzeKwYTApq\n\tK8XlgLDF/BIqgAjhQDExrzAuA/oA/Xt4QRRnDVW5dMxhsbK1ZK3Gi5fopKdobwIlHPP9\n\tASWQ==", "X-Gm-Message-State": "AHYfb5ggK8f2brO0ddYAf3XRoRmWtWsCnAenH7yVicRH+9lQarLRbQoH\n\tDFFVrUAkEKfFNXiqOs0=", "X-Received": "by 10.223.183.199 with SMTP id t7mr826203wre.57.1504035082473;\n\tTue, 29 Aug 2017 12:31:22 -0700 (PDT)", "From": "Florian Fainelli <f.fainelli@gmail.com>", "To": "netdev@vger.kernel.org", "Cc": "davem@davemloft.net, opendmb@gmail.com, jaedon.shin@gmail.com,\n\tFlorian Fainelli <f.fainelli@gmail.com>", "Subject": "[PATCH net-next v2] net: bcmgenet: Use correct I/O accessors", "Date": "Tue, 29 Aug 2017 12:25:31 -0700", "Message-Id": "<1504034731-31613-1-git-send-email-f.fainelli@gmail.com>", "X-Mailer": "git-send-email 1.9.1", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "The GENET driver currently uses __raw_{read,write}l which means\nnative I/O endian. This works correctly for an ARM LE kernel (default)\nbut fails miserably on an ARM BE (BE8) kernel where registers are kept\nlittle endian, so replace uses with {read,write}l_relaxed here which is\nwhat we want because this is all performance sensitive code.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\nChanges in v2:\n\n- fixed email address\n\n drivers/net/ethernet/broadcom/genet/bcmgenet.c | 75 ++++++++++++++++----------\n drivers/net/ethernet/broadcom/genet/bcmgenet.h | 13 ++++-\n 2 files changed, 58 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\nindex a981c4ee9d72..612d1ef3b5f5 100644\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n@@ -72,23 +72,42 @@\n #define GENET_RDMA_REG_OFF\t(priv->hw_params->rdma_offset + \\\n \t\t\t\tTOTAL_DESC * DMA_DESC_SIZE)\n \n+static inline void bcmgenet_writel(u32 value, void __iomem *offset)\n+{\n+\t/* MIPS chips strapped for BE will automagically configure the\n+\t * peripheral registers for CPU-native byte order.\n+\t */\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))\n+\t\t__raw_writel(value, offset);\n+\telse\n+\t\twritel_relaxed(value, offset);\n+}\n+\n+static inline u32 bcmgenet_readl(void __iomem *offset)\n+{\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))\n+\t\treturn __raw_readl(offset);\n+\telse\n+\t\treturn readl_relaxed(offset);\n+}\n+\n static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,\n \t\t\t\t\t void __iomem *d, u32 value)\n {\n-\t__raw_writel(value, d + DMA_DESC_LENGTH_STATUS);\n+\tbcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);\n }\n \n static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,\n \t\t\t\t\t void __iomem *d)\n {\n-\treturn __raw_readl(d + DMA_DESC_LENGTH_STATUS);\n+\treturn bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);\n }\n \n static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,\n \t\t\t\t void __iomem *d,\n \t\t\t\t dma_addr_t addr)\n {\n-\t__raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);\n+\tbcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);\n \n \t/* Register writes to GISB bus can take couple hundred nanoseconds\n \t * and are done for each packet, save these expensive writes unless\n@@ -96,7 +115,7 @@ static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,\n \t */\n #ifdef CONFIG_PHYS_ADDR_T_64BIT\n \tif (priv->hw_params->flags & GENET_HAS_40BITS)\n-\t\t__raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);\n+\t\tbcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);\n #endif\n }\n \n@@ -113,7 +132,7 @@ static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,\n {\n \tdma_addr_t addr;\n \n-\taddr = __raw_readl(d + DMA_DESC_ADDRESS_LO);\n+\taddr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);\n \n \t/* Register writes to GISB bus can take couple hundred nanoseconds\n \t * and are done for each packet, save these expensive writes unless\n@@ -121,7 +140,7 @@ static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,\n \t */\n #ifdef CONFIG_PHYS_ADDR_T_64BIT\n \tif (priv->hw_params->flags & GENET_HAS_40BITS)\n-\t\taddr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;\n+\t\taddr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;\n #endif\n \treturn addr;\n }\n@@ -156,8 +175,8 @@ static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)\n \tif (GENET_IS_V1(priv))\n \t\treturn bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);\n \telse\n-\t\treturn __raw_readl(priv->base +\n-\t\t\t\tpriv->hw_params->tbuf_offset + TBUF_CTRL);\n+\t\treturn bcmgenet_readl(priv->base +\n+\t\t\t\t priv->hw_params->tbuf_offset + TBUF_CTRL);\n }\n \n static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)\n@@ -165,7 +184,7 @@ static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)\n \tif (GENET_IS_V1(priv))\n \t\tbcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);\n \telse\n-\t\t__raw_writel(val, priv->base +\n+\t\tbcmgenet_writel(val, priv->base +\n \t\t\t\tpriv->hw_params->tbuf_offset + TBUF_CTRL);\n }\n \n@@ -174,8 +193,8 @@ static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)\n \tif (GENET_IS_V1(priv))\n \t\treturn bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);\n \telse\n-\t\treturn __raw_readl(priv->base +\n-\t\t\t\tpriv->hw_params->tbuf_offset + TBUF_BP_MC);\n+\t\treturn bcmgenet_readl(priv->base +\n+\t\t\t\t priv->hw_params->tbuf_offset + TBUF_BP_MC);\n }\n \n static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)\n@@ -183,7 +202,7 @@ static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)\n \tif (GENET_IS_V1(priv))\n \t\tbcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);\n \telse\n-\t\t__raw_writel(val, priv->base +\n+\t\tbcmgenet_writel(val, priv->base +\n \t\t\t\tpriv->hw_params->tbuf_offset + TBUF_BP_MC);\n }\n \n@@ -326,28 +345,28 @@ static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)\n static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,\n \t\t\t\t enum dma_reg r)\n {\n-\treturn __raw_readl(priv->base + GENET_TDMA_REG_OFF +\n-\t\t\tDMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n+\treturn bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +\n+\t\t\t DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n }\n \n static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,\n \t\t\t\t\tu32 val, enum dma_reg r)\n {\n-\t__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +\n+\tbcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +\n \t\t\tDMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n }\n \n static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,\n \t\t\t\t enum dma_reg r)\n {\n-\treturn __raw_readl(priv->base + GENET_RDMA_REG_OFF +\n-\t\t\tDMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n+\treturn bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +\n+\t\t\t DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n }\n \n static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,\n \t\t\t\t\tu32 val, enum dma_reg r)\n {\n-\t__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +\n+\tbcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +\n \t\t\tDMA_RINGS_SIZE + bcmgenet_dma_regs[r]);\n }\n \n@@ -418,16 +437,16 @@ static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,\n \t\t\t\t\t unsigned int ring,\n \t\t\t\t\t enum dma_ring_reg r)\n {\n-\treturn __raw_readl(priv->base + GENET_TDMA_REG_OFF +\n-\t\t\t(DMA_RING_SIZE * ring) +\n-\t\t\tgenet_dma_ring_regs[r]);\n+\treturn bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +\n+\t\t\t (DMA_RING_SIZE * ring) +\n+\t\t\t genet_dma_ring_regs[r]);\n }\n \n static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,\n \t\t\t\t\t unsigned int ring, u32 val,\n \t\t\t\t\t enum dma_ring_reg r)\n {\n-\t__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +\n+\tbcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +\n \t\t\t(DMA_RING_SIZE * ring) +\n \t\t\tgenet_dma_ring_regs[r]);\n }\n@@ -436,16 +455,16 @@ static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,\n \t\t\t\t\t unsigned int ring,\n \t\t\t\t\t enum dma_ring_reg r)\n {\n-\treturn __raw_readl(priv->base + GENET_RDMA_REG_OFF +\n-\t\t\t(DMA_RING_SIZE * ring) +\n-\t\t\tgenet_dma_ring_regs[r]);\n+\treturn bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +\n+\t\t\t (DMA_RING_SIZE * ring) +\n+\t\t\t genet_dma_ring_regs[r]);\n }\n \n static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,\n \t\t\t\t\t unsigned int ring, u32 val,\n \t\t\t\t\t enum dma_ring_reg r)\n {\n-\t__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +\n+\tbcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +\n \t\t\t(DMA_RING_SIZE * ring) +\n \t\t\tgenet_dma_ring_regs[r]);\n }\n@@ -991,12 +1010,12 @@ static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)\n \tbcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);\n \n \t/* Enable EEE and switch to a 27Mhz clock automatically */\n-\treg = __raw_readl(priv->base + off);\n+\treg = bcmgenet_readl(priv->base + off);\n \tif (enable)\n \t\treg |= TBUF_EEE_EN | TBUF_PM_EN;\n \telse\n \t\treg &= ~(TBUF_EEE_EN | TBUF_PM_EN);\n-\t__raw_writel(reg, priv->base + off);\n+\tbcmgenet_writel(reg, priv->base + off);\n \n \t/* Do the same for thing for RBUF */\n \treg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);\ndiff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.h b/drivers/net/ethernet/broadcom/genet/bcmgenet.h\nindex 3a34fdba5301..4b31e6c172b6 100644\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h\n@@ -671,12 +671,21 @@ struct bcmgenet_priv {\n static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv,\t\\\n \t\t\t\t\tu32 off)\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\treturn __raw_readl(priv->base + offset + off);\t\t\t\\\n+\t/* MIPS chips strapped for BE will automagically configure the\t\\\n+\t * peripheral registers for CPU-native byte order.\t\t\\\n+\t */\t\t\t\t\t\t\t\t\\\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \\\n+\t\treturn __raw_readl(priv->base + offset + off);\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\treturn readl_relaxed(priv->base + offset + off);\t\\\n }\t\t\t\t\t\t\t\t\t\\\n static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv,\t\\\n \t\t\t\t\tu32 val, u32 off)\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\t__raw_writel(val, priv->base + offset + off);\t\t\t\\\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \\\n+\t\treturn __raw_writel(val, priv->base + offset + off);\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\twritel_relaxed(val, priv->base + offset + off);\t\t\\\n }\n \n GENET_IO_MACRO(ext, GENET_EXT_OFF);\n", "prefixes": [ "net-next", "v2" ] }