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{
    "id": 807160,
    "url": "http://patchwork.ozlabs.org/api/patches/807160/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170829155157.6272-1-wsa+renesas@sang-engineering.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170829155157.6272-1-wsa+renesas@sang-engineering.com>",
    "list_archive_url": null,
    "date": "2017-08-29T15:51:57",
    "name": "[v3] pinctrl: sh-pfc: r8a7795: Add SDHI0-3 support",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "63cf24fd09116e05fdf32ba97fd8352c5e7a45c3",
    "submitter": {
        "id": 69646,
        "url": "http://patchwork.ozlabs.org/api/people/69646/?format=api",
        "name": "Wolfram Sang",
        "email": "wsa+renesas@sang-engineering.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20170829155157.6272-1-wsa+renesas@sang-engineering.com/mbox/",
    "series": [
        {
            "id": 399,
            "url": "http://patchwork.ozlabs.org/api/series/399/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=399",
            "date": "2017-08-29T15:51:57",
            "name": "[v3] pinctrl: sh-pfc: r8a7795: Add SDHI0-3 support",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/399/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/807160/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/807160/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhY6n1g8cz9t38\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 30 Aug 2017 01:52:17 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753052AbdH2PwO (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 29 Aug 2017 11:52:14 -0400",
            "from sauhun.de ([88.99.104.3]:45477 \"EHLO pokefinder.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753006AbdH2PwN (ORCPT <rfc822;linux-gpio@vger.kernel.org>);\n\tTue, 29 Aug 2017 11:52:13 -0400",
            "from localhost (p54B33289.dip0.t-ipconnect.de [84.179.50.137])\n\tby pokefinder.org (Postfix) with ESMTPSA id CA4572C30E3;\n\tTue, 29 Aug 2017 17:52:11 +0200 (CEST)"
        ],
        "From": "Wolfram Sang <wsa+renesas@sang-engineering.com>",
        "To": "linux-gpio@vger.kernel.org",
        "Cc": "linux-renesas-soc@vger.kernel.org,\n\tGeert Uytterhoeven <geert@linux-m68k.org>,\n\tTakeshi Kihara <takeshi.kihara.df@renesas.com>,\n\tDirk Behme <dirk.behme@de.bosch.com>,\n\tWolfram Sang <wsa+renesas@sang-engineering.com>",
        "Subject": "[PATCH v3] pinctrl: sh-pfc: r8a7795: Add SDHI0-3 support",
        "Date": "Tue, 29 Aug 2017 17:51:57 +0200",
        "Message-Id": "<20170829155157.6272-1-wsa+renesas@sang-engineering.com>",
        "X-Mailer": "git-send-email 2.11.0",
        "Sender": "linux-gpio-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "From: Takeshi Kihara <takeshi.kihara.df@renesas.com>\n\nAdd SDHI0-3 support for R-Car H3 ES2.0 based on a patch from the Renesas\nBSP. SDHI pin config is identical to H3 ES1.*.\n\nSigned-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>\nSigned-off-by: Dirk Behme <dirk.behme@de.bosch.com>\nSigned-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>\n---\n\nChanges since V2 (from Dirk):\n\t* re-added Takeshi's SoB and authorship\n\t* rebased to sh-pfc-for-v4.14-tag1\n\t* reworded commit message\n\t* did more testing\n\n drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 275 +++++++++++++++++++++++++++++++++++\n 1 file changed, 275 insertions(+)",
    "diff": "diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c\nindex 8b35772cda9864..b225bc2f9bea9f 100644\n--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c\n+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c\n@@ -2734,6 +2734,213 @@ static const unsigned int scif5_clk_b_mux[] = {\n \tSCK5_B_MARK,\n };\n \n+/* - SDHI0 ------------------------------------------------------------------ */\n+static const unsigned int sdhi0_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 2),\n+};\n+static const unsigned int sdhi0_data1_mux[] = {\n+\tSD0_DAT0_MARK,\n+};\n+static const unsigned int sdhi0_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),\n+\tRCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),\n+};\n+static const unsigned int sdhi0_data4_mux[] = {\n+\tSD0_DAT0_MARK, SD0_DAT1_MARK,\n+\tSD0_DAT2_MARK, SD0_DAT3_MARK,\n+};\n+static const unsigned int sdhi0_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),\n+};\n+static const unsigned int sdhi0_ctrl_mux[] = {\n+\tSD0_CLK_MARK, SD0_CMD_MARK,\n+};\n+static const unsigned int sdhi0_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 12),\n+};\n+static const unsigned int sdhi0_cd_mux[] = {\n+\tSD0_CD_MARK,\n+};\n+static const unsigned int sdhi0_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 13),\n+};\n+static const unsigned int sdhi0_wp_mux[] = {\n+\tSD0_WP_MARK,\n+};\n+/* - SDHI1 ------------------------------------------------------------------ */\n+static const unsigned int sdhi1_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(3, 8),\n+};\n+static const unsigned int sdhi1_data1_mux[] = {\n+\tSD1_DAT0_MARK,\n+};\n+static const unsigned int sdhi1_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi1_data4_mux[] = {\n+\tSD1_DAT0_MARK, SD1_DAT1_MARK,\n+\tSD1_DAT2_MARK, SD1_DAT3_MARK,\n+};\n+static const unsigned int sdhi1_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),\n+};\n+static const unsigned int sdhi1_ctrl_mux[] = {\n+\tSD1_CLK_MARK, SD1_CMD_MARK,\n+};\n+static const unsigned int sdhi1_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(3, 14),\n+};\n+static const unsigned int sdhi1_cd_mux[] = {\n+\tSD1_CD_MARK,\n+};\n+static const unsigned int sdhi1_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(3, 15),\n+};\n+static const unsigned int sdhi1_wp_mux[] = {\n+\tSD1_WP_MARK,\n+};\n+/* - SDHI2 ------------------------------------------------------------------ */\n+static const unsigned int sdhi2_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 2),\n+};\n+static const unsigned int sdhi2_data1_mux[] = {\n+\tSD2_DAT0_MARK,\n+};\n+static const unsigned int sdhi2_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),\n+};\n+static const unsigned int sdhi2_data4_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+};\n+static const unsigned int sdhi2_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),\n+\tRCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),\n+\tRCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),\n+\tRCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),\n+};\n+static const unsigned int sdhi2_data8_mux[] = {\n+\tSD2_DAT0_MARK, SD2_DAT1_MARK,\n+\tSD2_DAT2_MARK, SD2_DAT3_MARK,\n+\tSD2_DAT4_MARK, SD2_DAT5_MARK,\n+\tSD2_DAT6_MARK, SD2_DAT7_MARK,\n+};\n+static const unsigned int sdhi2_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),\n+};\n+static const unsigned int sdhi2_ctrl_mux[] = {\n+\tSD2_CLK_MARK, SD2_CMD_MARK,\n+};\n+static const unsigned int sdhi2_cd_a_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 13),\n+};\n+static const unsigned int sdhi2_cd_a_mux[] = {\n+\tSD2_CD_A_MARK,\n+};\n+static const unsigned int sdhi2_cd_b_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(5, 10),\n+};\n+static const unsigned int sdhi2_cd_b_mux[] = {\n+\tSD2_CD_B_MARK,\n+};\n+static const unsigned int sdhi2_wp_a_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 14),\n+};\n+static const unsigned int sdhi2_wp_a_mux[] = {\n+\tSD2_WP_A_MARK,\n+};\n+static const unsigned int sdhi2_wp_b_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(5, 11),\n+};\n+static const unsigned int sdhi2_wp_b_mux[] = {\n+\tSD2_WP_B_MARK,\n+};\n+static const unsigned int sdhi2_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 6),\n+};\n+static const unsigned int sdhi2_ds_mux[] = {\n+\tSD2_DS_MARK,\n+};\n+/* - SDHI3 ------------------------------------------------------------------ */\n+static const unsigned int sdhi3_data1_pins[] = {\n+\t/* D0 */\n+\tRCAR_GP_PIN(4, 9),\n+};\n+static const unsigned int sdhi3_data1_mux[] = {\n+\tSD3_DAT0_MARK,\n+};\n+static const unsigned int sdhi3_data4_pins[] = {\n+\t/* D[0:3] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+};\n+static const unsigned int sdhi3_data4_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+};\n+static const unsigned int sdhi3_data8_pins[] = {\n+\t/* D[0:7] */\n+\tRCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),\n+\tRCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),\n+\tRCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),\n+\tRCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_data8_mux[] = {\n+\tSD3_DAT0_MARK, SD3_DAT1_MARK,\n+\tSD3_DAT2_MARK, SD3_DAT3_MARK,\n+\tSD3_DAT4_MARK, SD3_DAT5_MARK,\n+\tSD3_DAT6_MARK, SD3_DAT7_MARK,\n+};\n+static const unsigned int sdhi3_ctrl_pins[] = {\n+\t/* CLK, CMD */\n+\tRCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),\n+};\n+static const unsigned int sdhi3_ctrl_mux[] = {\n+\tSD3_CLK_MARK, SD3_CMD_MARK,\n+};\n+static const unsigned int sdhi3_cd_pins[] = {\n+\t/* CD */\n+\tRCAR_GP_PIN(4, 15),\n+};\n+static const unsigned int sdhi3_cd_mux[] = {\n+\tSD3_CD_MARK,\n+};\n+static const unsigned int sdhi3_wp_pins[] = {\n+\t/* WP */\n+\tRCAR_GP_PIN(4, 16),\n+};\n+static const unsigned int sdhi3_wp_mux[] = {\n+\tSD3_WP_MARK,\n+};\n+static const unsigned int sdhi3_ds_pins[] = {\n+\t/* DS */\n+\tRCAR_GP_PIN(4, 17),\n+};\n+static const unsigned int sdhi3_ds_mux[] = {\n+\tSD3_DS_MARK,\n+};\n+\n /* - SCIF Clock ------------------------------------------------------------- */\n static const unsigned int scif_clk_a_pins[] = {\n \t/* SCIF_CLK */\n@@ -2943,6 +3150,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {\n \tSH_PFC_PIN_GROUP(scif5_clk_b),\n \tSH_PFC_PIN_GROUP(scif_clk_a),\n \tSH_PFC_PIN_GROUP(scif_clk_b),\n+\tSH_PFC_PIN_GROUP(sdhi0_data1),\n+\tSH_PFC_PIN_GROUP(sdhi0_data4),\n+\tSH_PFC_PIN_GROUP(sdhi0_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi0_cd),\n+\tSH_PFC_PIN_GROUP(sdhi0_wp),\n+\tSH_PFC_PIN_GROUP(sdhi1_data1),\n+\tSH_PFC_PIN_GROUP(sdhi1_data4),\n+\tSH_PFC_PIN_GROUP(sdhi1_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi1_cd),\n+\tSH_PFC_PIN_GROUP(sdhi1_wp),\n+\tSH_PFC_PIN_GROUP(sdhi2_data1),\n+\tSH_PFC_PIN_GROUP(sdhi2_data4),\n+\tSH_PFC_PIN_GROUP(sdhi2_data8),\n+\tSH_PFC_PIN_GROUP(sdhi2_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_a),\n+\tSH_PFC_PIN_GROUP(sdhi2_cd_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_wp_b),\n+\tSH_PFC_PIN_GROUP(sdhi2_ds),\n+\tSH_PFC_PIN_GROUP(sdhi3_data1),\n+\tSH_PFC_PIN_GROUP(sdhi3_data4),\n+\tSH_PFC_PIN_GROUP(sdhi3_data8),\n+\tSH_PFC_PIN_GROUP(sdhi3_ctrl),\n+\tSH_PFC_PIN_GROUP(sdhi3_cd),\n+\tSH_PFC_PIN_GROUP(sdhi3_wp),\n+\tSH_PFC_PIN_GROUP(sdhi3_ds),\n \tSH_PFC_PIN_GROUP(usb0),\n \tSH_PFC_PIN_GROUP(usb1),\n \tSH_PFC_PIN_GROUP(usb2),\n@@ -3168,6 +3401,44 @@ static const char * const scif_clk_groups[] = {\n \t\"scif_clk_b\",\n };\n \n+static const char * const sdhi0_groups[] = {\n+\t\"sdhi0_data1\",\n+\t\"sdhi0_data4\",\n+\t\"sdhi0_ctrl\",\n+\t\"sdhi0_cd\",\n+\t\"sdhi0_wp\",\n+};\n+\n+static const char * const sdhi1_groups[] = {\n+\t\"sdhi1_data1\",\n+\t\"sdhi1_data4\",\n+\t\"sdhi1_ctrl\",\n+\t\"sdhi1_cd\",\n+\t\"sdhi1_wp\",\n+};\n+\n+static const char * const sdhi2_groups[] = {\n+\t\"sdhi2_data1\",\n+\t\"sdhi2_data4\",\n+\t\"sdhi2_data8\",\n+\t\"sdhi2_ctrl\",\n+\t\"sdhi2_cd_a\",\n+\t\"sdhi2_wp_a\",\n+\t\"sdhi2_cd_b\",\n+\t\"sdhi2_wp_b\",\n+\t\"sdhi2_ds\",\n+};\n+\n+static const char * const sdhi3_groups[] = {\n+\t\"sdhi3_data1\",\n+\t\"sdhi3_data4\",\n+\t\"sdhi3_data8\",\n+\t\"sdhi3_ctrl\",\n+\t\"sdhi3_cd\",\n+\t\"sdhi3_wp\",\n+\t\"sdhi3_ds\",\n+};\n+\n static const char * const usb0_groups[] = {\n \t\"usb0\",\n };\n@@ -3205,6 +3476,10 @@ static const struct sh_pfc_function pinmux_functions[] = {\n \tSH_PFC_FUNCTION(scif4),\n \tSH_PFC_FUNCTION(scif5),\n \tSH_PFC_FUNCTION(scif_clk),\n+\tSH_PFC_FUNCTION(sdhi0),\n+\tSH_PFC_FUNCTION(sdhi1),\n+\tSH_PFC_FUNCTION(sdhi2),\n+\tSH_PFC_FUNCTION(sdhi3),\n \tSH_PFC_FUNCTION(usb0),\n \tSH_PFC_FUNCTION(usb1),\n \tSH_PFC_FUNCTION(usb2),\n",
    "prefixes": [
        "v3"
    ]
}