Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/807062/?format=api
{ "id": 807062, "url": "http://patchwork.ozlabs.org/api/patches/807062/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-16-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-16-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:57", "name": "[U-Boot,15/19] arm: socfpga: Add support to memory allocation in SPL", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "13532cb39940a56b61a9f2517a705a313339fa7d", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-16-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807062/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807062/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRvH59X8z9t3J\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 21:56:30 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid EFD96C2206F; Tue, 29 Aug 2017 11:17:14 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 174DAC21F45;\n\tTue, 29 Aug 2017 11:17:11 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid DEEF0C21D95; Tue, 29 Aug 2017 10:46:47 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id A438DC21E2C\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:43 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:43 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:41 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176717\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:57 +0800", "Message-Id": "<1504003561-6290-16-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 15/19] arm: socfpga: Add support to memory\n\tallocation in SPL", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nAdd support to memory allocation in SPL for preparation to enable FAT\nin SPL. Memory allocation is needed by FAT to work properly.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n include/configs/socfpga_common.h | 23 ++++++++++++++++++++++-\n 1 files changed, 22 insertions(+), 1 deletions(-)", "diff": "diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h\nindex 05b03bd..0f53888 100644\n--- a/include/configs/socfpga_common.h\n+++ b/include/configs/socfpga_common.h\n@@ -292,17 +292,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);\n /*\n * SPL\n *\n- * SRAM Memory layout:\n+ * SRAM Memory layout for gen 5:\n *\n * 0xFFFF_0000 ...... Start of SRAM\n * 0xFFFF_xxxx ...... Top of stack (grows down)\n * 0xFFFF_yyyy ...... Malloc area\n * 0xFFFF_zzzz ...... Global Data\n * 0xFFFF_FF00 ...... End of SRAM\n+ *\n+ * SRAM Memory layout for Arria 10:\n+ * 0xFFE0_0000 ...... Start of SRAM (bottom)\n+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)\n+ * 0xFFEy_yyyy ...... Malloc area (grows up to top)\n+ * 0xFFEz_zzzz ...... Global Data\n+ * 0xFFE3_FFFF ...... End of SRAM (top)\n */\n #define CONFIG_SPL_FRAMEWORK\n #define CONFIG_SPL_TEXT_BASE\t\tCONFIG_SYS_INIT_RAM_ADDR\n #define CONFIG_SPL_MAX_SIZE\t\tCONFIG_SYS_INIT_RAM_SIZE\n+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+/* SPL memory allocation configuration, it is required by FAT feature */\n+#ifndef CONFIG_SYS_SPL_MALLOC_START\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00002000\n+#define CONFIG_SYS_SPL_MALLOC_START\t(CONFIG_SYS_INIT_RAM_SIZE - \\\n+\t\t\t\t\t GENERATED_GBL_DATA_SIZE - \\\n+\t\t\t\t\t CONFIG_SYS_SPL_MALLOC_SIZE + \\\n+\t\t\t\t\t CONFIG_SYS_INIT_RAM_ADDR)\n+#endif\n+#endif\n \n /* SPL SDMMC boot support */\n #ifdef CONFIG_SPL_MMC_SUPPORT\n@@ -332,7 +349,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);\n /*\n * Stack setup\n */\n+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n #define CONFIG_SPL_STACK\t\tCONFIG_SYS_INIT_SP_ADDR\n+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+#define CONFIG_SPL_STACK\t\t(CONFIG_SYS_SPL_MALLOC_START - 1)\n+#endif\n \n /* Extra Environment */\n #ifndef CONFIG_SPL_BUILD\n", "prefixes": [ "U-Boot", "15/19" ] }