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GET /api/patches/807060/?format=api
{ "id": 807060, "url": "http://patchwork.ozlabs.org/api/patches/807060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-7-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-7-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:48", "name": "[U-Boot,06/19] arm: socfpga: Rename the gen5 sdram driver to more specific name", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7bb25dd8f2e1ec53f0c9050254845d3977e01c1a", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-7-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRZH6Yc9z9s65\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 21:42:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 43704C22042; Tue, 29 Aug 2017 10:48:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C3E02C22023;\n\tTue, 29 Aug 2017 10:48:16 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E5FABC21F68; Tue, 29 Aug 2017 10:46:25 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 61635C22026\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:21 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:20 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:18 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176617\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:48 +0800", "Message-Id": "<1504003561-6290-7-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 06/19] arm: socfpga: Rename the gen5 sdram driver\n\tto more specific name", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nCurrent sdram driver is only applied to gen5 device, hence it is better\nto rename sdram driver to more specific name which is related to gen5\ndevice.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n arch/arm/mach-socfpga/include/mach/sdram.h | 436 +-------------------\n .../include/mach/{sdram.h => sdram_gen5.h} | 6 +-\n drivers/ddr/altera/Makefile | 2 +-\n drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0\n 4 files changed, 9 insertions(+), 435 deletions(-)\n copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)\n rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)", "diff": "diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h\nindex b11228f..f471913 100644\n--- a/arch/arm/mach-socfpga/include/mach/sdram.h\n+++ b/arch/arm/mach-socfpga/include/mach/sdram.h\n@@ -1,442 +1,16 @@\n /*\n- * Copyright Altera Corporation (C) 2014-2015\n+ * Copyright (C) 2017 Intel Corporation <www.intel.com>\n *\n- * SPDX-License-Identifier:\tGPL-2.0+\n+ * SPDX-License-Identifier:\tGPL-2.0\n */\n #ifndef\t_SDRAM_H_\n #define\t_SDRAM_H_\n \n #ifndef __ASSEMBLY__\n \n-unsigned long sdram_calculate_size(void);\n-int sdram_mmr_init_full(unsigned int sdr_phy_reg);\n-int sdram_calibration_full(void);\n-\n-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);\n-\n-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);\n-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);\n-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);\n-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);\n-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);\n-\n-#define SDR_CTRLGRP_ADDRESS\t(SOCFPGA_SDR_ADDRESS | 0x5000)\n-\n-struct socfpga_sdr_ctrl {\n-\tu32\tctrl_cfg;\n-\tu32\tdram_timing1;\n-\tu32\tdram_timing2;\n-\tu32\tdram_timing3;\n-\tu32\tdram_timing4;\t/* 0x10 */\n-\tu32\tlowpwr_timing;\n-\tu32\tdram_odt;\n-\tu32\textratime1;\n-\tu32\t__padding0[3];\n-\tu32\tdram_addrw;\t/* 0x2c */\n-\tu32\tdram_if_width;\t/* 0x30 */\n-\tu32\tdram_dev_width;\n-\tu32\tdram_sts;\n-\tu32\tdram_intr;\n-\tu32\tsbe_count;\t/* 0x40 */\n-\tu32\tdbe_count;\n-\tu32\terr_addr;\n-\tu32\tdrop_count;\n-\tu32\tdrop_addr;\t/* 0x50 */\n-\tu32\tlowpwr_eq;\n-\tu32\tlowpwr_ack;\n-\tu32\tstatic_cfg;\n-\tu32\tctrl_width;\t/* 0x60 */\n-\tu32\tcport_width;\n-\tu32\tcport_wmap;\n-\tu32\tcport_rmap;\n-\tu32\trfifo_cmap;\t/* 0x70 */\n-\tu32\twfifo_cmap;\n-\tu32\tcport_rdwr;\n-\tu32\tport_cfg;\n-\tu32\tfpgaport_rst;\t/* 0x80 */\n-\tu32\t__padding1;\n-\tu32\tfifo_cfg;\n-\tu32\tprotport_default;\n-\tu32\tprot_rule_addr;\t/* 0x90 */\n-\tu32\tprot_rule_id;\n-\tu32\tprot_rule_data;\n-\tu32\tprot_rule_rdwr;\n-\tu32\t__padding2[3];\n-\tu32\tmp_priority;\t/* 0xac */\n-\tu32\tmp_weight0;\t/* 0xb0 */\n-\tu32\tmp_weight1;\n-\tu32\tmp_weight2;\n-\tu32\tmp_weight3;\n-\tu32\tmp_pacing0;\t/* 0xc0 */\n-\tu32\tmp_pacing1;\n-\tu32\tmp_pacing2;\n-\tu32\tmp_pacing3;\n-\tu32\tmp_threshold0;\t/* 0xd0 */\n-\tu32\tmp_threshold1;\n-\tu32\tmp_threshold2;\n-\tu32\t__padding3[29];\n-\tu32\tphy_ctrl0;\t/* 0x150 */\n-\tu32\tphy_ctrl1;\n-\tu32\tphy_ctrl2;\n-};\n-\n-/* SDRAM configuration structure for the SPL. */\n-struct socfpga_sdram_config {\n-\tu32\tctrl_cfg;\n-\tu32\tdram_timing1;\n-\tu32\tdram_timing2;\n-\tu32\tdram_timing3;\n-\tu32\tdram_timing4;\n-\tu32\tlowpwr_timing;\n-\tu32\tdram_odt;\n-\tu32\textratime1;\n-\tu32\tdram_addrw;\n-\tu32\tdram_if_width;\n-\tu32\tdram_dev_width;\n-\tu32\tdram_intr;\n-\tu32\tlowpwr_eq;\n-\tu32\tstatic_cfg;\n-\tu32\tctrl_width;\n-\tu32\tcport_width;\n-\tu32\tcport_wmap;\n-\tu32\tcport_rmap;\n-\tu32\trfifo_cmap;\n-\tu32\twfifo_cmap;\n-\tu32\tcport_rdwr;\n-\tu32\tport_cfg;\n-\tu32\tfpgaport_rst;\n-\tu32\tfifo_cfg;\n-\tu32\tmp_priority;\n-\tu32\tmp_weight0;\n-\tu32\tmp_weight1;\n-\tu32\tmp_weight2;\n-\tu32\tmp_weight3;\n-\tu32\tmp_pacing0;\n-\tu32\tmp_pacing1;\n-\tu32\tmp_pacing2;\n-\tu32\tmp_pacing3;\n-\tu32\tmp_threshold0;\n-\tu32\tmp_threshold1;\n-\tu32\tmp_threshold2;\n-\tu32\tphy_ctrl0;\n-};\n-\n-struct socfpga_sdram_rw_mgr_config {\n-\tu8\tactivate_0_and_1;\n-\tu8\tactivate_0_and_1_wait1;\n-\tu8\tactivate_0_and_1_wait2;\n-\tu8\tactivate_1;\n-\tu8\tclear_dqs_enable;\n-\tu8\tguaranteed_read;\n-\tu8\tguaranteed_read_cont;\n-\tu8\tguaranteed_write;\n-\tu8\tguaranteed_write_wait0;\n-\tu8\tguaranteed_write_wait1;\n-\tu8\tguaranteed_write_wait2;\n-\tu8\tguaranteed_write_wait3;\n-\tu8\tidle;\n-\tu8\tidle_loop1;\n-\tu8\tidle_loop2;\n-\tu8\tinit_reset_0_cke_0;\n-\tu8\tinit_reset_1_cke_0;\n-\tu8\tlfsr_wr_rd_bank_0;\n-\tu8\tlfsr_wr_rd_bank_0_data;\n-\tu8\tlfsr_wr_rd_bank_0_dqs;\n-\tu8\tlfsr_wr_rd_bank_0_nop;\n-\tu8\tlfsr_wr_rd_bank_0_wait;\n-\tu8\tlfsr_wr_rd_bank_0_wl_1;\n-\tu8\tlfsr_wr_rd_dm_bank_0;\n-\tu8\tlfsr_wr_rd_dm_bank_0_data;\n-\tu8\tlfsr_wr_rd_dm_bank_0_dqs;\n-\tu8\tlfsr_wr_rd_dm_bank_0_nop;\n-\tu8\tlfsr_wr_rd_dm_bank_0_wait;\n-\tu8\tlfsr_wr_rd_dm_bank_0_wl_1;\n-\tu8\tmrs0_dll_reset;\n-\tu8\tmrs0_dll_reset_mirr;\n-\tu8\tmrs0_user;\n-\tu8\tmrs0_user_mirr;\n-\tu8\tmrs1;\n-\tu8\tmrs1_mirr;\n-\tu8\tmrs2;\n-\tu8\tmrs2_mirr;\n-\tu8\tmrs3;\n-\tu8\tmrs3_mirr;\n-\tu8\tprecharge_all;\n-\tu8\tread_b2b;\n-\tu8\tread_b2b_wait1;\n-\tu8\tread_b2b_wait2;\n-\tu8\trefresh_all;\n-\tu8\trreturn;\n-\tu8\tsgle_read;\n-\tu8\tzqcl;\n-\n-\tu8\ttrue_mem_data_mask_width;\n-\tu8\tmem_address_mirroring;\n-\tu8\tmem_data_mask_width;\n-\tu8\tmem_data_width;\n-\tu8\tmem_dq_per_read_dqs;\n-\tu8\tmem_dq_per_write_dqs;\n-\tu8\tmem_if_read_dqs_width;\n-\tu8\tmem_if_write_dqs_width;\n-\tu8\tmem_number_of_cs_per_dimm;\n-\tu8\tmem_number_of_ranks;\n-\tu8\tmem_virtual_groups_per_read_dqs;\n-\tu8\tmem_virtual_groups_per_write_dqs;\n-};\n-\n-struct socfpga_sdram_io_config {\n-\tu16\tdelay_per_opa_tap;\n-\tu8\tdelay_per_dchain_tap;\n-\tu8\tdelay_per_dqs_en_dchain_tap;\n-\tu8\tdll_chain_length;\n-\tu8\tdqdqs_out_phase_max;\n-\tu8\tdqs_en_delay_max;\n-\tu8\tdqs_en_delay_offset;\n-\tu8\tdqs_en_phase_max;\n-\tu8\tdqs_in_delay_max;\n-\tu8\tdqs_in_reserve;\n-\tu8\tdqs_out_reserve;\n-\tu8\tio_in_delay_max;\n-\tu8\tio_out1_delay_max;\n-\tu8\tio_out2_delay_max;\n-\tu8\tshift_dqs_en_when_shift_dqs;\n-};\n-\n-struct socfpga_sdram_misc_config {\n-\tu32\treg_file_init_seq_signature;\n-\tu8\tafi_rate_ratio;\n-\tu8\tcalib_lfifo_offset;\n-\tu8\tcalib_vfifo_offset;\n-\tu8\tenable_super_quick_calibration;\n-\tu8\tmax_latency_count_width;\n-\tu8\tread_valid_fifo_size;\n-\tu8\ttinit_cntr0_val;\n-\tu8\ttinit_cntr1_val;\n-\tu8\ttinit_cntr2_val;\n-\tu8\ttreset_cntr0_val;\n-\tu8\ttreset_cntr1_val;\n-\tu8\ttreset_cntr2_val;\n-};\n-\n-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23\n-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000\n-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22\n-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000\n-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16\n-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000\n-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15\n-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000\n-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11\n-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800\n-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10\n-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400\n-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8\n-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300\n-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3\n-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8\n-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0\n-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007\n-/* Register template: sdr::ctrlgrp::dramtiming1 */\n-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24\n-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000\n-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18\n-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000\n-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14\n-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000\n-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9\n-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00\n-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4\n-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0\n-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0\n-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f\n-/* Register template: sdr::ctrlgrp::dramtiming2 */\n-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25\n-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000\n-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21\n-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000\n-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17\n-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000\n-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13\n-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000\n-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0\n-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff\n-/* Register template: sdr::ctrlgrp::dramtiming3 */\n-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19\n-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000\n-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15\n-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000\n-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9\n-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00\n-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4\n-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0\n-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0\n-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f\n-/* Register template: sdr::ctrlgrp::dramtiming4 */\n-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20\n-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000\n-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10\n-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00\n-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0\n-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff\n-/* Register template: sdr::ctrlgrp::lowpwrtiming */\n-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16\n-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000\n-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0\n-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff\n-/* Register template: sdr::ctrlgrp::dramaddrw */\n-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13\n-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000\n-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10\n-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00\n-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5\n-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0\n-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0\n-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f\n-/* Register template: sdr::ctrlgrp::dramifwidth */\n-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0\n-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff\n-/* Register template: sdr::ctrlgrp::dramdevwidth */\n-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0\n-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f\n-/* Register template: sdr::ctrlgrp::dramintr */\n-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0\n-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001\n-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4\n-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030\n-/* Register template: sdr::ctrlgrp::staticcfg */\n-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3\n-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008\n-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2\n-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004\n-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0\n-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003\n-/* Register template: sdr::ctrlgrp::ctrlwidth */\n-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0\n-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003\n-/* Register template: sdr::ctrlgrp::cportwidth */\n-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0\n-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff\n-/* Register template: sdr::ctrlgrp::cportwmap */\n-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0\n-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff\n-/* Register template: sdr::ctrlgrp::cportrmap */\n-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0\n-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff\n-/* Register template: sdr::ctrlgrp::rfifocmap */\n-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0\n-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff\n-/* Register template: sdr::ctrlgrp::wfifocmap */\n-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0\n-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff\n-/* Register template: sdr::ctrlgrp::cportrdwr */\n-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0\n-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff\n-/* Register template: sdr::ctrlgrp::portcfg */\n-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10\n-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00\n-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0\n-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff\n-/* Register template: sdr::ctrlgrp::fifocfg */\n-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10\n-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400\n-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0\n-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff\n-/* Register template: sdr::ctrlgrp::mppriority */\n-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0\n-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff\n-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff\n-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff\n-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff\n-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0\n-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff\n-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */\n-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0\n-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff\n-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */\n-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28\n-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000\n-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0\n-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff\n-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */\n-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0\n-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff\n-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */\n-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0\n-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff\n-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \\\n-0xffffffff\n-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \\\n-0xffffffff\n-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0\n-#define \\\n-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \\\n-0x0000ffff\n-/* Register template: sdr::ctrlgrp::remappriority */\n-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0\n-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff\n-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \\\n- (((x) << 12) & 0xfffff000)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \\\n- (((x) << 10) & 0x00000c00)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \\\n- (((x) << 6) & 0x000000c0)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \\\n- (((x) << 8) & 0x00000100)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \\\n- (((x) << 9) & 0x00000200)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \\\n- (((x) << 4) & 0x00000030)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \\\n- (((x) << 2) & 0x0000000c)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \\\n- (((x) << 0) & 0x00000003)\n-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \\\n- (((x) << 12) & 0xfffff000)\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \\\n- (((x) << 0) & 0x00000fff)\n-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */\n-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \\\n- (((x) << 0) & 0x00000fff)\n-/* Register template: sdr::ctrlgrp::dramodt */\n-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4\n-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0\n-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0\n-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f\n-/* Field instance: sdr::ctrlgrp::dramsts */\n-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008\n-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004\n-/* Register template: sdr::ctrlgrp::extratime1 */\n-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20\n-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24\n-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28\n-\n-/* SDRAM width macro for configuration with ECC */\n-#define SDRAM_WIDTH_32BIT_WITH_ECC\t40\n-#define SDRAM_WIDTH_16BIT_WITH_ECC\t24\n+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n+#include <asm/arch/sdram_gen5.h>\n+#endif\n \n #endif\n #endif /* _SDRAM_H_ */\ndiff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h\nsimilarity index 99%\ncopy from arch/arm/mach-socfpga/include/mach/sdram.h\ncopy to arch/arm/mach-socfpga/include/mach/sdram_gen5.h\nindex b11228f..b16d776 100644\n--- a/arch/arm/mach-socfpga/include/mach/sdram.h\n+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h\n@@ -3,8 +3,8 @@\n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n-#ifndef\t_SDRAM_H_\n-#define\t_SDRAM_H_\n+#ifndef\t_SOCFPGA_SDRAM_GEN5_H_\n+#define\t_SOCFPGA_SDRAM_GEN5_H_\n \n #ifndef __ASSEMBLY__\n \n@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \\\n #define SDRAM_WIDTH_16BIT_WITH_ECC\t24\n \n #endif\n-#endif /* _SDRAM_H_ */\n+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */\ndiff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile\nindex bdd2872..ac4ab85 100644\n--- a/drivers/ddr/altera/Makefile\n+++ b/drivers/ddr/altera/Makefile\n@@ -9,5 +9,5 @@\n #\n \n ifdef CONFIG_ALTERA_SDRAM\n-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o\n+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o\n endif\ndiff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram_gen5.c\nsimilarity index 100%\nrename from drivers/ddr/altera/sdram.c\nrename to drivers/ddr/altera/sdram_gen5.c\n", "prefixes": [ "U-Boot", "06/19" ] }