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GET /api/patches/807053/?format=api
{ "id": 807053, "url": "http://patchwork.ozlabs.org/api/patches/807053/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-10-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-10-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:51", "name": "[U-Boot,09/19] arm: socfpga: Add DDR driver for Arria 10", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "91f2f8efbbe8ef38eeb08ff8291b8aefb202e9d0", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-10-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807053/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807053/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRM70yWDz9t2v\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 21:32:33 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 14E34C21C39; Tue, 29 Aug 2017 10:53:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3F3EAC21F9F;\n\tTue, 29 Aug 2017 10:53:09 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid CAAD0C22026; Tue, 29 Aug 2017 10:46:32 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 640D9C21FF3\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:28 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:27 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:25 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176648\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:51 +0800", "Message-Id": "<1504003561-6290-10-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 09/19] arm: socfpga: Add DDR driver for Arria 10", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nAdd DDR driver suppport for Arria 10.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n arch/arm/mach-socfpga/include/mach/sdram.h | 2 +\n arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 +++-\n drivers/ddr/altera/sdram_arria10.c | 735 ++++++++++++++++++++\n 3 files changed, 839 insertions(+), 1 deletions(-)\n create mode 100644 drivers/ddr/altera/sdram_arria10.c", "diff": "diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h\nindex f471913..0ba3fcb 100644\n--- a/arch/arm/mach-socfpga/include/mach/sdram.h\n+++ b/arch/arm/mach-socfpga/include/mach/sdram.h\n@@ -10,6 +10,8 @@\n \n #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n #include <asm/arch/sdram_gen5.h>\n+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n+#include <asm/arch/sdram_arria10.h>\n #endif\n \n #endif\ndiff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\nindex 1d7b7c1..7af9431 100644\n--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h\n@@ -1,5 +1,5 @@\n /*\n- * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>\n+ * Copyright (C) 2017 Intel Corporation <www.intel.com>\n *\n * SPDX-License-Identifier:\tGPL-2.0\n */\n@@ -8,6 +8,7 @@\n #define _SOCFPGA_SDRAM_ARRIA10_H_\n \n #ifndef __ASSEMBLY__\n+int ddr_calibration_sequence(void);\n \n struct socfpga_ecc_hmc {\n \tu32 ip_rev_id;\n@@ -204,6 +205,106 @@ struct socfpga_io48_mmr {\n \tu32 niosreserve1;\n \tu32 niosreserve2;\n };\n+\n+union dramaddrw_reg {\n+\tstruct {\n+\t\tu32 cfg_col_addr_width:5;\n+\t\tu32 cfg_row_addr_width:5;\n+\t\tu32 cfg_bank_addr_width:4;\n+\t\tu32 cfg_bank_group_addr_width:2;\n+\t\tu32 cfg_cs_addr_width:3;\n+\t\tu32 reserved:13;\n+\t};\n+\tu32 word;\n+};\n+\n+union ctrlcfg0_reg {\n+\tstruct {\n+\t\tu32 cfg_mem_type:4;\n+\t\tu32 cfg_dimm_type:3;\n+\t\tu32 cfg_ac_pos:2;\n+\t\tu32 cfg_ctrl_burst_len:5;\n+\t\tu32 reserved:18; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union ctrlcfg1_reg {\n+\tstruct {\n+\t\tu32 cfg_dbc3_burst_len:5;\n+\t\tu32 cfg_addr_order:2;\n+\t\tu32 cfg_ctrl_enable_ecc:1;\n+\t\tu32 reserved:24; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming0_reg {\n+\tstruct {\n+\t\tu32 cfg_act_to_rdwr:6;\n+\t\tu32 cfg_act_to_pch:6;\n+\t\tu32 cfg_act_to_act:6;\n+\t\tu32 cfg_act_to_act_db:6;\n+\t\tu32 reserved:8; /* Other fields unused */\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming1_reg {\n+\tstruct {\n+\t\tu32 cfg_rd_to_rd:6;\n+\t\tu32 cfg_rd_to_rd_dc:6;\n+\t\tu32 cfg_rd_to_rd_db:6;\n+\t\tu32 cfg_rd_to_wr:6;\n+\t\tu32 cfg_rd_to_wr_dc:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming2_reg {\n+\tstruct {\n+\t\tu32 cfg_rd_to_wr_db:6;\n+\t\tu32 cfg_rd_to_pch:6;\n+\t\tu32 cfg_rd_ap_to_valid:6;\n+\t\tu32 cfg_wr_to_wr:6;\n+\t\tu32 cfg_wr_to_wr_dc:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming3_reg {\n+\tstruct {\n+\t\tu32 cfg_wr_to_wr_db:6;\n+\t\tu32 cfg_wr_to_rd:6;\n+\t\tu32 cfg_wr_to_rd_dc:6;\n+\t\tu32 cfg_wr_to_rd_db:6;\n+\t\tu32 cfg_wr_to_pch:6;\n+\t\tu32 reserved:2;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming4_reg {\n+\tstruct {\n+\t\tu32 cfg_wr_ap_to_valid:6;\n+\t\tu32 cfg_pch_to_valid:6;\n+\t\tu32 cfg_pch_all_to_valid:6;\n+\t\tu32 cfg_arf_to_valid:8;\n+\t\tu32 cfg_pdn_to_valid:6;\n+\t};\n+\tu32 word;\n+};\n+\n+union caltiming9_reg {\n+\tstruct {\n+\t\tu32 cfg_4_act_to_act:8;\n+\t\tu32 reserved:24;\n+\t};\n+\tu32 word;\n+};\n+\n #endif /*__ASSEMBLY__*/\n \n #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK\t\t0x1F000000\ndiff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c\nnew file mode 100644\nindex 0000000..f22a726\n--- /dev/null\n+++ b/drivers/ddr/altera/sdram_arria10.c\n@@ -0,0 +1,735 @@\n+/*\n+ * Copyright (C) 2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0\n+ */\n+\n+#include <common.h>\n+#include <fdtdec.h>\n+#include <malloc.h>\n+#include <mmc.h>\n+#include <nand.h>\n+#include <watchdog.h>\n+#include <ns16550.h>\n+#include <asm/io.h>\n+#include <asm/arch/fpga_manager.h>\n+#include <asm/arch/misc.h>\n+#include <asm/arch/reset_manager.h>\n+#include <asm/arch/sdram.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static void sdram_mmr_init(void);\n+static unsigned long long sdram_size_calc(void);\n+\n+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */\n+#define ARRIA10_SDR_ACTIVATE_FAWBANK\t(0x1)\n+\n+#define ARRIA_DDR_CONFIG(A, B, C, R)\t((A<<24)|(B<<16)|(C<<8)|R)\n+#define DDR_CONFIG_ELEMENTS\t(sizeof(ddr_config)/sizeof(u32))\n+#define DDR_REG_SEQ2CORE 0xFFD0507C\n+#define DDR_REG_CORE2SEQ 0xFFD05078\n+#define DDR_READ_LATENCY_DELAY\t40\n+#define DDR_SIZE_2GB_HEX\t0x80000000\n+#define DDR_MAX_TRIES\t\t0x00100000\n+\n+#define IO48_MMR_DRAMSTS\t0xFFCFA0EC\n+#define IO48_MMR_NIOS2_RESERVE0\t0xFFCFA110\n+#define IO48_MMR_NIOS2_RESERVE1\t0xFFCFA114\n+#define IO48_MMR_NIOS2_RESERVE2\t0xFFCFA118\n+\n+#define SEQ2CORE_MASK\t\t0xF\n+#define CORE2SEQ_INT_REQ\t0xF\n+#define SEQ2CORE_INT_RESP_BIT\t3\n+\n+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =\n+\t\t(void *)SOCFPGA_SDR_ADDRESS;\n+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =\n+\t\t(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;\n+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram\n+\t\t*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =\n+\t\t(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;\n+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =\n+\t\t(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;\n+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =\n+\t\t(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;\n+\n+/* The followring are the supported configurations */\n+static u32 ddr_config[] = {\n+\t/* Chip - Row - Bank - Column Style */\n+\t/* All Types */\n+\tARRIA_DDR_CONFIG(0, 3, 10, 12),\n+\tARRIA_DDR_CONFIG(0, 3, 10, 13),\n+\tARRIA_DDR_CONFIG(0, 3, 10, 14),\n+\tARRIA_DDR_CONFIG(0, 3, 10, 15),\n+\tARRIA_DDR_CONFIG(0, 3, 10, 16),\n+\tARRIA_DDR_CONFIG(0, 3, 10, 17),\n+\t/* LPDDR x16 */\n+\tARRIA_DDR_CONFIG(0, 3, 11, 14),\n+\tARRIA_DDR_CONFIG(0, 3, 11, 15),\n+\tARRIA_DDR_CONFIG(0, 3, 11, 16),\n+\tARRIA_DDR_CONFIG(0, 3, 12, 15),\n+\t/* DDR4 Only */\n+\tARRIA_DDR_CONFIG(0, 4, 10, 14),\n+\tARRIA_DDR_CONFIG(0, 4, 10, 15),\n+\tARRIA_DDR_CONFIG(0, 4, 10, 16),\n+\tARRIA_DDR_CONFIG(0, 4, 10, 17),\t/* 14 */\n+\t/* Chip - Bank - Row - Column Style */\n+\tARRIA_DDR_CONFIG(1, 3, 10, 12),\n+\tARRIA_DDR_CONFIG(1, 3, 10, 13),\n+\tARRIA_DDR_CONFIG(1, 3, 10, 14),\n+\tARRIA_DDR_CONFIG(1, 3, 10, 15),\n+\tARRIA_DDR_CONFIG(1, 3, 10, 16),\n+\tARRIA_DDR_CONFIG(1, 3, 10, 17),\n+\tARRIA_DDR_CONFIG(1, 3, 11, 14),\n+\tARRIA_DDR_CONFIG(1, 3, 11, 15),\n+\tARRIA_DDR_CONFIG(1, 3, 11, 16),\n+\tARRIA_DDR_CONFIG(1, 3, 12, 15),\n+\t/* DDR4 Only */\n+\tARRIA_DDR_CONFIG(1, 4, 10, 14),\n+\tARRIA_DDR_CONFIG(1, 4, 10, 15),\n+\tARRIA_DDR_CONFIG(1, 4, 10, 16),\n+\tARRIA_DDR_CONFIG(1, 4, 10, 17),\n+};\n+\n+static int match_ddr_conf(u32 ddr_conf)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {\n+\t\tif (ddr_conf == ddr_config[i])\n+\t\t\treturn i;\n+\t}\n+\treturn 0;\n+}\n+\n+/* Check whether SDRAM is successfully Calibrated */\n+static int is_sdram_cal_success(void)\n+{\n+\treturn readl(&socfpga_ecc_hmc_base->ddrcalstat);\n+}\n+\n+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)\n+{\n+\tu32 reg = readl(ereg);\n+\n+\treturn (reg & (1 << bit)) ? 1 : 0;\n+}\n+\n+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,\n+\t\t\t u32 expected, u32 timeout_usec)\n+{\n+\tu32 tmr;\n+\n+\tfor (tmr = 0; tmr < timeout_usec; tmr += 100) {\n+\t\tudelay(100);\n+\t\tWATCHDOG_RESET();\n+\t\tif (ddr_get_bit(ereg, bit) == expected)\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+static void ddr_delay(u32 delay)\n+{\n+\tint tmr;\n+\n+\tfor (tmr = 0; tmr < delay; tmr++) {\n+\t\tudelay(1000);\n+\t\tWATCHDOG_RESET();\n+\t}\n+}\n+\n+static int emif_clear(void)\n+{\n+\tu32 s2c;\n+\tu32 i = DDR_MAX_TRIES;\n+\n+\twritel(0, DDR_REG_CORE2SEQ);\n+\tdo {\n+\t\tddr_delay(50);\n+\t\ts2c = readl(DDR_REG_SEQ2CORE);\n+\t} while ((s2c & SEQ2CORE_MASK) && (--i > 0));\n+\n+\treturn !i;\n+}\n+\n+static int emif_reset(void)\n+{\n+\tu32 c2s, s2c;\n+\n+\tc2s = readl(DDR_REG_CORE2SEQ);\n+\ts2c = readl(DDR_REG_SEQ2CORE);\n+\n+\tdebug(\"c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\\n\",\n+\t\tc2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),\n+\t\treadl(IO48_MMR_NIOS2_RESERVE1),\n+\t\treadl(IO48_MMR_NIOS2_RESERVE2),\n+\t\treadl(IO48_MMR_DRAMSTS));\n+\n+\tif ((s2c & SEQ2CORE_MASK) && emif_clear()) {\n+\t\tprintf(\"failed emif_clear()\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\twritel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);\n+\n+\tif (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {\n+\t\tprintf(\"emif_reset failed to see interrupt acknowledge\\n\");\n+\t\treturn -2;\n+\t} else {\n+\t\tprintf(\"emif_reset interrupt acknowledged\\n\");\n+\t}\n+\n+\tif (emif_clear()) {\n+\t\tprintf(\"emif_clear() failed\\n\");\n+\t\treturn -3;\n+\t}\n+\tdebug(\"emif_reset interrupt cleared\\n\");\n+\n+\tdebug(\"nr0=%08x nr1=%08x nr2=%08x\\n\",\n+\t\treadl(IO48_MMR_NIOS2_RESERVE0),\n+\t\treadl(IO48_MMR_NIOS2_RESERVE1),\n+\t\treadl(IO48_MMR_NIOS2_RESERVE2));\n+\n+\treturn 0;\n+}\n+\n+static int ddr_setup(void)\n+{\n+\tint i, j, ddr_setup_complete = 0;\n+\n+\t/* Try 3 times to do a calibration */\n+\tfor (i = 0; (i < 3) && !ddr_setup_complete; i++) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\t/* A delay to wait for calibration bit to set */\n+\t\tfor (j = 0; (j < 10) && !ddr_setup_complete; j++) {\n+\t\t\tddr_delay(500);\n+\t\t\tddr_setup_complete = is_sdram_cal_success();\n+\t\t}\n+\n+\t\tif (!ddr_setup_complete)\n+\t\t\temif_reset();\n+\t}\n+\n+\tif (!ddr_setup_complete) {\n+\t\tputs(\"Error: Could Not Calibrate SDRAM\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Function to startup the SDRAM*/\n+static int sdram_startup(void)\n+{\n+\t/* Release NOC ddr scheduler from reset */\n+\tsocfpga_reset_deassert_noc_ddr_scheduler();\n+\n+\t/* Bringup the DDR (calibration and configuration) */\n+\treturn ddr_setup();\n+}\n+\n+static unsigned long long sdram_size_calc(void)\n+{\n+\tunion dramaddrw_reg dramaddrw =\n+\t\t(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);\n+\n+\tunsigned long long size = (1 << (dramaddrw.cfg_cs_addr_width +\n+\t\t\t\tdramaddrw.cfg_bank_group_addr_width +\n+\t\t\t\tdramaddrw.cfg_bank_addr_width +\n+\t\t\t\tdramaddrw.cfg_row_addr_width +\n+\t\t\t\tdramaddrw.cfg_col_addr_width));\n+\n+\tsize *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &\n+\t\t ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));\n+\n+\treturn size;\n+}\n+\n+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/\n+static void sdram_mmr_init(void)\n+{\n+\tu32 update_value, io48_value;\n+\tunion ctrlcfg0_reg ctrlcfg0 =\n+\t\t(union ctrlcfg0_reg)readl(&socfpga_io48_mmr_base->ctrlcfg0);\n+\tunion ctrlcfg1_reg ctrlcfg1 =\n+\t\t(union ctrlcfg1_reg)readl(&socfpga_io48_mmr_base->ctrlcfg1);\n+\tunion dramaddrw_reg dramaddrw =\n+\t\t(union dramaddrw_reg)readl(&socfpga_io48_mmr_base->dramaddrw);\n+\tunion caltiming0_reg caltim0 =\n+\t\t(union caltiming0_reg)readl(&socfpga_io48_mmr_base->caltiming0);\n+\tunion caltiming1_reg caltim1 =\n+\t\t(union caltiming1_reg)readl(&socfpga_io48_mmr_base->caltiming1);\n+\tunion caltiming2_reg caltim2 =\n+\t\t(union caltiming2_reg)readl(&socfpga_io48_mmr_base->caltiming2);\n+\tunion caltiming3_reg caltim3 =\n+\t\t(union caltiming3_reg)readl(&socfpga_io48_mmr_base->caltiming3);\n+\tunion caltiming4_reg caltim4 =\n+\t\t(union caltiming4_reg)readl(&socfpga_io48_mmr_base->caltiming4);\n+\tunion caltiming9_reg caltim9 =\n+\t\t(union caltiming9_reg)readl(&socfpga_io48_mmr_base->caltiming9);\n+\tu32 ddrioctl;\n+\n+\t/*\n+\t * Configure the DDR IO size [0xFFCFB008]\n+\t * niosreserve0: Used to indicate DDR width &\n+\t *\tbit[7:0] = Number of data bits (0x20 for 32bit)\n+\t *\tbit[8] = 1 if user-mode OCT is present\n+\t *\tbit[9] = 1 if warm reset compiled into EMIF Cal Code\n+\t *\tbit[10] = 1 if warm reset is on during generation in EMIF Cal\n+\t * niosreserve1: IP ADCDS version encoded as 16 bit value\n+\t *\tbit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,\n+\t *\t\t\t 3=EAP, 4-6 are reserved)\n+\t *\tbit[5:3] = Service Pack # (e.g. 1)\n+\t *\tbit[9:6] = Minor Release #\n+\t *\tbit[14:10] = Major Release #\n+\t */\n+\tif ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {\n+\t\tupdate_value = readl(&socfpga_io48_mmr_base->niosreserve0);\n+\t\twritel(((update_value & 0xFF) >> 5),\n+\t\t &socfpga_ecc_hmc_base->ddrioctrl);\n+\t}\n+\n+\tddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);\n+\n+\t/* Set the DDR Configuration [0xFFD12400] */\n+\tio48_value = ARRIA_DDR_CONFIG(ctrlcfg1.cfg_addr_order,\n+\t\t\t\t (dramaddrw.cfg_bank_addr_width +\n+\t\t\t\t dramaddrw.cfg_bank_group_addr_width),\n+\t\t\t\t dramaddrw.cfg_col_addr_width,\n+\t\t\t\t dramaddrw.cfg_row_addr_width);\n+\n+\tupdate_value = match_ddr_conf(io48_value);\n+\tif (update_value)\n+\t\twritel(update_value,\n+\t\t&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);\n+\n+\t/*\n+\t * Configure DDR timing [0xFFD1240C]\n+\t * RDTOMISS = tRTP + tRP + tRCD - BL/2\n+\t * WRTOMISS = WL + tWR + tRP + tRCD and\n+\t * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...\n+\t * First part of equation is in memory clock units so divide by 2\n+\t * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.\n+\t * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD\n+\t */\n+\tupdate_value = (caltim2.cfg_rd_to_pch + caltim4.cfg_pch_to_valid +\n+\t\t\tcaltim0.cfg_act_to_rdwr -\n+\t\t\t(ctrlcfg0.cfg_ctrl_burst_len >> 2));\n+\tio48_value = ((((socfpga_io48_mmr_base->dramtiming0 &\n+\t\t ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +\n+\t\t (ctrlcfg0.cfg_ctrl_burst_len >> 1)) >> 1) -\n+\t\t /* Up to here was in memory cycles so divide by 2 */\n+\t\t caltim1.cfg_rd_to_wr + caltim0.cfg_act_to_rdwr +\n+\t\t caltim4.cfg_pch_to_valid);\n+\n+\twritel(((caltim0.cfg_act_to_act <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |\n+\t\t(update_value <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |\n+\t\t(io48_value <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |\n+\t\t((ctrlcfg0.cfg_ctrl_burst_len >> 2) <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |\n+\t\t(caltim1.cfg_rd_to_wr <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |\n+\t\t(caltim3.cfg_wr_to_rd <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |\n+\t\t(((ddrioctl == 1) ? 1 : 0) <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),\n+\t\t&socfpga_noc_ddr_scheduler_base->\n+\t\t\tddr_t_main_scheduler_ddrtiming);\n+\n+\t/* Configure DDR mode [0xFFD12410] [precharge = 0] */\n+\twritel(((ddrioctl ? 0 : 1) <<\n+\t\tALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),\n+\t\t&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);\n+\n+\t/* Configure the read latency [0xFFD12414] */\n+\twritel(((socfpga_io48_mmr_base->dramtiming0 &\n+\t\tALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +\n+\t\tDDR_READ_LATENCY_DELAY,\n+\t\t&socfpga_noc_ddr_scheduler_base->\n+\t\t\tddr_t_main_scheduler_readlatency);\n+\n+\t/*\n+\t * Configuring timing values concerning activate commands\n+\t * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]\n+\t */\n+\twritel(((caltim0.cfg_act_to_act_db <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |\n+\t\t(caltim9.cfg_4_act_to_act <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |\n+\t\t(ARRIA10_SDR_ACTIVATE_FAWBANK <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),\n+\t\t&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);\n+\n+\t/*\n+\t * Configuring timing values concerning device to device data bus\n+\t * ownership change [0xFFD1243C]\n+\t */\n+\twritel(((caltim1.cfg_rd_to_rd_dc <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |\n+\t\t(caltim1.cfg_rd_to_wr_dc <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |\n+\t\t(caltim3.cfg_wr_to_rd_dc <<\n+\t\t\tALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),\n+\t\t&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);\n+\n+\t/* Enable or disable the SDRAM ECC */\n+\tif (ctrlcfg1.cfg_ctrl_enable_ecc) {\n+\t\tsetbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));\n+\t\tsetbits_le32(&socfpga_ecc_hmc_base->eccctrl2,\n+\t\t\t (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));\n+\t} else {\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl,\n+\t\t\t (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));\n+\t\tclrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,\n+\t\t\t (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |\n+\t\t\t ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));\n+\t}\n+}\n+\n+struct firewall_entry {\n+\tconst char *prop_name;\n+\tconst u32 cfg_addr;\n+\tconst u32 en_addr;\n+\tconst u32 en_bit;\n+};\n+#define FW_MPU_FPGA_ADDRESS \\\n+\t((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\\\n+\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)\n+const struct firewall_entry firewall_table[] = {\n+\t{\n+\t\t\"altr,mpu0\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t mpuregion0addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,mpu1\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t mpuregion1addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,mpu2\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t mpuregion2addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,mpu3\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t mpuregion3addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-0\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion0addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-1\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion1addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-2\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion2addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-3\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion3addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-4\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion4addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-5\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion5addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-6\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion6addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,l3-7\",\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, hpsregion7addr),\n+\t\tSOCFPGA_SDR_FIREWALL_L3_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_l3, enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram0-0\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram0region0addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram0-1\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram0region1addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram0-2\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram0region2addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram0-3\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram0region3addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram1-0\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram1region0addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram1-1\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram1region1addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram1-2\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram1region2addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram1-3\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram1region3addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK\n+\t},\t{\n+\t\t\"altr,fpga2sdram2-0\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram2region0addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram2-1\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram2region1addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram2-2\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram2region2addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK\n+\t},\n+\t{\n+\t\t\"altr,fpga2sdram2-3\",\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t fpga2sdram2region3addr),\n+\t\tSOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +\n+\t\t\toffsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram,\n+\t\t\t\t enable),\n+\t\tALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK\n+\t},\n+\n+};\n+\n+static int of_sdram_firewall_setup(const void *blob)\n+{\n+\tint child, i, node;\n+\tu32 start_end[2];\n+\n+\tnode = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);\n+\tif (node < 0)\n+\t\treturn 2;\n+\n+\tchild = fdt_first_subnode(blob, node);\n+\tif (child < 0)\n+\t\treturn 1;\n+\n+\t/* set to default state */\n+\twritel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);\n+\twritel(0, &socfpga_noc_fw_ddr_l3_base->enable);\n+\n+\n+\tfor (i = 0; i < ARRAY_SIZE(firewall_table); i++) {\n+\t\tif (!fdtdec_get_int_array(blob, child,\n+\t\t\t\t\t firewall_table[i].prop_name,\n+\t\t\t\t\t start_end, 2)) {\n+\t\t\twritel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |\n+\t\t\t\t(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),\n+\t\t\t\t firewall_table[i].cfg_addr);\n+\t\t\tsetbits_le32(firewall_table[i].en_addr,\n+\t\t\t\t firewall_table[i].en_bit);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int ddr_calibration_sequence(void)\n+{\n+\tWATCHDOG_RESET();\n+\n+\t/* Check to see if SDRAM cal was success */\n+\tif (sdram_startup()) {\n+\t\tputs(\"DDRCAL: Failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tputs(\"DDRCAL: Success\\n\");\n+\n+\tWATCHDOG_RESET();\n+\n+\t/* initialize the MMR register */\n+\tsdram_mmr_init();\n+\n+\t/* assigning the SDRAM size */\n+\tunsigned long long size = sdram_size_calc();\n+\n+\t/* If a weird value, use default Config size */\n+\t/* Up to 2GB is supported, 2GB would be used if more than that */\n+\tif (size <= 0)\n+\t\tgd->ram_size = PHYS_SDRAM_1_SIZE;\n+\telse if (DDR_SIZE_2GB_HEX <= size)\n+\t\tgd->ram_size = DDR_SIZE_2GB_HEX;\n+\telse\n+\t\tgd->ram_size = (u32)size;\n+\n+\t/* setup the dram info within bd */\n+\tdram_init_banksize();\n+\n+\tif (of_sdram_firewall_setup(gd->fdt_blob))\n+\t\tputs(\"FW: Error Configuring Firewall\\n\");\n+\n+\treturn 0;\n+}\n+\n+void dram_bank_mmu_setup(int bank)\n+{\n+\tbd_t *bd = gd->bd;\n+\tint\ti;\n+\n+\tdebug(\"%s: bank: %d\\n\", __func__, bank);\n+\tfor (i = bd->bi_dram[bank].start >> 20;\n+\t i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;\n+\t i++) {\n+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)\n+\t\tset_section_dcache(i, DCACHE_WRITETHROUGH);\n+#else\n+\t\tset_section_dcache(i, DCACHE_WRITEBACK);\n+#endif\n+\t}\n+\n+\t/* same as above but just that we would want cacheable for ocram too */\n+\ti = CONFIG_SYS_INIT_RAM_ADDR >> 20;\n+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)\n+\tset_section_dcache(i, DCACHE_WRITETHROUGH);\n+#else\n+\tset_section_dcache(i, DCACHE_WRITEBACK);\n+#endif\n+}\n", "prefixes": [ "U-Boot", "09/19" ] }