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GET /api/patches/807049/?format=api
{ "id": 807049, "url": "http://patchwork.ozlabs.org/api/patches/807049/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-11-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-11-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:52", "name": "[U-Boot,10/19] configs: Add DDR Kconfig support for Arria 10", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "db63aa14e589a8330ea68bcf0d2214edfebde728", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-11-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807049/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807049/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhRJF69j4z9t38\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 21:30:04 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8D51FC21FCB; Tue, 29 Aug 2017 10:54:20 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 7E470C21F01;\n\tTue, 29 Aug 2017 10:53:59 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9E72CC21FF3; Tue, 29 Aug 2017 10:46:34 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id E24DDC22009\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:30 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:30 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:28 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176657\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:52 +0800", "Message-Id": "<1504003561-6290-11-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 10/19] configs: Add DDR Kconfig support for Arria 10", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nThis patch enables DDR Kconfig support for Arria 10.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n arch/arm/mach-socfpga/Kconfig | 1 +\n drivers/ddr/altera/Kconfig | 2 +-\n 2 files changed, 2 insertions(+), 1 deletions(-)", "diff": "diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex 45e5379..3e7a68a 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5\n config TARGET_SOCFPGA_ARRIA10\n \tbool\n \tselect SPL_BOARD_INIT if SPL\n+\tselect ALTERA_SDRAM\n \n config TARGET_SOCFPGA_CYCLONE5\n \tbool\ndiff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig\nindex 021ec1d..2b28a97 100644\n--- a/drivers/ddr/altera/Kconfig\n+++ b/drivers/ddr/altera/Kconfig\n@@ -1,5 +1,5 @@\n config ALTERA_SDRAM\n \tbool \"SoCFPGA DDR SDRAM driver\"\n-\tdepends on TARGET_SOCFPGA_GEN5\n+\tdepends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10\n \thelp\n \t Enable DDR SDRAM controller for the SoCFPGA devices.\n", "prefixes": [ "U-Boot", "10/19" ] }