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GET /api/patches/807040/?format=api
{ "id": 807040, "url": "http://patchwork.ozlabs.org/api/patches/807040/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-5-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504003561-6290-5-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-08-29T10:45:46", "name": "[U-Boot,04/19] arm: socfpga: Add FPGA loadfs command support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "a3f88237c7bcdb476aca2520026947d3a649edab", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1504003561-6290-5-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 345, "url": "http://patchwork.ozlabs.org/api/series/345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=345", "date": "2017-08-29T10:45:42", "name": "Add FPGA, SDRAM drivers and booting to U-boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/807040/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/807040/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhQfg1FYkz9s7c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 21:00:57 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid DCCFCC21D95; Tue, 29 Aug 2017 10:47:39 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 44C8BC21F72;\n\tTue, 29 Aug 2017 10:47:38 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E698AC21C35; Tue, 29 Aug 2017 10:46:22 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 5FAC0C21F9F\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:16 +0000 (UTC)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 03:46:16 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.65])\n\tby orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:13 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.41,444,1498546800\"; d=\"scan'208\";a=\"143176592\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 18:45:46 +0800", "Message-Id": "<1504003561-6290-5-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH 04/19] arm: socfpga: Add FPGA loadfs command support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nThis patch enables FPGA loadfs command support to U-boot console.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n cmd/fpga.c | 2 +-\n drivers/fpga/altera.c | 38 ++++++++++++++++++++++++++++++--------\n drivers/fpga/fpga.c | 8 ++++++++\n include/fpga.h | 2 ++\n 4 files changed, 41 insertions(+), 9 deletions(-)", "diff": "diff --git a/cmd/fpga.c b/cmd/fpga.c\nindex 016349f..28e6628 100644\n--- a/cmd/fpga.c\n+++ b/cmd/fpga.c\n@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,\n \t \"(Xilinx only)\\n\"\n #endif\n #if defined(CONFIG_CMD_FPGA_LOADFS)\n-\t \"Load device from filesystem (FAT by default) (Xilinx only)\\n\"\n+\t \"Load device from filesystem (FAT by default)\\n\"\n \t \" loadfs [dev] [address] [image size] [blocksize] <interface>\\n\"\n \t \" [<dev[:part]>] <filename>\\n\"\n #endif\ndiff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c\nindex 135a357..8b60bd5 100644\n--- a/drivers/fpga/altera.c\n+++ b/drivers/fpga/altera.c\n@@ -23,25 +23,30 @@ static const struct altera_fpga {\n \tenum altera_family\tfamily;\n \tconst char\t\t*name;\n \tint\t\t\t(*load)(Altera_desc *, const void *, size_t);\n+\tint \t\t\t(*loadfs)(Altera_desc *, const void *, size_t,\n+\t\t\t\t\t\t fpga_fs_info *);\n \tint\t\t\t(*dump)(Altera_desc *, const void *, size_t);\n \tint\t\t\t(*info)(Altera_desc *);\n } altera_fpga[] = {\n #if defined(CONFIG_FPGA_ACEX1K)\n-\t{ Altera_ACEX1K, \"ACEX1K\", ACEX1K_load, ACEX1K_dump, ACEX1K_info },\n-\t{ Altera_CYC2, \"ACEX1K\", ACEX1K_load, ACEX1K_dump, ACEX1K_info },\n+\t{ Altera_ACEX1K, \"ACEX1K\", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info },\n+\t{ Altera_CYC2, \"ACEX1K\", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info },\n #elif defined(CONFIG_FPGA_CYCLON2)\n-\t{ Altera_ACEX1K, \"CycloneII\", CYC2_load, CYC2_dump, CYC2_info },\n-\t{ Altera_CYC2, \"CycloneII\", CYC2_load, CYC2_dump, CYC2_info },\n+\t{ Altera_ACEX1K, \"CycloneII\", CYC2_load, NULL, CYC2_dump, CYC2_info },\n+\t{ Altera_CYC2, \"CycloneII\", CYC2_load, NULL, CYC2_dump, CYC2_info },\n #endif\n #if defined(CONFIG_FPGA_STRATIX_II)\n-\t{ Altera_StratixII, \"StratixII\", StratixII_load,\n+\t{ Altera_StratixII, \"StratixII\", StratixII_load, NULL,\n \t StratixII_dump, StratixII_info },\n #endif\n #if defined(CONFIG_FPGA_STRATIX_V)\n-\t{ Altera_StratixV, \"StratixV\", stratixv_load, NULL, NULL },\n+\t{ Altera_StratixV, \"StratixV\", stratixv_load, NULL, NULL, NULL },\n #endif\n-#if defined(CONFIG_FPGA_SOCFPGA)\n-\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, NULL, NULL },\n+#if defined(CONFIG_FPGA_SOCFPGA) && !defined(CONFIG_CMD_FPGA_LOADFS)\n+\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, NULL, NULL, NULL },\n+#endif\n+#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS)\n+\t{ Altera_SoCFPGA, \"SoC FPGA\", socfpga_load, socfpga_loadfs, NULL, NULL },\n #endif\n };\n \n@@ -174,3 +179,20 @@ int altera_info(Altera_desc *desc)\n \n \treturn FPGA_SUCCESS;\n }\n+\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n+int altera_loadfs(Altera_desc *desc, const void *buf, size_t bsize,\n+\t\t fpga_fs_info *fpga_fsinfo)\n+{\n+\tconst struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);\n+\n+\tif (!fpga)\n+\t\treturn FPGA_FAIL;\n+\n+\tdebug_cond(FPGA_DEBUG, \"%s: Launching the %s FS Loader...\\n\",\n+\t\t __func__, fpga->name);\n+\tif (fpga->loadfs)\n+\t\treturn fpga->loadfs(desc, buf, bsize, fpga_fsinfo);\n+\treturn 0;\n+}\n+#endif\ndiff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c\nindex e0fb1b4..42e901e 100644\n--- a/drivers/fpga/fpga.c\n+++ b/drivers/fpga/fpga.c\n@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,\n \t\t\tfpga_no_sup((char *)__func__, \"Xilinx devices\");\n #endif\n \t\t\tbreak;\n+#if defined(CONFIG_FPGA_ALTERA)\n+\t\tcase fpga_altera:\n+\t\t\tret_val = altera_loadfs(desc->devdesc, buf, size,\n+\t\t\t\t\t\tfpga_fsinfo);\n+#else\n+\t\t\tfpga_no_sup((char *)__func__, \"Altera devices\");\n+#endif\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tprintf(\"%s: Invalid or unsupported device type %d\\n\",\n \t\t\t __func__, desc->devtype);\ndiff --git a/include/fpga.h b/include/fpga.h\nindex d768fb1..8920016 100644\n--- a/include/fpga.h\n+++ b/include/fpga.h\n@@ -56,8 +56,10 @@ int fpga_count(void);\n const fpga_desc *const fpga_get_desc(int devnum);\n int fpga_load(int devnum, const void *buf, size_t bsize,\n \t bitstream_type bstype);\n+#if defined(CONFIG_CMD_FPGA_LOADFS)\n int fpga_fsload(int devnum, const void *buf, size_t size,\n \t\tfpga_fs_info *fpga_fsinfo);\n+#endif\n int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,\n \t\t bitstream_type bstype);\n int fpga_dump(int devnum, const void *buf, size_t bsize);\n", "prefixes": [ "U-Boot", "04/19" ] }