Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/806961/?format=api
{ "id": 806961, "url": "http://patchwork.ozlabs.org/api/patches/806961/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-8-git-send-email-sukadev@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503987820-31933-8-git-send-email-sukadev@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503987820-31933-8-git-send-email-sukadev@linux.vnet.ibm.com/", "date": "2017-08-29T06:23:37", "name": "[v8,07/10] powerpc/vas: Define vas_rx_win_open() interface", "commit_ref": "62c4eda4fabe89709ec43dcf1efe9fbea007a734", "pull_url": null, "state": "accepted", "archived": false, "hash": "ef19237fea3cfcdff944b778b1e4ed8548589594", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-8-git-send-email-sukadev@linux.vnet.ibm.com/mbox/", "series": [ { "id": 310, "url": "http://patchwork.ozlabs.org/api/series/310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=310", "date": "2017-08-29T06:23:30", "name": "Enable VAS", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806961/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806961/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJnX59Ghz9t2x\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:36:32 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhJnX4DZLzDqw7\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:36:32 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhJWP6DQFzDqTm\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:17 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xhJWN1tPNz8vDS\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:16 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhJWM73j7z9t4X; Tue, 29 Aug 2017 16:24:16 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJWM09GFz9t3w\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 16:24:14 +1000 (AEST)", "from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T6OC1T130634\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:24:13 -0400", "from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cn0dtakfk-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:24:12 -0400", "from localhost\n\tby e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@ozlabs.org> from <sukadev@linux.vnet.ibm.com>;\n\tTue, 29 Aug 2017 02:24:05 -0400", "from b01cxnp23033.gho.pok.ibm.com (9.57.198.28)\n\tby e16.ny.us.ibm.com (146.89.104.203) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tTue, 29 Aug 2017 02:24:02 -0400", "from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7T6O1OS66912346; Tue, 29 Aug 2017 06:24:01 GMT", "from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 53AE2AE03C;\n\tTue, 29 Aug 2017 02:24:25 -0400 (EDT)", "from suka-w540.usor.ibm.com (unknown [9.70.94.25])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 79DB9AE03B;\n\tTue, 29 Aug 2017 02:24:24 -0400 (EDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>", "Subject": "[PATCH v8 07/10] powerpc/vas: Define vas_rx_win_open() interface", "Date": "Mon, 28 Aug 2017 23:23:37 -0700", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "References": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17082906-0024-0000-0000-000002C6F130", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007631; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909146; UDB=6.00455922;\n\tIPR=6.00689402; \n\tBA=6.00005559; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912;\n\tXFM=3.00000015; UTC=2017-08-29 06:24:04", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082906-0025-0000-0000-0000453F061E", "Message-Id": "<1503987820-31933-8-git-send-email-sukadev@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290096", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, mikey@neuling.org, linuxppc-dev@ozlabs.org, \n\tlinux-kernel@vger.kernel.org, apopple@au1.ibm.com, oohall@gmail.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Define the vas_rx_win_open() interface. This interface is intended to be\nused by the Nest Accelerator (NX) driver(s) to setup receive windows for\none or more NX engines (which implement compression/encryption algorithms\nin the hardware).\n\nFollow-on patches will provide an interface to close the window and to open\na send window that kernel subsystems can use to access the NX engines.\n\nThe interface to open a receive window is expected to be invoked for each\ninstance of VAS in the system.\n\nSigned-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>\n---\n\nChangelog[v8]:\n\t- [Michael Ellerman] Drop vas_initialized() check; use pr_fmt;\n\t user kernel integer types (u32,64 etc);\n\t- Dropped (deferred) code that handles user rx windows.\n\nChangelog[v7]:\n\t- vas_rx_win_open() is simplified because API for FTW windows\n\t are simplified. We expect the driver to open an rxwin and txwin\n\t one after the other and we don't get back an rx_win_handle from\n\t user space so don't have to validate the pid permissions.\n\nChangelog[v6]:\n\t- Add support for FTW windows\n\nChangelog[v4]:\n\t- Export the symbols\n\nChangelog[v3]:\n\t- Fault receive windows must enable interrupts and disable\n\t notifications. NX Windows are opposite.\n\t- Use macros rather than enum for threshold-control mode\n\t- Ignore irq_ports for in-kernel windows. They are needed for\n\t user space windows and will be added later\n---\n arch/powerpc/include/asm/vas.h | 46 +++++\n arch/powerpc/platforms/powernv/vas-window.c | 283 +++++++++++++++++++++++++++-\n arch/powerpc/platforms/powernv/vas.h | 14 ++\n 3 files changed, 342 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h\nindex 33e93ca..5ce800a 100644\n--- a/arch/powerpc/include/asm/vas.h\n+++ b/arch/powerpc/include/asm/vas.h\n@@ -50,4 +50,50 @@ enum vas_cop_type {\n \tVAS_COP_TYPE_MAX,\n };\n \n+/*\n+ * Receive window attributes specified by the (in-kernel) owner of window.\n+ */\n+struct vas_rx_win_attr {\n+\tvoid *rx_fifo;\n+\tint rx_fifo_size;\n+\tint wcreds_max;\n+\n+\tbool pin_win;\n+\tbool rej_no_credit;\n+\tbool tx_wcred_mode;\n+\tbool rx_wcred_mode;\n+\tbool tx_win_ord_mode;\n+\tbool rx_win_ord_mode;\n+\tbool data_stamp;\n+\tbool nx_win;\n+\tbool fault_win;\n+\tbool user_win;\n+\tbool notify_disable;\n+\tbool intr_disable;\n+\tbool notify_early;\n+\n+\tint lnotify_lpid;\n+\tint lnotify_pid;\n+\tint lnotify_tid;\n+\tu32 pswid;\n+\n+\tint tc_mode;\n+};\n+\n+/*\n+ * Helper to initialize receive window attributes to defaults for an\n+ * NX window.\n+ */\n+extern void vas_init_rx_win_attr(struct vas_rx_win_attr *rxattr,\n+\t\t\t\tenum vas_cop_type cop);\n+\n+/*\n+ * Open a VAS receive window for the instance of VAS identified by @vasid\n+ * Use @attr to initialize the attributes of the window.\n+ *\n+ * Return a handle to the window or ERR_PTR() on error.\n+ */\n+extern struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,\n+\t\t\tstruct vas_rx_win_attr *attr);\n+\n #endif /* _MISC_VAS_H */\ndiff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c\nindex bfc9dba..783c8c6 100644\n--- a/arch/powerpc/platforms/powernv/vas-window.c\n+++ b/arch/powerpc/platforms/powernv/vas-window.c\n@@ -14,6 +14,8 @@\n #include <linux/slab.h>\n #include <linux/io.h>\n #include <linux/log2.h>\n+#include <linux/rcupdate.h>\n+#include <linux/cred.h>\n \n #include \"vas.h\"\n \n@@ -531,7 +533,7 @@ void vas_window_free(struct vas_window *window)\n \tvas_release_window_id(&vinst->ida, winid);\n }\n \n-struct vas_window *vas_window_alloc(struct vas_instance *vinst)\n+static struct vas_window *vas_window_alloc(struct vas_instance *vinst)\n {\n \tint winid;\n \tstruct vas_window *window;\n@@ -558,6 +560,285 @@ struct vas_window *vas_window_alloc(struct vas_instance *vinst)\n \treturn ERR_PTR(-ENOMEM);\n }\n \n+/*\n+ * Get the VAS receive window associated with NX engine identified\n+ * by @cop and if applicable, @pswid.\n+ *\n+ * See also function header of set_vinst_win().\n+ */\n+struct vas_window *get_vinst_rxwin(struct vas_instance *vinst,\n+\t\t\tenum vas_cop_type cop, u32 pswid)\n+{\n+\tstruct vas_window *rxwin;\n+\n+\tmutex_lock(&vinst->mutex);\n+\n+\tif (cop == VAS_COP_TYPE_842 || cop == VAS_COP_TYPE_842_HIPRI)\n+\t\trxwin = vinst->rxwin[cop] ?: ERR_PTR(-EINVAL);\n+\telse\n+\t\trxwin = ERR_PTR(-EINVAL);\n+\n+\tif (!IS_ERR(rxwin))\n+\t\tatomic_inc(&rxwin->num_txwins);\n+\n+\tmutex_unlock(&vinst->mutex);\n+\n+\treturn rxwin;\n+}\n+\n+/*\n+ * We have two tables of windows in a VAS instance. The first one,\n+ * ->windows[], contains all the windows in the instance and allows\n+ * looking up a window by its id. It is used to look up send windows\n+ * during fault handling and receive windows when pairing user space\n+ * send/receive windows.\n+ *\n+ * The second table, ->rxwin[], contains receive windows that are\n+ * associated with NX engines. This table has VAS_COP_TYPE_MAX\n+ * entries and is used to look up a receive window by its\n+ * coprocessor type.\n+ *\n+ * Here, we save @window in the ->windows[] table. If it is a receive\n+ * window, we also save the window in the ->rxwin[] table.\n+ */\n+static void set_vinst_win(struct vas_instance *vinst,\n+\t\t\tstruct vas_window *window)\n+{\n+\tint id = window->winid;\n+\n+\tmutex_lock(&vinst->mutex);\n+\n+\t/*\n+\t * There should only be one receive window for a coprocessor type\n+\t * unless its a user (FTW) window.\n+\t */\n+\tif (!window->user_win && !window->tx_win) {\n+\t\tWARN_ON_ONCE(vinst->rxwin[window->cop]);\n+\t\tvinst->rxwin[window->cop] = window;\n+\t}\n+\n+\tWARN_ON_ONCE(vinst->windows[id] != NULL);\n+\tvinst->windows[id] = window;\n+\n+\tmutex_unlock(&vinst->mutex);\n+}\n+\n+/*\n+ * Clear this window from the table(s) of windows for this VAS instance.\n+ * See also function header of set_vinst_win().\n+ */\n+void clear_vinst_win(struct vas_window *window)\n+{\n+\tint id = window->winid;\n+\tstruct vas_instance *vinst = window->vinst;\n+\n+\tmutex_lock(&vinst->mutex);\n+\n+\tif (!window->user_win && !window->tx_win) {\n+\t\tWARN_ON_ONCE(!vinst->rxwin[window->cop]);\n+\t\tvinst->rxwin[window->cop] = NULL;\n+\t}\n+\n+\tWARN_ON_ONCE(vinst->windows[id] != window);\n+\tvinst->windows[id] = NULL;\n+\n+\tmutex_unlock(&vinst->mutex);\n+}\n+\n+static void init_winctx_for_rxwin(struct vas_window *rxwin,\n+\t\t\tstruct vas_rx_win_attr *rxattr,\n+\t\t\tstruct vas_winctx *winctx)\n+{\n+\t/*\n+\t * We first zero (memset()) all fields and only set non-zero fields.\n+\t * Following fields are 0/false but maybe deserve a comment:\n+\t *\n+\t *\t->notify_os_intr_reg\tIn powerNV, send intrs to HV\n+\t *\t->notify_disable\tFalse for NX windows\n+\t *\t->intr_disable\t\tFalse for Fault Windows\n+\t *\t->xtra_write\t\tFalse for NX windows\n+\t *\t->notify_early\t\tNA for NX windows\n+\t *\t->rsvd_txbuf_count\tNA for Rx windows\n+\t *\t->lpid, ->pid, ->tid\tNA for Rx windows\n+\t */\n+\n+\tmemset(winctx, 0, sizeof(struct vas_winctx));\n+\n+\twinctx->rx_fifo = rxattr->rx_fifo;\n+\twinctx->rx_fifo_size = rxattr->rx_fifo_size;\n+\twinctx->wcreds_max = rxattr->wcreds_max ?: VAS_WCREDS_DEFAULT;\n+\twinctx->pin_win = rxattr->pin_win;\n+\n+\twinctx->nx_win = rxattr->nx_win;\n+\twinctx->fault_win = rxattr->fault_win;\n+\twinctx->rx_word_mode = rxattr->rx_win_ord_mode;\n+\twinctx->tx_word_mode = rxattr->tx_win_ord_mode;\n+\twinctx->rx_wcred_mode = rxattr->rx_wcred_mode;\n+\twinctx->tx_wcred_mode = rxattr->tx_wcred_mode;\n+\n+\tif (winctx->nx_win) {\n+\t\twinctx->data_stamp = true;\n+\t\twinctx->intr_disable = true;\n+\t\twinctx->pin_win = true;\n+\n+\t\tWARN_ON_ONCE(winctx->fault_win);\n+\t\tWARN_ON_ONCE(!winctx->rx_word_mode);\n+\t\tWARN_ON_ONCE(!winctx->tx_word_mode);\n+\t\tWARN_ON_ONCE(winctx->notify_after_count);\n+\t} else if (winctx->fault_win) {\n+\t\twinctx->notify_disable = true;\n+\t} else if (winctx->user_win) {\n+\t\t/*\n+\t\t * Section 1.8.1 Low Latency Core-Core Wake up of\n+\t\t * the VAS workbook:\n+\t\t *\n+\t\t * - disable credit checks ([tr]x_wcred_mode = false)\n+\t\t * - disable FIFO writes\n+\t\t * - enable ASB_Notify, disable interrupt\n+\t\t */\n+\t\twinctx->fifo_disable = true;\n+\t\twinctx->intr_disable = true;\n+\t\twinctx->rx_fifo = NULL;\n+\t}\n+\n+\twinctx->lnotify_lpid = rxattr->lnotify_lpid;\n+\twinctx->lnotify_pid = rxattr->lnotify_pid;\n+\twinctx->lnotify_tid = rxattr->lnotify_tid;\n+\twinctx->pswid = rxattr->pswid;\n+\twinctx->dma_type = VAS_DMA_TYPE_INJECT;\n+\twinctx->tc_mode = rxattr->tc_mode;\n+\n+\twinctx->min_scope = VAS_SCOPE_LOCAL;\n+\twinctx->max_scope = VAS_SCOPE_VECTORED_GROUP;\n+}\n+\n+static bool rx_win_args_valid(enum vas_cop_type cop,\n+\t\t\tstruct vas_rx_win_attr *attr)\n+{\n+\tdump_rx_win_attr(attr);\n+\n+\tif (cop >= VAS_COP_TYPE_MAX)\n+\t\treturn false;\n+\n+\tif (cop != VAS_COP_TYPE_FTW &&\n+\t\t\t\tattr->rx_fifo_size < VAS_RX_FIFO_SIZE_MIN)\n+\t\treturn false;\n+\n+\tif (attr->rx_fifo_size > VAS_RX_FIFO_SIZE_MAX)\n+\t\treturn false;\n+\n+\tif (attr->nx_win) {\n+\t\t/* cannot be fault or user window if it is nx */\n+\t\tif (attr->fault_win || attr->user_win)\n+\t\t\treturn false;\n+\t\t/*\n+\t\t * Section 3.1.4.32: NX Windows must not disable notification,\n+\t\t *\tand must not enable interrupts or early notification.\n+\t\t */\n+\t\tif (attr->notify_disable || !attr->intr_disable ||\n+\t\t\t\tattr->notify_early)\n+\t\t\treturn false;\n+\t} else if (attr->fault_win) {\n+\t\t/* cannot be both fault and user window */\n+\t\tif (attr->user_win)\n+\t\t\treturn false;\n+\n+\t\t/*\n+\t\t * Section 3.1.4.32: Fault windows must disable notification\n+\t\t *\tbut not interrupts.\n+\t\t */\n+\t\tif (!attr->notify_disable || attr->intr_disable)\n+\t\t\treturn false;\n+\n+\t} else if (attr->user_win) {\n+\t\t/*\n+\t\t * User receive windows are only for fast-thread-wakeup\n+\t\t * (FTW). They don't need a FIFO and must disable interrupts\n+\t\t */\n+\t\tif (attr->rx_fifo || attr->rx_fifo_size || !attr->intr_disable)\n+\t\t\treturn false;\n+\t} else {\n+\t\t/* Rx window must be one of NX or Fault or User window. */\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n+void vas_init_rx_win_attr(struct vas_rx_win_attr *rxattr, enum vas_cop_type cop)\n+{\n+\tmemset(rxattr, 0, sizeof(*rxattr));\n+\n+\tif (cop == VAS_COP_TYPE_842 || cop == VAS_COP_TYPE_842_HIPRI) {\n+\t\trxattr->pin_win = true;\n+\t\trxattr->nx_win = true;\n+\t\trxattr->fault_win = false;\n+\t\trxattr->intr_disable = true;\n+\t\trxattr->rx_wcred_mode = true;\n+\t\trxattr->tx_wcred_mode = true;\n+\t\trxattr->rx_win_ord_mode = true;\n+\t\trxattr->tx_win_ord_mode = true;\n+\t} else if (cop == VAS_COP_TYPE_FAULT) {\n+\t\trxattr->pin_win = true;\n+\t\trxattr->fault_win = true;\n+\t\trxattr->notify_disable = true;\n+\t\trxattr->rx_wcred_mode = true;\n+\t\trxattr->tx_wcred_mode = true;\n+\t\trxattr->rx_win_ord_mode = true;\n+\t\trxattr->tx_win_ord_mode = true;\n+\t} else if (cop == VAS_COP_TYPE_FTW) {\n+\t\trxattr->user_win = true;\n+\t\trxattr->intr_disable = true;\n+\n+\t\t/*\n+\t\t * As noted in the VAS Workbook we disable credit checks.\n+\t\t * If we enable credit checks in the future, we must also\n+\t\t * implement a mechanism to return the user credits or new\n+\t\t * paste operations will fail.\n+\t\t */\n+\t}\n+}\n+EXPORT_SYMBOL_GPL(vas_init_rx_win_attr);\n+\n+struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,\n+\t\t\tstruct vas_rx_win_attr *rxattr)\n+{\n+\tstruct vas_window *rxwin;\n+\tstruct vas_winctx winctx;\n+\tstruct vas_instance *vinst;\n+\n+\tif (!rx_win_args_valid(cop, rxattr))\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tvinst = find_vas_instance(vasid);\n+\tif (!vinst) {\n+\t\tpr_devel(\"vasid %d not found!\\n\", vasid);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\tpr_devel(\"Found instance %d\\n\", vasid);\n+\n+\trxwin = vas_window_alloc(vinst);\n+\tif (IS_ERR(rxwin)) {\n+\t\tpr_devel(\"Unable to allocate memory for Rx window\\n\");\n+\t\treturn rxwin;\n+\t}\n+\n+\trxwin->tx_win = false;\n+\trxwin->nx_win = rxattr->nx_win;\n+\trxwin->user_win = rxattr->user_win;\n+\trxwin->cop = cop;\n+\tif (rxattr->user_win)\n+\t\trxwin->pid = task_pid_vnr(current);\n+\n+\tinit_winctx_for_rxwin(rxwin, rxattr, &winctx);\n+\tinit_winctx_regs(rxwin, &winctx);\n+\n+\tset_vinst_win(vinst, rxwin);\n+\n+\treturn rxwin;\n+}\n+EXPORT_SYMBOL_GPL(vas_rx_win_open);\n+\n /* stub for now */\n int vas_win_close(struct vas_window *window)\n {\ndiff --git a/arch/powerpc/platforms/powernv/vas.h b/arch/powerpc/platforms/powernv/vas.h\nindex 60a3c3c..d3e4f55 100644\n--- a/arch/powerpc/platforms/powernv/vas.h\n+++ b/arch/powerpc/platforms/powernv/vas.h\n@@ -289,6 +289,9 @@ enum vas_notify_after_count {\n /*\n * One per instance of VAS. Each instance will have a separate set of\n * receive windows, one per coprocessor type.\n+ *\n+ * See also function header of set_vinst_win() for details on ->windows[]\n+ * and ->rxwin[] tables.\n */\n struct vas_instance {\n \tint vas_id;\n@@ -393,6 +396,16 @@ extern struct vas_instance *find_vas_instance(int vasid);\n #define VREG(r)\t\tVREG_SFX(r, _OFFSET)\n \n #ifdef vas_debug\n+static inline void dump_rx_win_attr(struct vas_rx_win_attr *attr)\n+{\n+\tpr_err(\"VAS: fault %d, notify %d, intr %d early %d\\n\",\n+\t\t\tattr->fault_win, attr->notify_disable,\n+\t\t\tattr->intr_disable, attr->notify_early);\n+\n+\tpr_err(\"VAS: rx_fifo_size %d, max value %d\\n\",\n+\t\t\t\tattr->rx_fifo_size, VAS_RX_FIFO_SIZE_MAX);\n+}\n+\n static inline void vas_log_write(struct vas_window *win, char *name,\n \t\t\tvoid *regptr, u64 val)\n {\n@@ -405,6 +418,7 @@ static inline void vas_log_write(struct vas_window *win, char *name,\n #else\t/* vas_debug */\n \n #define vas_log_write(win, name, reg, val)\n+#define dump_rx_win_attr(attr)\n \n #endif\t/* vas_debug */\n \n", "prefixes": [ "v8", "07/10" ] }