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GET /api/patches/806957/?format=api
{ "id": 806957, "url": "http://patchwork.ozlabs.org/api/patches/806957/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-6-git-send-email-sukadev@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503987820-31933-6-git-send-email-sukadev@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503987820-31933-6-git-send-email-sukadev@linux.vnet.ibm.com/", "date": "2017-08-29T06:23:35", "name": "[v8,05/10] powerpc/vas: Define helpers to init window context", "commit_ref": "b25b33ac18b35775949ab227bb3075bb6cb11bc3", "pull_url": null, "state": "accepted", "archived": false, "hash": "0912d1f7664ce0bf0e0ec549013457990774cd9e", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-6-git-send-email-sukadev@linux.vnet.ibm.com/mbox/", "series": [ { "id": 310, "url": "http://patchwork.ozlabs.org/api/series/310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=310", "date": "2017-08-29T06:23:30", "name": "Enable VAS", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806957/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806957/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJk02r86z9t2v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:33:28 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhJk01y31zDrTh\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:33:28 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhJWB67LFzDqTs\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:06 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xhJW95C23z8vLq\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:05 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhJW84BHZz9t3t; Tue, 29 Aug 2017 16:24:04 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJW76Sspz9t3J\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 16:24:03 +1000 (AEST)", "from pps.filterd (m0098420.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T6JNCt004018\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:24:01 -0400", "from e12.ny.us.ibm.com (e12.ny.us.ibm.com [129.33.205.202])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2cmx9uj3v7-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:24:01 -0400", "from localhost\n\tby e12.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tTue, 29 Aug 2017 02:23:58 -0400", "from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7T6NvnV32637132; Tue, 29 Aug 2017 06:23:57 GMT", "from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 6C3FDAE034;\n\tTue, 29 Aug 2017 02:24:21 -0400 (EDT)", "from suka-w540.usor.ibm.com (unknown [9.70.94.25])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 888B8AE04E;\n\tTue, 29 Aug 2017 02:24:20 -0400 (EDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>", "Subject": "[PATCH v8 05/10] powerpc/vas: Define helpers to init window context", "Date": "Mon, 28 Aug 2017 23:23:35 -0700", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "References": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17082906-0048-0000-0000-000001DB0A23", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007631; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909146; UDB=6.00455923;\n\tIPR=6.00689401; \n\tBA=6.00005559; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912;\n\tXFM=3.00000015; UTC=2017-08-29 06:24:00", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082906-0049-0000-0000-0000426238B2", "Message-Id": "<1503987820-31933-6-git-send-email-sukadev@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290094", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, mikey@neuling.org, linuxppc-dev@ozlabs.org, \n\tlinux-kernel@vger.kernel.org, apopple@au1.ibm.com, oohall@gmail.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Define helpers to initialize window context registers of the VAS\nhardware. These will be used in follow-on patches when opening/closing\nVAS windows.\n\nSigned-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>\n---\nChangelog[v8]:\n\t- Update comments (ISA references and some cleanup)\n\t- Use 0 or 1 when setting boolean fields with SET_FIELD()\n\t- Don't write to spare/unused registers.\n\t- Use kernel integer types (u64/u32/s32)\nChangelog[v6]\n\t- Add support for FTW windows and drop the fault window id\n\t code since it is not needed for FTW/kernel windows.\nChangelog[v5]\n\t- Fix: Copy the FIFO address into LFIFO_BAR register as is (don't\n\t shift address into bits 8:53).\n\nChangelog[v4]\n\t- Michael Neuling] Use ilog2(), radix_enabled() helpers;\n\t drop warning when 32-bit app uses VAS (a follow-on patch\n\t will check and return error). Set MSR_PR state to 0 for\n\t kernel (rather than reading from MSR).\n\nChangelog[v3]\n\t- Have caller, rather than init_xlate_regs() reset window regs\n\t so we don't reset any settings caller may already have set.\n\t- Translation mode should be 0x3 (0b11) not 0x11.\n\t- Skip initilaizing read-only registers NX_UTIL and NX_UTIL_SE\n\t- Skip initializing adder registers from UWC - they are already\n\t initialized from the HVWC.\n\t- Check winctx->user_win when setting translation registers\n---\n arch/powerpc/platforms/powernv/vas-window.c | 299 ++++++++++++++++++++++++++++\n arch/powerpc/platforms/powernv/vas.h | 55 +++++\n 2 files changed, 354 insertions(+)", "diff": "diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c\nindex 642814a2..68dfe53 100644\n--- a/arch/powerpc/platforms/powernv/vas-window.c\n+++ b/arch/powerpc/platforms/powernv/vas-window.c\n@@ -13,6 +13,7 @@\n #include <linux/mutex.h>\n #include <linux/slab.h>\n #include <linux/io.h>\n+#include <linux/log2.h>\n \n #include \"vas.h\"\n \n@@ -186,6 +187,304 @@ int map_winctx_mmio_bars(struct vas_window *window)\n \treturn 0;\n }\n \n+/*\n+ * Reset all valid registers in the HV and OS/User Window Contexts for\n+ * the window identified by @window.\n+ *\n+ * NOTE: We cannot really use a for loop to reset window context. Not all\n+ *\t offsets in a window context are valid registers and the valid\n+ *\t registers are not sequential. And, we can only write to offsets\n+ *\t with valid registers.\n+ */\n+void reset_window_regs(struct vas_window *window)\n+{\n+\twrite_hvwc_reg(window, VREG(LPID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(PID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(XLATE_MSR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(XLATE_CTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(AMR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(SEIDR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL);\n+\twrite_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);\n+\twrite_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL);\n+\twrite_hvwc_reg(window, VREG(PSWID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LFIFO_BAR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LDATA_STAMP_CTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LDMA_CACHE_CTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);\n+\twrite_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LRX_WCRED), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);\n+\twrite_hvwc_reg(window, VREG(TX_WCRED), 0ULL);\n+\twrite_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LFIFO_SIZE), 0ULL);\n+\twrite_hvwc_reg(window, VREG(WINCTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);\n+\twrite_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(TX_RSVD_BUF_COUNT), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_CTL), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_PID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_LPID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_TID), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_SCOPE), 0ULL);\n+\twrite_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);\n+\n+\t/* Skip read-only registers: NX_UTIL and NX_UTIL_SE */\n+\n+\t/*\n+\t * The send and receive window credit adder registers are also\n+\t * accessible from HVWC and have been initialized above. We don't\n+\t * need to initialize from the OS/User Window Context, so skip\n+\t * following calls:\n+\t *\n+\t *\twrite_uwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);\n+\t *\twrite_uwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);\n+\t */\n+}\n+\n+/*\n+ * Initialize window context registers related to Address Translation.\n+ * These registers are common to send/receive windows although they\n+ * differ for user/kernel windows. As we resolve the TODOs we may\n+ * want to add fields to vas_winctx and move the initialization to\n+ * init_vas_winctx_regs().\n+ */\n+static void init_xlate_regs(struct vas_window *window, bool user_win)\n+{\n+\tu64 lpcr, val;\n+\n+\t/*\n+\t * MSR_TA, MSR_US are false for both kernel and user.\n+\t * MSR_DR and MSR_PR are false for kernel.\n+\t */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_XLATE_MSR_HV, val, 1);\n+\tval = SET_FIELD(VAS_XLATE_MSR_SF, val, 1);\n+\tif (user_win) {\n+\t\tval = SET_FIELD(VAS_XLATE_MSR_DR, val, 1);\n+\t\tval = SET_FIELD(VAS_XLATE_MSR_PR, val, 1);\n+\t}\n+\twrite_hvwc_reg(window, VREG(XLATE_MSR), val);\n+\n+\tlpcr = mfspr(SPRN_LPCR);\n+\tval = 0ULL;\n+\t/*\n+\t * NOTE: From Section 5.7.8.1 Segment Lookaside Buffer of the\n+\t *\t Power ISA, v3.0B, Page size encoding is 0 = 4KB, 5 = 64KB.\n+\t *\n+\t * NOTE: From Section 1.3.1, Address Translation Context of the\n+\t *\t Nest MMU Workbook, LPCR_SC should be 0 for Power9.\n+\t */\n+\tval = SET_FIELD(VAS_XLATE_LPCR_PAGE_SIZE, val, 5);\n+\tval = SET_FIELD(VAS_XLATE_LPCR_ISL, val, lpcr & LPCR_ISL);\n+\tval = SET_FIELD(VAS_XLATE_LPCR_TC, val, lpcr & LPCR_TC);\n+\tval = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0);\n+\twrite_hvwc_reg(window, VREG(XLATE_LPCR), val);\n+\n+\t/*\n+\t * Section 1.3.1 (Address translation Context) of NMMU workbook.\n+\t *\t0b00\tHashed Page Table mode\n+\t *\t0b01\tReserved\n+\t *\t0b10\tRadix on HPT\n+\t *\t0b11\tRadix on Radix\n+\t */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_XLATE_MODE, val, radix_enabled() ? 3 : 2);\n+\twrite_hvwc_reg(window, VREG(XLATE_CTL), val);\n+\n+\t/*\n+\t * TODO: Can we mfspr(AMR) even for user windows?\n+\t */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_AMR, val, mfspr(SPRN_AMR));\n+\twrite_hvwc_reg(window, VREG(AMR), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_SEIDR, val, 0);\n+\twrite_hvwc_reg(window, VREG(SEIDR), val);\n+}\n+\n+/*\n+ * Initialize Reserved Send Buffer Count for the send window. It involves\n+ * writing to the register, reading it back to confirm that the hardware\n+ * has enough buffers to reserve. See section 1.3.1.2.1 of VAS workbook.\n+ *\n+ * Since we can only make a best-effort attempt to fulfill the request,\n+ * we don't return any errors if we cannot.\n+ *\n+ * TODO: Reserved (aka dedicated) send buffers are not supported yet.\n+ */\n+static void init_rsvd_tx_buf_count(struct vas_window *txwin,\n+\t\t\t\tstruct vas_winctx *winctx)\n+{\n+\twrite_hvwc_reg(txwin, VREG(TX_RSVD_BUF_COUNT), 0ULL);\n+}\n+\n+/*\n+ * init_winctx_regs()\n+ *\tInitialize window context registers for a receive window.\n+ *\tExcept for caching control and marking window open, the registers\n+ *\tare initialized in the order listed in Section 3.1.4 (Window Context\n+ *\tCache Register Details) of the VAS workbook although they don't need\n+ *\tto be.\n+ *\n+ * Design note: For NX receive windows, NX allocates the FIFO buffer in OPAL\n+ *\t(so that it can get a large contiguous area) and passes that buffer\n+ *\tto kernel via device tree. We now write that buffer address to the\n+ *\tFIFO BAR. Would it make sense to do this all in OPAL? i.e have OPAL\n+ *\twrite the per-chip RX FIFO addresses to the windows during boot-up\n+ *\tas a one-time task? That could work for NX but what about other\n+ *\treceivers? Let the receivers tell us the rx-fifo buffers for now.\n+ */\n+int init_winctx_regs(struct vas_window *window, struct vas_winctx *winctx)\n+{\n+\tu64 val;\n+\tint fifo_size;\n+\n+\treset_window_regs(window);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LPID, val, winctx->lpid);\n+\twrite_hvwc_reg(window, VREG(LPID), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_PID_ID, val, winctx->pidr);\n+\twrite_hvwc_reg(window, VREG(PID), val);\n+\n+\tinit_xlate_regs(window, winctx->user_win);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_FAULT_TX_WIN, val, 0);\n+\twrite_hvwc_reg(window, VREG(FAULT_TX_WIN), val);\n+\n+\t/* In PowerNV, interrupts go to HV. */\n+\twrite_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_HV_INTR_SRC_RA, val, winctx->irq_port);\n+\twrite_hvwc_reg(window, VREG(HV_INTR_SRC_RA), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_PSWID_EA_HANDLE, val, winctx->pswid);\n+\twrite_hvwc_reg(window, VREG(PSWID), val);\n+\n+\twrite_hvwc_reg(window, VREG(SPARE1), 0ULL);\n+\twrite_hvwc_reg(window, VREG(SPARE2), 0ULL);\n+\twrite_hvwc_reg(window, VREG(SPARE3), 0ULL);\n+\n+\t/*\n+\t * NOTE: VAS expects the FIFO address to be copied into the LFIFO_BAR\n+\t *\t register as is - do NOT shift the address into VAS_LFIFO_BAR\n+\t *\t bit fields! Ok to set the page migration select fields -\n+\t *\t VAS ignores the lower 10+ bits in the address anyway, because\n+\t *\t the minimum FIFO size is 1K?\n+\t *\n+\t * See also: Design note in function header.\n+\t */\n+\tval = __pa(winctx->rx_fifo);\n+\tval = SET_FIELD(VAS_PAGE_MIGRATION_SELECT, val, 0);\n+\twrite_hvwc_reg(window, VREG(LFIFO_BAR), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LDATA_STAMP, val, winctx->data_stamp);\n+\twrite_hvwc_reg(window, VREG(LDATA_STAMP_CTL), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LDMA_TYPE, val, winctx->dma_type);\n+\tval = SET_FIELD(VAS_LDMA_FIFO_DISABLE, val, winctx->fifo_disable);\n+\twrite_hvwc_reg(window, VREG(LDMA_CACHE_CTL), val);\n+\n+\twrite_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);\n+\twrite_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LRX_WCRED, val, winctx->wcreds_max);\n+\twrite_hvwc_reg(window, VREG(LRX_WCRED), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_TX_WCRED, val, winctx->wcreds_max);\n+\twrite_hvwc_reg(window, VREG(TX_WCRED), val);\n+\n+\twrite_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);\n+\twrite_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);\n+\n+\tfifo_size = winctx->rx_fifo_size / 1024;\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LFIFO_SIZE, val, ilog2(fifo_size));\n+\twrite_hvwc_reg(window, VREG(LFIFO_SIZE), val);\n+\n+\t/* Update window control and caching control registers last so\n+\t * we mark the window open only after fully initializing it and\n+\t * pushing context to cache.\n+\t */\n+\n+\twrite_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);\n+\n+\tinit_rsvd_tx_buf_count(window, winctx);\n+\n+\t/* for a send window, point to the matching receive window */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LRX_WIN_ID, val, winctx->rx_win_id);\n+\twrite_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), val);\n+\n+\twrite_hvwc_reg(window, VREG(SPARE4), 0ULL);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_NOTIFY_DISABLE, val, winctx->notify_disable);\n+\tval = SET_FIELD(VAS_INTR_DISABLE, val, winctx->intr_disable);\n+\tval = SET_FIELD(VAS_NOTIFY_EARLY, val, winctx->notify_early);\n+\tval = SET_FIELD(VAS_NOTIFY_OSU_INTR, val, winctx->notify_os_intr_reg);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_CTL), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LNOTIFY_PID, val, winctx->lnotify_pid);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_PID), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LNOTIFY_LPID, val, winctx->lnotify_lpid);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_LPID), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LNOTIFY_TID, val, winctx->lnotify_tid);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_TID), val);\n+\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_LNOTIFY_MIN_SCOPE, val, winctx->min_scope);\n+\tval = SET_FIELD(VAS_LNOTIFY_MAX_SCOPE, val, winctx->max_scope);\n+\twrite_hvwc_reg(window, VREG(LNOTIFY_SCOPE), val);\n+\n+\t/* Skip read-only registers NX_UTIL and NX_UTIL_SE */\n+\n+\twrite_hvwc_reg(window, VREG(SPARE5), 0ULL);\n+\twrite_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);\n+\twrite_hvwc_reg(window, VREG(SPARE6), 0ULL);\n+\n+\t/* Finally, push window context to memory and... */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_PUSH_TO_MEM, val, 1);\n+\twrite_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);\n+\n+\t/* ... mark the window open for business */\n+\tval = 0ULL;\n+\tval = SET_FIELD(VAS_WINCTL_REJ_NO_CREDIT, val, winctx->rej_no_credit);\n+\tval = SET_FIELD(VAS_WINCTL_PIN, val, winctx->pin_win);\n+\tval = SET_FIELD(VAS_WINCTL_TX_WCRED_MODE, val, winctx->tx_wcred_mode);\n+\tval = SET_FIELD(VAS_WINCTL_RX_WCRED_MODE, val, winctx->rx_wcred_mode);\n+\tval = SET_FIELD(VAS_WINCTL_TX_WORD_MODE, val, winctx->tx_word_mode);\n+\tval = SET_FIELD(VAS_WINCTL_RX_WORD_MODE, val, winctx->rx_word_mode);\n+\tval = SET_FIELD(VAS_WINCTL_FAULT_WIN, val, winctx->fault_win);\n+\tval = SET_FIELD(VAS_WINCTL_NX_WIN, val, winctx->nx_win);\n+\tval = SET_FIELD(VAS_WINCTL_OPEN, val, 1);\n+\twrite_hvwc_reg(window, VREG(WINCTL), val);\n+\n+\treturn 0;\n+}\n+\n /* stub for now */\n int vas_win_close(struct vas_window *window)\n {\ndiff --git a/arch/powerpc/platforms/powernv/vas.h b/arch/powerpc/platforms/powernv/vas.h\nindex 650805d..60a3c3c 100644\n--- a/arch/powerpc/platforms/powernv/vas.h\n+++ b/arch/powerpc/platforms/powernv/vas.h\n@@ -12,6 +12,7 @@\n #include <linux/atomic.h>\n #include <linux/idr.h>\n #include <asm/vas.h>\n+#include <linux/io.h>\n \n /*\n * Overview of Virtual Accelerator Switchboard (VAS).\n@@ -381,4 +382,58 @@ struct vas_winctx {\n \n extern struct vas_instance *find_vas_instance(int vasid);\n \n+/*\n+ * VREG(x):\n+ * Expand a register's short name (eg: LPID) into two parameters:\n+ *\t- the register's short name in string form (\"LPID\"), and\n+ *\t- the name of the macro (eg: VAS_LPID_OFFSET), defining the\n+ *\t register's offset in the window context\n+ */\n+#define VREG_SFX(n, s)\t__stringify(n), VAS_##n##s\n+#define VREG(r)\t\tVREG_SFX(r, _OFFSET)\n+\n+#ifdef vas_debug\n+static inline void vas_log_write(struct vas_window *win, char *name,\n+\t\t\tvoid *regptr, u64 val)\n+{\n+\tif (val)\n+\t\tpr_err(\"%swin #%d: %s reg %p, val 0x%016llx\\n\",\n+\t\t\t\twin->tx_win ? \"Tx\" : \"Rx\", win->winid, name,\n+\t\t\t\tregptr, val);\n+}\n+\n+#else\t/* vas_debug */\n+\n+#define vas_log_write(win, name, reg, val)\n+\n+#endif\t/* vas_debug */\n+\n+static inline void write_uwc_reg(struct vas_window *win, char *name,\n+\t\t\ts32 reg, u64 val)\n+{\n+\tvoid *regptr;\n+\n+\tregptr = win->uwc_map + reg;\n+\tvas_log_write(win, name, regptr, val);\n+\n+\tout_be64(regptr, val);\n+}\n+\n+static inline void write_hvwc_reg(struct vas_window *win, char *name,\n+\t\t\ts32 reg, u64 val)\n+{\n+\tvoid *regptr;\n+\n+\tregptr = win->hvwc_map + reg;\n+\tvas_log_write(win, name, regptr, val);\n+\n+\tout_be64(regptr, val);\n+}\n+\n+static inline u64 read_hvwc_reg(struct vas_window *win,\n+\t\t\tchar *name __maybe_unused, s32 reg)\n+{\n+\treturn in_be64(win->hvwc_map+reg);\n+}\n+\n #endif /* _VAS_H */\n", "prefixes": [ "v8", "05/10" ] }