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GET /api/patches/806956/?format=api
{ "id": 806956, "url": "http://patchwork.ozlabs.org/api/patches/806956/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-5-git-send-email-sukadev@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503987820-31933-5-git-send-email-sukadev@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503987820-31933-5-git-send-email-sukadev@linux.vnet.ibm.com/", "date": "2017-08-29T06:23:34", "name": "[v8,04/10] powerpc/vas: Define helpers to access MMIO regions", "commit_ref": "180fe15a8299c14f77347c5835c98c2446226ee6", "pull_url": null, "state": "accepted", "archived": false, "hash": "3fe89362125989e8e82a477da99c8c546999c50c", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-5-git-send-email-sukadev@linux.vnet.ibm.com/mbox/", "series": [ { "id": 310, "url": "http://patchwork.ozlabs.org/api/series/310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=310", "date": "2017-08-29T06:23:30", "name": "Enable VAS", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806956/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806956/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJhW4ryNz9t2v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:32:11 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhJhW41qNzDrJF\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:32:11 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhJW71KQ7zDqVg\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:03 +1000 (AEST)", "from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xhJW670QQz8vLq\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:24:02 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhJW65psWz9t3t; Tue, 29 Aug 2017 16:24:02 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJW60Gljz9t3J\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 16:24:01 +1000 (AEST)", "from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T6KDf7119831\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:24:00 -0400", "from e14.ny.us.ibm.com (e14.ny.us.ibm.com [129.33.205.204])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cn0dtak9g-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:23:59 -0400", "from localhost\n\tby e14.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tTue, 29 Aug 2017 02:23:56 -0400", "from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7T6NtHe33292316; Tue, 29 Aug 2017 06:23:55 GMT", "from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 6EAA2AE034;\n\tTue, 29 Aug 2017 02:24:19 -0400 (EDT)", "from suka-w540.usor.ibm.com (unknown [9.70.94.25])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 94BB2AE03B;\n\tTue, 29 Aug 2017 02:24:18 -0400 (EDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>", "Subject": "[PATCH v8 04/10] powerpc/vas: Define helpers to access MMIO regions", "Date": "Mon, 28 Aug 2017 23:23:34 -0700", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "References": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17082906-0052-0000-0000-00000257539A", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007631; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909146; UDB=6.00455922;\n\tIPR=6.00689402; \n\tBA=6.00005559; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912;\n\tXFM=3.00000015; UTC=2017-08-29 06:23:58", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082906-0053-0000-0000-000051D27DEA", "Message-Id": "<1503987820-31933-5-git-send-email-sukadev@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=2\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290094", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, mikey@neuling.org, linuxppc-dev@ozlabs.org, \n\tlinux-kernel@vger.kernel.org, apopple@au1.ibm.com, oohall@gmail.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Define some helper functions to access the MMIO regions. We use these\nin follow-on patches to read/write VAS hardware registers. They are\nalso used to later issue 'paste' instructions to submit requests to\nthe NX hardware engines.\n\nSigned-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>\n---\nChangelog [v8]:\n\tMinor cleanup of error/debug messages\n\nChangelog [v6]:\n\t- Minor reorg to make setup/cleanup functions more symmetric\n\nChangelog [v5]:\n\t- [Ben Herrenschmidt]: Need cachable mapping for paste regions\n\t and non-cachable mapping for the MMIO regions. So, just use\n\t ioremap() for mapping the MMIO regions; use \"winctx\" instead\n\t of \"wc\" to avoid collision with \"write combine\".\n\nChangelog [v3]:\n\t- Minor reorg/cleanup of map/unmap functions\n\nChangelog [v2]:\n\t- Get HVWC, UWC and paste addresses from window->vinst (i.e DT)\n\t rather than kernel macros.\n---\n arch/powerpc/platforms/powernv/vas-window.c | 174 ++++++++++++++++++++++++++++\n 1 file changed, 174 insertions(+)", "diff": "diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c\nindex de21acb..642814a2 100644\n--- a/arch/powerpc/platforms/powernv/vas-window.c\n+++ b/arch/powerpc/platforms/powernv/vas-window.c\n@@ -7,11 +7,185 @@\n * 2 of the License, or (at your option) any later version.\n */\n \n+#define pr_fmt(fmt) \"vas: \" fmt\n+\n #include <linux/types.h>\n #include <linux/mutex.h>\n+#include <linux/slab.h>\n+#include <linux/io.h>\n \n #include \"vas.h\"\n \n+/*\n+ * Compute the paste address region for the window @window using the\n+ * ->paste_base_addr and ->paste_win_id_shift we got from device tree.\n+ */\n+static void compute_paste_address(struct vas_window *window, u64 *addr, int *len)\n+{\n+\tint winid;\n+\tu64 base, shift;\n+\n+\tbase = window->vinst->paste_base_addr;\n+\tshift = window->vinst->paste_win_id_shift;\n+\twinid = window->winid;\n+\n+\t*addr = base + (winid << shift);\n+\tif (len)\n+\t\t*len = PAGE_SIZE;\n+\n+\tpr_debug(\"Txwin #%d: Paste addr 0x%llx\\n\", winid, *addr);\n+}\n+\n+static inline void get_hvwc_mmio_bar(struct vas_window *window,\n+\t\t\tu64 *start, int *len)\n+{\n+\tu64 pbaddr;\n+\n+\tpbaddr = window->vinst->hvwc_bar_start;\n+\t*start = pbaddr + window->winid * VAS_HVWC_SIZE;\n+\t*len = VAS_HVWC_SIZE;\n+}\n+\n+static inline void get_uwc_mmio_bar(struct vas_window *window,\n+\t\t\tu64 *start, int *len)\n+{\n+\tu64 pbaddr;\n+\n+\tpbaddr = window->vinst->uwc_bar_start;\n+\t*start = pbaddr + window->winid * VAS_UWC_SIZE;\n+\t*len = VAS_UWC_SIZE;\n+}\n+\n+/*\n+ * Map the paste bus address of the given send window into kernel address\n+ * space. Unlike MMIO regions (map_mmio_region() below), paste region must\n+ * be mapped cache-able and is only applicable to send windows.\n+ */\n+void *map_paste_region(struct vas_window *txwin)\n+{\n+\tint len;\n+\tvoid *map;\n+\tchar *name;\n+\tu64 start;\n+\n+\tname = kasprintf(GFP_KERNEL, \"window-v%d-w%d\", txwin->vinst->vas_id,\n+\t\t\t\ttxwin->winid);\n+\tif (!name)\n+\t\tgoto free_name;\n+\n+\ttxwin->paste_addr_name = name;\n+\tcompute_paste_address(txwin, &start, &len);\n+\n+\tif (!request_mem_region(start, len, name)) {\n+\t\tpr_devel(\"%s(): request_mem_region(0x%llx, %d) failed\\n\",\n+\t\t\t\t__func__, start, len);\n+\t\tgoto free_name;\n+\t}\n+\n+\tmap = ioremap_cache(start, len);\n+\tif (!map) {\n+\t\tpr_devel(\"%s(): ioremap_cache(0x%llx, %d) failed\\n\", __func__,\n+\t\t\t\tstart, len);\n+\t\tgoto free_name;\n+\t}\n+\n+\tpr_devel(\"Mapped paste addr 0x%llx to kaddr 0x%p\\n\", start, map);\n+\treturn map;\n+\n+free_name:\n+\tkfree(name);\n+\treturn ERR_PTR(-ENOMEM);\n+}\n+\n+\n+static void *map_mmio_region(char *name, u64 start, int len)\n+{\n+\tvoid *map;\n+\n+\tif (!request_mem_region(start, len, name)) {\n+\t\tpr_devel(\"%s(): request_mem_region(0x%llx, %d) failed\\n\",\n+\t\t\t\t__func__, start, len);\n+\t\treturn NULL;\n+\t}\n+\n+\tmap = ioremap(start, len);\n+\tif (!map) {\n+\t\tpr_devel(\"%s(): ioremap(0x%llx, %d) failed\\n\", __func__, start,\n+\t\t\t\tlen);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn map;\n+}\n+\n+static void unmap_region(void *addr, u64 start, int len)\n+{\n+\tiounmap(addr);\n+\trelease_mem_region((phys_addr_t)start, len);\n+}\n+\n+/*\n+ * Unmap the paste address region for a window.\n+ */\n+void unmap_paste_region(struct vas_window *window)\n+{\n+\tint len;\n+\tu64 busaddr_start;\n+\n+\tif (window->paste_kaddr) {\n+\t\tcompute_paste_address(window, &busaddr_start, &len);\n+\t\tunmap_region(window->paste_kaddr, busaddr_start, len);\n+\t\twindow->paste_kaddr = NULL;\n+\t\tkfree(window->paste_addr_name);\n+\t\twindow->paste_addr_name = NULL;\n+\t}\n+}\n+\n+/*\n+ * Unmap the MMIO regions for a window.\n+ */\n+static void unmap_winctx_mmio_bars(struct vas_window *window)\n+{\n+\tint len;\n+\tu64 busaddr_start;\n+\n+\tif (window->hvwc_map) {\n+\t\tget_hvwc_mmio_bar(window, &busaddr_start, &len);\n+\t\tunmap_region(window->hvwc_map, busaddr_start, len);\n+\t\twindow->hvwc_map = NULL;\n+\t}\n+\n+\tif (window->uwc_map) {\n+\t\tget_uwc_mmio_bar(window, &busaddr_start, &len);\n+\t\tunmap_region(window->uwc_map, busaddr_start, len);\n+\t\twindow->uwc_map = NULL;\n+\t}\n+}\n+\n+/*\n+ * Find the Hypervisor Window Context (HVWC) MMIO Base Address Region and the\n+ * OS/User Window Context (UWC) MMIO Base Address Region for the given window.\n+ * Map these bus addresses and save the mapped kernel addresses in @window.\n+ */\n+int map_winctx_mmio_bars(struct vas_window *window)\n+{\n+\tint len;\n+\tu64 start;\n+\n+\tget_hvwc_mmio_bar(window, &start, &len);\n+\twindow->hvwc_map = map_mmio_region(\"HVWCM_Window\", start, len);\n+\n+\tget_uwc_mmio_bar(window, &start, &len);\n+\twindow->uwc_map = map_mmio_region(\"UWCM_Window\", start, len);\n+\n+\tif (!window->hvwc_map || !window->uwc_map) {\n+\t\tunmap_winctx_mmio_bars(window);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* stub for now */\n int vas_win_close(struct vas_window *window)\n {\n", "prefixes": [ "v8", "04/10" ] }