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GET /api/patches/806953/?format=api
{ "id": 806953, "url": "http://patchwork.ozlabs.org/api/patches/806953/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-2-git-send-email-sukadev@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503987820-31933-2-git-send-email-sukadev@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503987820-31933-2-git-send-email-sukadev@linux.vnet.ibm.com/", "date": "2017-08-29T06:23:31", "name": "[v8,01/10] powerpc/vas: Define macros, register fields and structures", "commit_ref": "967689141eb37c4365eac0fac82d857773098475", "pull_url": null, "state": "accepted", "archived": false, "hash": "2ed90b5971d0388a0ee43eb3fee7e0dd654e3adb", "submitter": { "id": 984, "url": "http://patchwork.ozlabs.org/api/people/984/?format=api", "name": "Sukadev Bhattiprolu", "email": "sukadev@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503987820-31933-2-git-send-email-sukadev@linux.vnet.ibm.com/mbox/", "series": [ { "id": 310, "url": "http://patchwork.ozlabs.org/api/series/310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=310", "date": "2017-08-29T06:23:30", "name": "Enable VAS", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806953/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJbF53VVz9t2v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:27:37 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhJbF3tcvzDqZ5\n\tfor <patchwork-incoming@ozlabs.org>;\n\tTue, 29 Aug 2017 16:27:37 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhJW26Kn7zDqR9\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:23:58 +1000 (AEST)", "from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 3xhJW25Z49z8vDS\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tTue, 29 Aug 2017 16:23:58 +1000 (AEST)", "by ozlabs.org (Postfix)\n\tid 3xhJW25L4pz9t3f; Tue, 29 Aug 2017 16:23:58 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhJW22kQyz9t3P\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 16:23:58 +1000 (AEST)", "from pps.filterd (m0098404.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T6KVpK109602\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:23:56 -0400", "from e19.ny.us.ibm.com (e19.ny.us.ibm.com [129.33.205.209])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cmwgaky3p-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@ozlabs.org>; Tue, 29 Aug 2017 02:23:55 -0400", "from localhost\n\tby e19.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tTue, 29 Aug 2017 02:23:50 -0400", "from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com\n\t[9.57.199.110])\n\tby b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid v7T6NnQk26280136; Tue, 29 Aug 2017 06:23:49 GMT", "from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 92A79AE04B;\n\tTue, 29 Aug 2017 02:24:13 -0400 (EDT)", "from suka-w540.usor.ibm.com (unknown [9.70.94.25])\n\tby b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id AEB79AE034;\n\tTue, 29 Aug 2017 02:24:12 -0400 (EDT)" ], "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=sukadev@linux.vnet.ibm.com; receiver=<UNKNOWN>)", "From": "Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>", "To": "Michael Ellerman <mpe@ellerman.id.au>", "Subject": "[PATCH v8 01/10] powerpc/vas: Define macros,\n\tregister fields and structures", "Date": "Mon, 28 Aug 2017 23:23:31 -0700", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "References": "<1503987820-31933-1-git-send-email-sukadev@linux.vnet.ibm.com>", "X-TM-AS-GCONF": "00", "x-cbid": "17082906-0056-0000-0000-000003BDFABA", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007631; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000226; SDB=6.00909146; UDB=6.00455922;\n\tIPR=6.00689401; \n\tBA=6.00005559; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912;\n\tXFM=3.00000015; UTC=2017-08-29 06:23:52", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082906-0057-0000-0000-000007F42B66", "Message-Id": "<1503987820-31933-2-git-send-email-sukadev@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-29_01:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708290094", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "stewart@linux.vnet.ibm.com, mikey@neuling.org, linuxppc-dev@ozlabs.org, \n\tlinux-kernel@vger.kernel.org, apopple@au1.ibm.com, oohall@gmail.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Define macros for the VAS hardware registers and bit-fields as well\nas couple of data structures needed by the VAS driver.\n\nSigned-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>\n---\nChangelog[v8]\n\t- Use u64/u32 instead of the uintXX versions.\n\nChangelog[v7]\n\t- Move the threshold control macros from uapi/asm/vas.h to\n\t asm/vas.h for now. When we actually have an user space need for\n\t them, we can move them to uapi/asm/vas.h. With this change,\n\t uapi/asm/vas.h is empty and can be dropped from this patch.\n\nChangelog[v6]\n\t- Add some fields for FTW windows\n\nChangelog[v4]\n\t- [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and\n\t vas-internal.h to kernel and uapi versions; rather than creating\n\t separate properties for window context/address entries in device\n\t tree, combine them into \"reg\" properties; drop ->hwirq and irq_port\n\t fields from vas_window as they are only needed with user space\n\t windows.\n\t- Drop the error check for CONFIG_PPC_4K_PAGES. Instead in a\n\t follow-on patch add a \"depends on CONFIG_PPC_64K_PAGES\".\n\nChangelog[v3]\n\t- Rename winctx->pid to winctx->pidr to reflect that its a value\n\t from the PID register (SPRN_PID), not the linux process id.\n\t- Make it easier to split header into kernel/user parts\n\t- To keep user interface simple, use macros rather than enum for\n\t the threshold-control modes.\n\t- Add a pid field to struct vas_window - needed for user space\n\t send windows.\n\nChangelog[v2]\n\t- Add an overview of VAS in vas-internal.h\n\t- Get window context parameters from device tree and drop\n\t unnecessary macros.\n---\n arch/powerpc/include/asm/vas.h | 45 +++++\n arch/powerpc/platforms/powernv/vas.h | 382 +++++++++++++++++++++++++++++++++++\n 2 files changed, 427 insertions(+)\n create mode 100644 arch/powerpc/include/asm/vas.h\n create mode 100644 arch/powerpc/platforms/powernv/vas.h", "diff": "diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h\nnew file mode 100644\nindex 0000000..ff87e44\n--- /dev/null\n+++ b/arch/powerpc/include/asm/vas.h\n@@ -0,0 +1,45 @@\n+/*\n+ * Copyright 2016-17 IBM Corp.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ */\n+\n+#ifndef _MISC_VAS_H\n+#define _MISC_VAS_H\n+\n+/*\n+ * Min and max FIFO sizes are based on Version 1.05 Section 3.1.4.25\n+ * (Local FIFO Size Register) of the VAS workbook.\n+ */\n+#define VAS_RX_FIFO_SIZE_MIN\t(1 << 10)\t/* 1KB */\n+#define VAS_RX_FIFO_SIZE_MAX\t(8 << 20)\t/* 8MB */\n+\n+/*\n+ * Threshold Control Mode: Have paste operation fail if the number of\n+ * requests in receive FIFO exceeds a threshold.\n+ *\n+ * NOTE: No special error code yet if paste is rejected because of these\n+ *\t limits. So users can't distinguish between this and other errors.\n+ */\n+#define VAS_THRESH_DISABLED\t\t0\n+#define VAS_THRESH_FIFO_GT_HALF_FULL\t1\n+#define VAS_THRESH_FIFO_GT_QTR_FULL\t2\n+#define VAS_THRESH_FIFO_GT_EIGHTH_FULL\t3\n+\n+/*\n+ * Co-processor Engine type.\n+ */\n+enum vas_cop_type {\n+\tVAS_COP_TYPE_FAULT,\n+\tVAS_COP_TYPE_842,\n+\tVAS_COP_TYPE_842_HIPRI,\n+\tVAS_COP_TYPE_GZIP,\n+\tVAS_COP_TYPE_GZIP_HIPRI,\n+\tVAS_COP_TYPE_FTW,\n+\tVAS_COP_TYPE_MAX,\n+};\n+\n+#endif /* _MISC_VAS_H */\ndiff --git a/arch/powerpc/platforms/powernv/vas.h b/arch/powerpc/platforms/powernv/vas.h\nnew file mode 100644\nindex 0000000..abb545f\n--- /dev/null\n+++ b/arch/powerpc/platforms/powernv/vas.h\n@@ -0,0 +1,382 @@\n+/*\n+ * Copyright 2016-17 IBM Corp.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ */\n+\n+#ifndef _VAS_H\n+#define _VAS_H\n+#include <linux/atomic.h>\n+#include <linux/idr.h>\n+#include <asm/vas.h>\n+\n+/*\n+ * Overview of Virtual Accelerator Switchboard (VAS).\n+ *\n+ * VAS is a hardware \"switchboard\" that allows senders and receivers to\n+ * exchange messages with _minimal_ kernel involvment. The receivers are\n+ * typically NX coprocessor engines that perform compression or encryption\n+ * in hardware, but receivers can also be other software threads.\n+ *\n+ * Senders are user/kernel threads that submit compression/encryption or\n+ * other requests to the receivers. Senders must format their messages as\n+ * Coprocessor Request Blocks (CRB)s and submit them using the \"copy\" and\n+ * \"paste\" instructions which were introduced in Power9.\n+ *\n+ * A Power node can have (upto?) 8 Power chips. There is one instance of\n+ * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports,\n+ * Senders and receivers must each connect to a separate window before they\n+ * can exchange messages through the switchboard.\n+ *\n+ * Each window is described by two types of window contexts:\n+ *\n+ *\tHypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes\n+ *\n+ *\tOS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.\n+ *\n+ * A window context can be viewed as a set of 64-bit registers. The settings\n+ * in these registers configure/control/determine the behavior of the VAS\n+ * hardware when messages are sent/received through the window. The registers\n+ * in the HVWC are configured by the kernel while the registers in the UWC can\n+ * be configured by the kernel or by the user space application that is using\n+ * the window.\n+ *\n+ * The HVWCs for all windows on a specific instance of VAS are in a contiguous\n+ * range of hardware addresses or Base address region (BAR) referred to as the\n+ * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance\n+ * are referred to as the UWC BAR for the instance.\n+ *\n+ * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet\n+ * and available to the kernel in the VAS node's \"reg\" property in the device\n+ * tree:\n+ *\n+ *\t/proc/device-tree/vasm@.../reg\n+ *\n+ * (see vas_probe() for details on the reg property).\n+ *\n+ * The kernel maps the HVWC and UWC BAR regions into the kernel address\n+ * space (hvwc_map and uwc_map). The kernel can then access the window\n+ * contexts of a specific window using:\n+ *\n+ *\t hvwc = hvwc_map + winid * VAS_HVWC_SIZE.\n+ *\t uwc = uwc_map + winid * VAS_UWC_SIZE.\n+ *\n+ * where winid is the window index (0..64K).\n+ *\n+ * As mentioned, a window context is used to \"configure\" a window. Besides\n+ * this configuration address, each _send_ window also has a unique hardware\n+ * \"paste\" address that is used to submit requests/CRBs (see vas_paste_crb()).\n+ *\n+ * The hardware paste address for a window is computed using the \"paste\n+ * base address\" and \"paste win id shift\" reg properties in the VAS device\n+ * tree node using:\n+ *\n+ *\tpaste_addr = paste_base + ((winid << paste_win_id_shift))\n+ *\n+ * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift).\n+ *\n+ * The kernel maps this hardware address into the sender's address space\n+ * after which they can use the 'paste' instruction (new in Power9) to\n+ * send a message (submit a request aka CRB) to the coprocessor.\n+ *\n+ * NOTE: In the initial version, senders can only in-kernel drivers/threads.\n+ *\t Support for user space threads will be added in follow-on patches.\n+ *\n+ * TODO: Do we need to map the UWC into user address space so they can return\n+ *\t credits? Its NA for NX but may be needed for other receive windows.\n+ *\n+ */\n+\n+#define VAS_WINDOWS_PER_CHIP\t\t(64 << 10)\n+\n+/*\n+ * Hypervisor and OS/USer Window Context sizes\n+ */\n+#define VAS_HVWC_SIZE\t\t\t512\n+#define VAS_UWC_SIZE\t\t\tPAGE_SIZE\n+\n+/*\n+ * Initial per-process credits.\n+ * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED)\n+ * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED)\n+ *\n+ * TODO: Needs tuning for per-process credits\n+ */\n+#define VAS_WCREDS_MIN\t\t\t16\n+#define VAS_WCREDS_MAX\t\t\t((64 << 10) - 1)\n+#define VAS_WCREDS_DEFAULT\t\t(1 << 10)\n+\n+/*\n+ * VAS Window Context Register Offsets and bitmasks.\n+ * See Section 3.1.4 of VAS Work book\n+ */\n+#define VAS_LPID_OFFSET\t\t\t0x010\n+#define VAS_LPID\t\t\tPPC_BITMASK(0, 11)\n+\n+#define VAS_PID_OFFSET\t\t\t0x018\n+#define VAS_PID_ID\t\t\tPPC_BITMASK(0, 19)\n+\n+#define VAS_XLATE_MSR_OFFSET\t\t0x020\n+#define VAS_XLATE_MSR_DR\t\tPPC_BIT(0)\n+#define VAS_XLATE_MSR_TA\t\tPPC_BIT(1)\n+#define VAS_XLATE_MSR_PR\t\tPPC_BIT(2)\n+#define VAS_XLATE_MSR_US\t\tPPC_BIT(3)\n+#define VAS_XLATE_MSR_HV\t\tPPC_BIT(4)\n+#define VAS_XLATE_MSR_SF\t\tPPC_BIT(5)\n+\n+#define VAS_XLATE_LPCR_OFFSET\t\t0x028\n+#define VAS_XLATE_LPCR_PAGE_SIZE\tPPC_BITMASK(0, 2)\n+#define VAS_XLATE_LPCR_ISL\t\tPPC_BIT(3)\n+#define VAS_XLATE_LPCR_TC\t\tPPC_BIT(4)\n+#define VAS_XLATE_LPCR_SC\t\tPPC_BIT(5)\n+\n+#define VAS_XLATE_CTL_OFFSET\t\t0x030\n+#define VAS_XLATE_MODE\t\t\tPPC_BITMASK(0, 1)\n+\n+#define VAS_AMR_OFFSET\t\t\t0x040\n+#define VAS_AMR\t\t\t\tPPC_BITMASK(0, 63)\n+\n+#define VAS_SEIDR_OFFSET\t\t0x048\n+#define VAS_SEIDR\t\t\tPPC_BITMASK(0, 63)\n+\n+#define VAS_FAULT_TX_WIN_OFFSET\t\t0x050\n+#define VAS_FAULT_TX_WIN\t\tPPC_BITMASK(48, 63)\n+\n+#define VAS_OSU_INTR_SRC_RA_OFFSET\t0x060\n+#define VAS_OSU_INTR_SRC_RA\t\tPPC_BITMASK(8, 63)\n+\n+#define VAS_HV_INTR_SRC_RA_OFFSET\t0x070\n+#define VAS_HV_INTR_SRC_RA\t\tPPC_BITMASK(8, 63)\n+\n+#define VAS_PSWID_OFFSET\t\t0x078\n+#define VAS_PSWID_EA_HANDLE\t\tPPC_BITMASK(0, 31)\n+\n+#define VAS_SPARE1_OFFSET\t\t0x080\n+#define VAS_SPARE2_OFFSET\t\t0x088\n+#define VAS_SPARE3_OFFSET\t\t0x090\n+#define VAS_SPARE4_OFFSET\t\t0x130\n+#define VAS_SPARE5_OFFSET\t\t0x160\n+#define VAS_SPARE6_OFFSET\t\t0x188\n+\n+#define VAS_LFIFO_BAR_OFFSET\t\t0x0A0\n+#define VAS_LFIFO_BAR\t\t\tPPC_BITMASK(8, 53)\n+#define VAS_PAGE_MIGRATION_SELECT\tPPC_BITMASK(54, 56)\n+\n+#define VAS_LDATA_STAMP_CTL_OFFSET\t0x0A8\n+#define VAS_LDATA_STAMP\t\t\tPPC_BITMASK(0, 1)\n+#define VAS_XTRA_WRITE\t\t\tPPC_BIT(2)\n+\n+#define VAS_LDMA_CACHE_CTL_OFFSET\t0x0B0\n+#define VAS_LDMA_TYPE\t\t\tPPC_BITMASK(0, 1)\n+#define VAS_LDMA_FIFO_DISABLE\t\tPPC_BIT(2)\n+\n+#define VAS_LRFIFO_PUSH_OFFSET\t\t0x0B8\n+#define VAS_LRFIFO_PUSH\t\t\tPPC_BITMASK(0, 15)\n+\n+#define VAS_CURR_MSG_COUNT_OFFSET\t0x0C0\n+#define VAS_CURR_MSG_COUNT\t\tPPC_BITMASK(0, 7)\n+\n+#define VAS_LNOTIFY_AFTER_COUNT_OFFSET\t0x0C8\n+#define VAS_LNOTIFY_AFTER_COUNT\t\tPPC_BITMASK(0, 7)\n+\n+#define VAS_LRX_WCRED_OFFSET\t\t0x0E0\n+#define VAS_LRX_WCRED\t\t\tPPC_BITMASK(0, 15)\n+\n+#define VAS_LRX_WCRED_ADDER_OFFSET\t0x190\n+#define VAS_LRX_WCRED_ADDER\t\tPPC_BITMASK(0, 15)\n+\n+#define VAS_TX_WCRED_OFFSET\t\t0x0F0\n+#define VAS_TX_WCRED\t\t\tPPC_BITMASK(4, 15)\n+\n+#define VAS_TX_WCRED_ADDER_OFFSET\t0x1A0\n+#define VAS_TX_WCRED_ADDER\t\tPPC_BITMASK(4, 15)\n+\n+#define VAS_LFIFO_SIZE_OFFSET\t\t0x100\n+#define VAS_LFIFO_SIZE\t\t\tPPC_BITMASK(0, 3)\n+\n+#define VAS_WINCTL_OFFSET\t\t0x108\n+#define VAS_WINCTL_OPEN\t\t\tPPC_BIT(0)\n+#define VAS_WINCTL_REJ_NO_CREDIT\tPPC_BIT(1)\n+#define VAS_WINCTL_PIN\t\t\tPPC_BIT(2)\n+#define VAS_WINCTL_TX_WCRED_MODE\tPPC_BIT(3)\n+#define VAS_WINCTL_RX_WCRED_MODE\tPPC_BIT(4)\n+#define VAS_WINCTL_TX_WORD_MODE\t\tPPC_BIT(5)\n+#define VAS_WINCTL_RX_WORD_MODE\t\tPPC_BIT(6)\n+#define VAS_WINCTL_RSVD_TXBUF\t\tPPC_BIT(7)\n+#define VAS_WINCTL_THRESH_CTL\t\tPPC_BITMASK(8, 9)\n+#define VAS_WINCTL_FAULT_WIN\t\tPPC_BIT(10)\n+#define VAS_WINCTL_NX_WIN\t\tPPC_BIT(11)\n+\n+#define VAS_WIN_STATUS_OFFSET\t\t0x110\n+#define VAS_WIN_BUSY\t\t\tPPC_BIT(1)\n+\n+#define VAS_WIN_CTX_CACHING_CTL_OFFSET\t0x118\n+#define VAS_CASTOUT_REQ\t\t\tPPC_BIT(0)\n+#define VAS_PUSH_TO_MEM\t\t\tPPC_BIT(1)\n+#define VAS_WIN_CACHE_STATUS\t\tPPC_BIT(4)\n+\n+#define VAS_TX_RSVD_BUF_COUNT_OFFSET\t0x120\n+#define VAS_RXVD_BUF_COUNT\t\tPPC_BITMASK(58, 63)\n+\n+#define VAS_LRFIFO_WIN_PTR_OFFSET\t0x128\n+#define VAS_LRX_WIN_ID\t\t\tPPC_BITMASK(0, 15)\n+\n+/*\n+ * Local Notification Control Register controls what happens in _response_\n+ * to a paste command and hence applies only to receive windows.\n+ */\n+#define VAS_LNOTIFY_CTL_OFFSET\t\t0x138\n+#define VAS_NOTIFY_DISABLE\t\tPPC_BIT(0)\n+#define VAS_INTR_DISABLE\t\tPPC_BIT(1)\n+#define VAS_NOTIFY_EARLY\t\tPPC_BIT(2)\n+#define VAS_NOTIFY_OSU_INTR\t\tPPC_BIT(3)\n+\n+#define VAS_LNOTIFY_PID_OFFSET\t\t0x140\n+#define VAS_LNOTIFY_PID\t\t\tPPC_BITMASK(0, 19)\n+\n+#define VAS_LNOTIFY_LPID_OFFSET\t\t0x148\n+#define VAS_LNOTIFY_LPID\t\tPPC_BITMASK(0, 11)\n+\n+#define VAS_LNOTIFY_TID_OFFSET\t\t0x150\n+#define VAS_LNOTIFY_TID\t\t\tPPC_BITMASK(0, 15)\n+\n+#define VAS_LNOTIFY_SCOPE_OFFSET\t0x158\n+#define VAS_LNOTIFY_MIN_SCOPE\t\tPPC_BITMASK(0, 1)\n+#define VAS_LNOTIFY_MAX_SCOPE\t\tPPC_BITMASK(2, 3)\n+\n+#define VAS_NX_UTIL_OFFSET\t\t0x1B0\n+#define VAS_NX_UTIL\t\t\tPPC_BITMASK(0, 63)\n+\n+/* SE: Side effects */\n+#define VAS_NX_UTIL_SE_OFFSET\t\t0x1B8\n+#define VAS_NX_UTIL_SE\t\t\tPPC_BITMASK(0, 63)\n+\n+#define VAS_NX_UTIL_ADDER_OFFSET\t0x180\n+#define VAS_NX_UTIL_ADDER\t\tPPC_BITMASK(32, 63)\n+\n+/*\n+ * Local Notify Scope Control Register. (Receive windows only).\n+ */\n+enum vas_notify_scope {\n+\tVAS_SCOPE_LOCAL,\n+\tVAS_SCOPE_GROUP,\n+\tVAS_SCOPE_VECTORED_GROUP,\n+\tVAS_SCOPE_UNUSED,\n+};\n+\n+/*\n+ * Local DMA Cache Control Register (Receive windows only).\n+ */\n+enum vas_dma_type {\n+\tVAS_DMA_TYPE_INJECT,\n+\tVAS_DMA_TYPE_WRITE,\n+};\n+\n+/*\n+ * Local Notify Scope Control Register. (Receive windows only).\n+ * Not applicable to NX receive windows.\n+ */\n+enum vas_notify_after_count {\n+\tVAS_NOTIFY_AFTER_256 = 0,\n+\tVAS_NOTIFY_NONE,\n+\tVAS_NOTIFY_AFTER_2\n+};\n+\n+/*\n+ * One per instance of VAS. Each instance will have a separate set of\n+ * receive windows, one per coprocessor type.\n+ */\n+struct vas_instance {\n+\tint vas_id;\n+\tstruct ida ida;\n+\tstruct list_head node;\n+\tstruct platform_device *pdev;\n+\n+\tu64 hvwc_bar_start;\n+\tu64 uwc_bar_start;\n+\tu64 paste_base_addr;\n+\tu64 paste_win_id_shift;\n+\n+\tstruct mutex mutex;\n+\tstruct vas_window *rxwin[VAS_COP_TYPE_MAX];\n+\tstruct vas_window *windows[VAS_WINDOWS_PER_CHIP];\n+};\n+\n+/*\n+ * In-kernel state a VAS window. One per window.\n+ */\n+struct vas_window {\n+\t/* Fields common to send and receive windows */\n+\tstruct vas_instance *vinst;\n+\tint winid;\n+\tbool tx_win;\t\t/* True if send window */\n+\tbool nx_win;\t\t/* True if NX window */\n+\tbool user_win;\t\t/* True if user space window */\n+\tvoid *hvwc_map;\t\t/* HV window context */\n+\tvoid *uwc_map;\t\t/* OS/User window context */\n+\tpid_t pid;\t\t/* Linux process id of owner */\n+\n+\t/* Fields applicable only to send windows */\n+\tvoid *paste_kaddr;\n+\tchar *paste_addr_name;\n+\tstruct vas_window *rxwin;\n+\n+\t/* Feilds applicable only to receive windows */\n+\tenum vas_cop_type cop;\n+\tatomic_t num_txwins;\n+};\n+\n+/*\n+ * Container for the hardware state of a window. One per-window.\n+ *\n+ * A VAS Window context is a 512-byte area in the hardware that contains\n+ * a set of 64-bit registers. Individual bit-fields in these registers\n+ * determine the configuration/operation of the hardware. struct vas_winctx\n+ * is a container for the register fields in the window context.\n+ */\n+struct vas_winctx {\n+\tvoid *rx_fifo;\n+\tint rx_fifo_size;\n+\tint wcreds_max;\n+\tint rsvd_txbuf_count;\n+\n+\tbool user_win;\n+\tbool nx_win;\n+\tbool fault_win;\n+\tbool rsvd_txbuf_enable;\n+\tbool pin_win;\n+\tbool rej_no_credit;\n+\tbool tx_wcred_mode;\n+\tbool rx_wcred_mode;\n+\tbool tx_word_mode;\n+\tbool rx_word_mode;\n+\tbool data_stamp;\n+\tbool xtra_write;\n+\tbool notify_disable;\n+\tbool intr_disable;\n+\tbool fifo_disable;\n+\tbool notify_early;\n+\tbool notify_os_intr_reg;\n+\n+\tint lpid;\n+\tint pidr;\t\t/* value from SPRN_PID, not linux pid */\n+\tint lnotify_lpid;\n+\tint lnotify_pid;\n+\tint lnotify_tid;\n+\tu32 pswid;\n+\tint rx_win_id;\n+\tint fault_win_id;\n+\tint tc_mode;\n+\n+\tu64 irq_port;\n+\n+\tenum vas_dma_type dma_type;\n+\tenum vas_notify_scope min_scope;\n+\tenum vas_notify_scope max_scope;\n+\tenum vas_notify_after_count notify_after_count;\n+};\n+\n+#endif /* _VAS_H */\n", "prefixes": [ "v8", "01/10" ] }