Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/806947/?format=api
{ "id": 806947, "url": "http://patchwork.ozlabs.org/api/patches/806947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503976853-3029-4-git-send-email-yamada.masahiro@socionext.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503976853-3029-4-git-send-email-yamada.masahiro@socionext.com>", "list_archive_url": null, "date": "2017-08-29T03:20:53", "name": "[U-Boot,4/4] ARM: dts: uniphier: update PXs3 SoC/board DT", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "39c5e76c2b6760f0dcd4b9814d090f60a07b4a2e", "submitter": { "id": 65882, "url": "http://patchwork.ozlabs.org/api/people/65882/?format=api", "name": "Masahiro Yamada", "email": "yamada.masahiro@socionext.com" }, "delegate": { "id": 38701, "url": "http://patchwork.ozlabs.org/api/users/38701/?format=api", "username": "masahir0y", "first_name": "Masahiro", "last_name": "Yamada", "email": "yamada.m@jp.panasonic.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503976853-3029-4-git-send-email-yamada.masahiro@socionext.com/mbox/", "series": [ { "id": 294, "url": "http://patchwork.ozlabs.org/api/series/294/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=294", "date": "2017-08-29T03:20:51", "name": "[U-Boot,1/4] reset: uniphier: fix compatible for SD reset node for LD11/LD20", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/294/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806947/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806947/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"BREXrZcD\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhGtN1R1Zz9t1G\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 15:10:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 11668C21E2F; Tue, 29 Aug 2017 03:35:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id ACAB8C22620;\n\tTue, 29 Aug 2017 03:35:24 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 17412C220CE; Tue, 29 Aug 2017 03:21:17 +0000 (UTC)", "from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74])\n\tby lists.denx.de (Postfix) with ESMTPS id 91C68C22690\n\tfor <u-boot@lists.denx.de>; Tue, 29 Aug 2017 03:21:15 +0000 (UTC)", "from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp\n\t[153.142.97.92]) (authenticated)\n\tby conuserg-07.nifty.com with ESMTP id v7T3KuI4005509;\n\tTue, 29 Aug 2017 12:20:58 +0900" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Filter": "OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v7T3KuI4005509", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1503976858;\n\tbh=6gPW1MC1fomrNiY+TXNveLge0GLYmJLVggVXvmCJ1MQ=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=BREXrZcDVCdrCh4QKe4Xst7TEDqWCTFulijDWPieU5BzmoVIhOIh4znHYR3viSdnm\n\t1fAK8LfUz66W60u7LtCo15jo8/WAS0jXlJQ0dkejm8QmHuZkpOZ2qbZzvwgcxnqCyp\n\tQyM7J+kjggyk5mnx47h7yidxXQY/3JNZH38/YorOad6CImqLWNrwalBn3U9X72Esnd\n\tTtR5/sinyMgr8pmtHbIaJOf0dnD+fdggrQJelfAg9qEaVz7vb+7lsqP5LZkl3m8WNp\n\taWEctiGtN2uM/Vv7/7cxfJABno7ue6nNVIlHwWAbJGoVhNiuIO9G3ZesohHr925vi9\n\t+kkTfpC6Mb2fQ==", "X-Nifty-SrcIP": "[153.142.97.92]", "From": "Masahiro Yamada <yamada.masahiro@socionext.com>", "To": "u-boot@lists.denx.de", "Date": "Tue, 29 Aug 2017 12:20:53 +0900", "Message-Id": "<1503976853-3029-4-git-send-email-yamada.masahiro@socionext.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1503976853-3029-1-git-send-email-yamada.masahiro@socionext.com>", "References": "<1503976853-3029-1-git-send-email-yamada.masahiro@socionext.com>", "Cc": "Albert Aribaud <albert.u.boot@aribaud.net>", "Subject": "[U-Boot] [PATCH 4/4] ARM: dts: uniphier: update PXs3 SoC/board DT", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Support PXs3 SoC and its reference development board.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n\n arch/arm/dts/uniphier-pxs3-ref.dts | 21 ++++--\n arch/arm/dts/uniphier-pxs3.dtsi | 127 ++++++++++++++++++++++++-------------\n 2 files changed, 98 insertions(+), 50 deletions(-)", "diff": "diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts\nindex cb1eef43c464..d65f746a3f9d 100644\n--- a/arch/arm/dts/uniphier-pxs3-ref.dts\n+++ b/arch/arm/dts/uniphier-pxs3-ref.dts\n@@ -4,13 +4,12 @@\n * Copyright (C) 2017 Socionext Inc.\n * Author: Masahiro Yamada <yamada.masahiro@socionext.com>\n *\n- * SPDX-License-Identifier:\tGPL-2.0+\tX11\n+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n */\n \n /dts-v1/;\n-/include/ \"uniphier-pxs3.dtsi\"\n-/include/ \"uniphier-ref-daughter.dtsi\"\n-/include/ \"uniphier-support-card.dtsi\"\n+#include \"uniphier-pxs3.dtsi\"\n+#include \"uniphier-support-card.dtsi\"\n \n / {\n \tmodel = \"UniPhier PXs3 Reference Board\";\n@@ -39,7 +38,7 @@\n };\n \n ðsc {\n-\tinterrupts = <0 48 4>;\n+\tinterrupts = <0 52 4>;\n };\n \n &serial0 {\n@@ -49,3 +48,15 @@\n &i2c0 {\n \tstatus = \"okay\";\n };\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi\nindex cdf7f9005f73..8615ba0bc771 100644\n--- a/arch/arm/dts/uniphier-pxs3.dtsi\n+++ b/arch/arm/dts/uniphier-pxs3.dtsi\n@@ -4,46 +4,10 @@\n * Copyright (C) 2017 Socionext Inc.\n * Author: Masahiro Yamada <yamada.masahiro@socionext.com>\n *\n- * This file is dual-licensed: you can use it either under the terms\n- * of the GPL or the X11 license, at your option. Note that this dual\n- * licensing only applies to this file, and not this project as a\n- * whole.\n- *\n- * a) This file is free software; you can redistribute it and/or\n- * modify it under the terms of the GNU General Public License as\n- * published by the Free Software Foundation; either version 2 of the\n- * License, or (at your option) any later version.\n- *\n- * This file is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n- * GNU General Public License for more details.\n- *\n- * Or, alternatively,\n- *\n- * b) Permission is hereby granted, free of charge, to any person\n- * obtaining a copy of this software and associated documentation\n- * files (the \"Software\"), to deal in the Software without\n- * restriction, including without limitation the rights to use,\n- * copy, modify, merge, publish, distribute, sublicense, and/or\n- * sell copies of the Software, and to permit persons to whom the\n- * Software is furnished to do so, subject to the following\n- * conditions:\n- *\n- * The above copyright notice and this permission notice shall be\n- * included in all copies or substantial portions of the Software.\n- *\n- * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n- * OTHER DEALINGS IN THE SOFTWARE.\n+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n */\n \n-/memreserve/ 0x80000000 0x00080000;\n+/memreserve/ 0x80000000 0x02000000;\n \n / {\n \tcompatible = \"socionext,uniphier-pxs3\";\n@@ -76,28 +40,74 @@\n \t\t\tdevice_type = \"cpu\";\n \t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n \t\t\treg = <0 0x000>;\n+\t\t\tclocks = <&sys_clk 33>;\n \t\t\tenable-method = \"psci\";\n+\t\t\toperating-points-v2 = <&cluster0_opp>;\n \t\t};\n \n \t\tcpu1: cpu@1 {\n \t\t\tdevice_type = \"cpu\";\n \t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n \t\t\treg = <0 0x001>;\n+\t\t\tclocks = <&sys_clk 33>;\n \t\t\tenable-method = \"psci\";\n+\t\t\toperating-points-v2 = <&cluster0_opp>;\n \t\t};\n \n \t\tcpu2: cpu@2 {\n \t\t\tdevice_type = \"cpu\";\n \t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n \t\t\treg = <0 0x002>;\n+\t\t\tclocks = <&sys_clk 33>;\n \t\t\tenable-method = \"psci\";\n+\t\t\toperating-points-v2 = <&cluster0_opp>;\n \t\t};\n \n \t\tcpu3: cpu@3 {\n \t\t\tdevice_type = \"cpu\";\n \t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n \t\t\treg = <0 0x003>;\n+\t\t\tclocks = <&sys_clk 33>;\n \t\t\tenable-method = \"psci\";\n+\t\t\toperating-points-v2 = <&cluster0_opp>;\n+\t\t};\n+\t};\n+\n+\tcluster0_opp: opp_table {\n+\t\tcompatible = \"operating-points-v2\";\n+\t\topp-shared;\n+\n+\t\topp-250000000 {\n+\t\t\topp-hz = /bits/ 64 <250000000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-325000000 {\n+\t\t\topp-hz = /bits/ 64 <325000000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-500000000 {\n+\t\t\topp-hz = /bits/ 64 <500000000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-650000000 {\n+\t\t\topp-hz = /bits/ 64 <650000000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-666667000 {\n+\t\t\topp-hz = /bits/ 64 <666667000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-866667000 {\n+\t\t\topp-hz = /bits/ 64 <866667000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\tclock-latency-ns = <300>;\n+\t\t};\n+\t\topp-1300000000 {\n+\t\t\topp-hz = /bits/ 64 <1300000000>;\n+\t\t\tclock-latency-ns = <300>;\n \t\t};\n \t};\n \n@@ -172,6 +182,22 @@\n \t\t\tclock-frequency = <58820000>;\n \t\t};\n \n+\t\tgpio: gpio@55000000 {\n+\t\t\tcompatible = \"socionext,uniphier-pxs3-gpio\";\n+\t\t\treg = <0x55000000 0x200>;\n+\t\t\tinterrupt-parent = <&aidet>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&pinctrl 0 0 0>,\n+\t\t\t\t <&pinctrl 96 0 0>,\n+\t\t\t\t <&pinctrl 160 0 0>;\n+\t\t\tgpio-ranges-group-names = \"gpio_range0\",\n+\t\t\t\t\t\t \"gpio_range1\",\n+\t\t\t\t\t\t \"gpio_range2\";\n+\t\t};\n+\n \t\ti2c0: i2c@58780000 {\n \t\t\tcompatible = \"socionext,uniphier-fi2c\";\n \t\t\tstatus = \"disabled\";\n@@ -205,6 +231,8 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n \t\t\tinterrupts = <0 43 4>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_i2c2>;\n \t\t\tclocks = <&peri_clk 6>;\n \t\t\tclock-frequency = <100000>;\n \t\t};\n@@ -251,7 +279,7 @@\n \t\tsdctrl@59810000 {\n \t\t\tcompatible = \"socionext,uniphier-pxs3-sdctrl\",\n \t\t\t\t \"simple-mfd\", \"syscon\";\n-\t\t\treg = <0x59810000 0x800>;\n+\t\t\treg = <0x59810000 0x400>;\n \n \t\t\tsd_clk: clock {\n \t\t\t\tcompatible = \"socionext,uniphier-pxs3-sd-clock\";\n@@ -282,7 +310,6 @@\n \n \t\temmc: sdhc@5a000000 {\n \t\t\tcompatible = \"socionext,uniphier-sd4hc\", \"cdns,sd4hc\";\n-\t\t\tstatus = \"disabled\";\n \t\t\treg = <0x5a000000 0x400>;\n \t\t\tinterrupts = <0 78 4>;\n \t\t\tpinctrl-names = \"default\";\n@@ -291,6 +318,11 @@\n \t\t\tbus-width = <8>;\n \t\t\tmmc-ddr-1_8v;\n \t\t\tmmc-hs200-1_8v;\n+\t\t\tcdns,phy-input-delay-legacy = <4>;\n+\t\t\tcdns,phy-input-delay-mmc-highspeed = <2>;\n+\t\t\tcdns,phy-input-delay-mmc-ddr = <3>;\n+\t\t\tcdns,phy-dll-delay-sdclk = <21>;\n+\t\t\tcdns,phy-dll-delay-sdclk-hsmmc = <21>;\n \t\t};\n \n \t\tsd: sdhc@5a400000 {\n@@ -317,9 +349,11 @@\n \t\t\t};\n \t\t};\n \n-\t\taidet@5fc20000 {\n-\t\t\tcompatible = \"simple-mfd\", \"syscon\";\n+\t\taidet: aidet@5fc20000 {\n+\t\t\tcompatible = \"socionext,uniphier-pxs3-aidet\";\n \t\t\treg = <0x5fc20000 0x200>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n \t\t};\n \n \t\tgic: interrupt-controller@5fe00000 {\n@@ -345,10 +379,14 @@\n \t\t\t\tcompatible = \"socionext,uniphier-pxs3-reset\";\n \t\t\t\t#reset-cells = <1>;\n \t\t\t};\n+\n+\t\t\twatchdog {\n+\t\t\t\tcompatible = \"socionext,uniphier-wdt\";\n+\t\t\t};\n \t\t};\n \n \t\tnand: nand@68000000 {\n-\t\t\tcompatible = \"socionext,denali-nand-v5b\";\n+\t\t\tcompatible = \"socionext,uniphier-denali-nand-v5b\";\n \t\t\tstatus = \"disabled\";\n \t\t\treg-names = \"nand_data\", \"denali_reg\";\n \t\t\treg = <0x68000000 0x20>, <0x68100000 0x1000>;\n@@ -356,9 +394,8 @@\n \t\t\tpinctrl-names = \"default\";\n \t\t\tpinctrl-0 = <&pinctrl_nand>;\n \t\t\tclocks = <&sys_clk 2>;\n-\t\t\tnand-ecc-strength = <8>;\n \t\t};\n \t};\n };\n \n-/include/ \"uniphier-pinctrl.dtsi\"\n+#include \"uniphier-pinctrl.dtsi\"\n", "prefixes": [ "U-Boot", "4/4" ] }