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GET /api/patches/806767/?format=api
{ "id": 806767, "url": "http://patchwork.ozlabs.org/api/patches/806767/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1503954854-30963-2-git-send-email-mw@semihalf.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503954854-30963-2-git-send-email-mw@semihalf.com>", "list_archive_url": null, "date": "2017-08-28T21:14:13", "name": "[1/2] mtd: spi-nor: add an option to force 3byte adressing mode", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": false, "hash": "4acfa45ba4ef418fb5ccf4f31f89d9af893a4f35", "submitter": { "id": 66998, "url": "http://patchwork.ozlabs.org/api/people/66998/?format=api", "name": "Marcin Wojtas", "email": "mw@semihalf.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1503954854-30963-2-git-send-email-mw@semihalf.com/mbox/", "series": [ { "id": 259, "url": "http://patchwork.ozlabs.org/api/series/259/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=259", "date": "2017-08-28T21:14:12", "name": "SPI NOR - force 3byte addressing mode", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/259/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806767/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806767/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Hitherto code set 4B addressing mode for all SPI flashes whose\nsize exceeds 16MB. However, changing the default 3B access\nin some cases may be harmful - it may happen that the Boot ROM\nis not capable of handling non-default state of the SPI NOR\n(e.g. after soft reset). Some flash devices allow to access the\nmemory above 128Mib without changing mode to 4byte thanks\nto special op codes (see SPI_NOR_4B_OPCODES flag). Unfortunately\nfor those which don't support them, the problem persists.\n\nThis patch adds optional property that can be added to the\nSPI flash node and which will force to use 3B addressing mode,\nlimiting the accessible memory size to 16MiB.\nBinding documentation is updated accordingly.\n\nSigned-off-by: Marcin Wojtas <mw@semihalf.com>\n---\n Documentation/devicetree/bindings/spi/spi-bus.txt | 2 ++\n drivers/mtd/spi-nor/spi-nor.c | 12 +++++++++++-\n 2 files changed, 13 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt\nindex 1f6e86f..f13b773 100644\n--- a/Documentation/devicetree/bindings/spi/spi-bus.txt\n+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt\n@@ -77,6 +77,8 @@ All slave nodes can contain the following optional properties:\n \t\t Defaults to 1 if not present.\n - spi-rx-delay-us - Microsecond delay after a read transfer.\n - spi-tx-delay-us - Microsecond delay after a write transfer.\n+- spi-3byte-addressing - Empty property indicating device access to be done\n+\t\t only in 3byte addressing mode.\n \n Some SPI controllers and devices support Dual and Quad SPI transfer mode.\n It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4\ndiff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c\nindex 1413828..029c87d 100644\n--- a/drivers/mtd/spi-nor/spi-nor.c\n+++ b/drivers/mtd/spi-nor/spi-nor.c\n@@ -2002,7 +2002,17 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,\n \t\tif (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||\n \t\t info->flags & SPI_NOR_4B_OPCODES)\n \t\t\tspi_nor_set_4byte_opcodes(nor, info);\n-\t\telse\n+\t\telse if (of_property_read_bool(np, \"spi-3byte-addressing\")) {\n+\t\t\t/*\n+\t\t\t * Do not enter 4byte mode in order to prevent\n+\t\t\t * the early bootloader to come up on non-default\n+\t\t\t * SPI NOR memory during boot. Limit accessible\n+\t\t\t * size to 16MiB.\n+\t\t\t */\n+\t\t\tnor->addr_width = 3;\n+\t\t\tmtd->size = 0x1000000;\n+\t\t\tdev_info(dev, \"Force 3B addressing mode\\n\");\n+\t\t} else\n \t\t\tset_4byte(nor, info, 1);\n \t} else {\n \t\tnor->addr_width = 3;\n", "prefixes": [ "1/2" ] }