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GET /api/patches/806705/?format=api
{ "id": 806705, "url": "http://patchwork.ozlabs.org/api/patches/806705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828180437.2646-3-ard.biesheuvel@linaro.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828180437.2646-3-ard.biesheuvel@linaro.org>", "list_archive_url": null, "date": "2017-08-28T18:04:37", "name": "[v3,2/2] dt-bindings: designware: add binding for Designware PCIe in ECAM mode", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6717ebb557cfa5197ae702095b2a0db7d1d2a6d2", "submitter": { "id": 26857, "url": "http://patchwork.ozlabs.org/api/people/26857/?format=api", "name": "Ard Biesheuvel", "email": "ard.biesheuvel@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828180437.2646-3-ard.biesheuvel@linaro.org/mbox/", "series": [ { "id": 229, "url": "http://patchwork.ozlabs.org/api/series/229/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=229", "date": "2017-08-28T18:04:35", "name": "pci: add support for firmware initialized designware RCs", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/229/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806705/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"hBy4o9Me\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xh06G61qxz9sP5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 04:04:54 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751271AbdH1SEw (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 14:04:52 -0400", "from mail-wr0-f172.google.com ([209.85.128.172]:35657 \"EHLO\n\tmail-wr0-f172.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751232AbdH1SEv (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 14:04:51 -0400", "by mail-wr0-f172.google.com with SMTP id j29so2903299wre.2\n\tfor <linux-pci@vger.kernel.org>; Mon, 28 Aug 2017 11:04:51 -0700 (PDT)", "from localhost.localdomain ([105.133.189.215])\n\tby smtp.gmail.com with ESMTPSA id\n\ti22sm1335922wrf.18.2017.08.28.11.04.47\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 28 Aug 2017 11:04:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=JicZgUtJKFKCyCXsainIVAsegpoGPs4jV0M0QQ1q6CU=;\n\tb=hBy4o9Meg9ovo9OqqGd1b4GnqjxS5bpOKl4yFvrobMda5X9dlKgzl5LbOcWXcfeXjE\n\tSWfj2G5M3Y8W/sLpWA5Z3Pp2jonkvvjWD15eUObXahtF+UziefEB0GsyZtAF7XmRez8J\n\tizCDys33Ln0SfZ1L+HGjrBgfuZ9tQfkn0uPp4=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=JicZgUtJKFKCyCXsainIVAsegpoGPs4jV0M0QQ1q6CU=;\n\tb=PJiIoHAGVHZd4BL8bAD/VPY/juR+Umrk1m4Jbf6CxE11Dz+b/n7dOpRJAbm60rRn4f\n\tKPdOhEfwTCVz8PZk9ian1r31SV/ogDga2ZWTQKN0cWxkFhHSJkg1fAHXahPCpEj88Vi3\n\tsnKAruUDFSj+UkC/Mbp70659fOFaguu3nZ+POVr17TfKwjn2B9esg1octT4T1j+OUj7u\n\tovohT8SFpEEPC+xgJWcD1wA+xyDVOXw5L9cqItC7A1SAvcuiAXOmeK9YCYomupSeNEZJ\n\t+7bLfWltKF9MC8lY/xdQG4LFUVXasIl5E/hNYMd8tsPV3iHCiXsq7y1add0kMTRwtxiW\n\ti07w==", "X-Gm-Message-State": "AHYfb5gXXzJ56QSQvvANcA/KbOC7T8vlVWk9mgGHcUUKGKniKh04OKsP\n\tAa2TM6Jekx9rXbYD69/c9g==", "X-Received": "by 10.223.174.165 with SMTP id y34mr1048264wrc.184.1503943490307;\n\tMon, 28 Aug 2017 11:04:50 -0700 (PDT)", "From": "Ard Biesheuvel <ard.biesheuvel@linaro.org>", "To": "linux-pci@vger.kernel.org", "Cc": "devicetree@vger.kernel.org, mw@semihalf.com,\n\tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\tLeif Lindholm <leif.lindholm@linaro.org>,\n\tGraeme Gregory <graeme.gregory@linaro.org>,\n\tBjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n\tJoao Pinto <Joao.Pinto@synopsys.com>, Rob Herring <robh@kernel.org>", "Subject": "[PATCH v3 2/2] dt-bindings: designware: add binding for Designware\n\tPCIe in ECAM mode", "Date": "Mon, 28 Aug 2017 19:04:37 +0100", "Message-Id": "<20170828180437.2646-3-ard.biesheuvel@linaro.org>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "References": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Describe the binding for firmware-configured instances of the Synopsys\nDesignware PCIe controller in RC mode, that are almost but not quite\nECAM compliant.\n\nCc: Rob Herring <robh@kernel.org>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\n---\n Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++\n 1 file changed, 42 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt\nnew file mode 100644\nindex 000000000000..29bad1337c87\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt\n@@ -0,0 +1,42 @@\n+* Synopsys Designware PCIe root complex in ECAM mode\n+\n+In some cases, firmware may already have configured the Synopsys Designware\n+PCIe controller in RC mode with static ATU window mappings that cover all\n+config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion.\n+In this case, there is no need for the OS to perform any low level setup\n+of clocks, PHYs or device registers, nor is there any reason for the driver\n+to reconfigure ATU windows for config and/or IO space accesses at runtime.\n+\n+In cases where the IP was synthesized with a minimum ATU window size of\n+64 KB, it cannot be supported by the generic ECAM driver, because it\n+requires special config space accessors that filter accesses to device #1\n+and beyond on the first bus.\n+\n+Required properties:\n+- compatible: \"marvell,armada8k-pcie-ecam\" or\n+ \"socionext,synquacer-pcie-ecam\" or\n+ \"snps,dw-pcie-ecam\" (must be preceded by a more specific match)\n+\n+Please refer to the binding document of \"pci-host-ecam-generic\" in the\n+file host-generic-pci.txt for a description of the remaining required\n+and optional properties.\n+\n+Example:\n+\n+ pcie1: pcie@7f000000 {\n+ compatible = \"socionext,synquacer-pcie-ecam\", \"snps,dw-pcie-ecam\";\n+ device_type = \"pci\";\n+ reg = <0x0 0x7f000000 0x0 0xf00000>;\n+ bus-range = <0x0 0xe>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,\n+ <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,\n+ <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;\n+\n+ #interrupt-cells = <0x1>;\n+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;\n+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;\n+ msi-map = <0x0 &its 0x0 0x10000>;\n+ dma-coherent;\n+ };\n", "prefixes": [ "v3", "2/2" ] }