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GET /api/patches/806703/?format=api
{ "id": 806703, "url": "http://patchwork.ozlabs.org/api/patches/806703/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828180437.2646-2-ard.biesheuvel@linaro.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828180437.2646-2-ard.biesheuvel@linaro.org>", "list_archive_url": null, "date": "2017-08-28T18:04:36", "name": "[v3,1/2] pci: designware: add driver for DWC controller in ECAM shift mode", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "0fdd1ce75752a274cabf6b19597a7c8061be9f6f", "submitter": { "id": 26857, "url": "http://patchwork.ozlabs.org/api/people/26857/?format=api", "name": "Ard Biesheuvel", "email": "ard.biesheuvel@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828180437.2646-2-ard.biesheuvel@linaro.org/mbox/", "series": [ { "id": 229, "url": "http://patchwork.ozlabs.org/api/series/229/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=229", "date": "2017-08-28T18:04:35", "name": "pci: add support for firmware initialized designware RCs", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/229/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806703/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806703/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"ci5B12lV\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xh06D3Yf2z9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 04:04:52 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751161AbdH1SEu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 14:04:50 -0400", "from mail-wr0-f175.google.com ([209.85.128.175]:35648 \"EHLO\n\tmail-wr0-f175.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751182AbdH1SEt (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 14:04:49 -0400", "by mail-wr0-f175.google.com with SMTP id j29so2902979wre.2\n\tfor <linux-pci@vger.kernel.org>; Mon, 28 Aug 2017 11:04:48 -0700 (PDT)", "from localhost.localdomain ([105.133.189.215])\n\tby smtp.gmail.com with ESMTPSA id\n\ti22sm1335922wrf.18.2017.08.28.11.04.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 28 Aug 2017 11:04:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=3wTCZGKm5urtjkZ+N6IJvAGmtQOruHhgXRZsj+N+174=;\n\tb=ci5B12lVF9vjM/da7zdIqQHdxQWJAnVPtStVnclPUbGjTt54RMW8gzCUFF9f/AbOnP\n\tzDf1McCVS1QmE4brKOponnOqYxyp7Rw5018Bp+8er2y5vzdcENvObDWpXTFkbNfyxyPY\n\tQm3Jt2RSIomNa1LwQiRsrO+NB8x4h7/2aHrNY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=3wTCZGKm5urtjkZ+N6IJvAGmtQOruHhgXRZsj+N+174=;\n\tb=NrcgiRlix0Ag4ubTcC/x36+NaGGr6cv2JgBrHp//d38L8Raue4qvWzuZDTA22Rsx8S\n\tW9uUT5Inrhv1H0kQSPBGOPOJvIFGJbumuMZytVmNjslvyYL7Os8kILo+JZ0OU15QfSsz\n\tp+5H7klPZU8afEC8dLSuiN2L3RAc+P5Ib5jJRNU6mB8fazF81rQH/sCbktMCwxNI+2Nf\n\t+SzA33lGd17q0dWbDNmUryTKXlP9PJ5/owFo+hWcx02xhUb9LNelMOcwRKnjMJWL+hjh\n\t7q+euaAf7aRqLF8hh0xPqwa5j48BJAt6PvzsvD+rPaNDLmeL9TAhFq5s91lRS01Lk6gQ\n\t52uA==", "X-Gm-Message-State": "AHYfb5h1QvxmtWYOPXH5jjPLeTxAMfcOE4PK5QfBvUJKdp7Ak5VA9Ptw\n\t/+kEg20ksJeXYwq4Mu0NMQ==", "X-Received": "by 10.223.174.89 with SMTP id u25mr1036918wrd.246.1503943487518; \n\tMon, 28 Aug 2017 11:04:47 -0700 (PDT)", "From": "Ard Biesheuvel <ard.biesheuvel@linaro.org>", "To": "linux-pci@vger.kernel.org", "Cc": "devicetree@vger.kernel.org, mw@semihalf.com,\n\tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\tLeif Lindholm <leif.lindholm@linaro.org>,\n\tGraeme Gregory <graeme.gregory@linaro.org>,\n\tBjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n\tJoao Pinto <Joao.Pinto@synopsys.com>, Rob Herring <robh@kernel.org>", "Subject": "[PATCH v3 1/2] pci: designware: add driver for DWC controller in\n\tECAM shift mode", "Date": "Mon, 28 Aug 2017 19:04:36 +0100", "Message-Id": "<20170828180437.2646-2-ard.biesheuvel@linaro.org>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "References": "<20170828180437.2646-1-ard.biesheuvel@linaro.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Some implementations of the Synopsys Designware PCIe controller implement\na so-called ECAM shift mode, which allows a static memory window to be\nconfigured that covers the configuration space of the entire bus range.\n\nIf the firmware performs all the low level configuration that is required\nto expose this controller in a fully ECAM compatible manner, we can\nsimply describe it as \"pci-host-ecam-generic\" and be done with it.\nHowever, it appears that in some cases (one of which is the Armada 80x0),\nthe IP is synthesized with an ATU window size that does not allow the\nfirst bus to be mapped in a way that prevents the device on the\ndownstream port from appearing more than once.\n\nSo implement a driver that relies on the firmware to perform all low\nlevel initialization, and drives the controller in ECAM mode, but\noverrides the config space accessors to take the above quirk into\naccount.\n\nNote that, unlike most drivers for this IP, this driver does not expose\na fake bridge device at B/D/F 00:00.0. There is no point in doing so,\ngiven that this is not a true bridge, and does not require any windows\nto be configured in order for the downstream device to operate correctly.\nOmitting it also prevents the PCI resource allocation routines from\nhanding out BAR space to it unnecessarily.\n\nCc: Bjorn Helgaas <bhelgaas@google.com>\nCc: Jingoo Han <jingoohan1@gmail.com>\nCc: Joao Pinto <Joao.Pinto@synopsys.com>\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\n---\n drivers/pci/dwc/Kconfig | 11 +++\n drivers/pci/dwc/Makefile | 1 +\n drivers/pci/dwc/pcie-designware-ecam.c | 77 ++++++++++++++++++++\n 3 files changed, 89 insertions(+)", "diff": "diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig\nindex d275aadc47ee..477576d07911 100644\n--- a/drivers/pci/dwc/Kconfig\n+++ b/drivers/pci/dwc/Kconfig\n@@ -169,4 +169,15 @@ config PCIE_KIRIN\n \t Say Y here if you want PCIe controller support\n \t on HiSilicon Kirin series SoCs.\n \n+config PCIE_DW_HOST_ECAM\n+\tbool \"Synopsys DesignWare PCIe controller in ECAM mode\"\n+\tdepends on OF && PCI\n+\tselect PCI_HOST_COMMON\n+\tselect IRQ_DOMAIN\n+\thelp\n+\t Add support for Synopsys DesignWare PCIe controllers configured\n+\t by the firmware into ECAM shift mode. In some cases, these are\n+\t fully ECAM compliant, in which case the pci-host-generic driver\n+\t may be used instead.\n+\n endmenu\ndiff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile\nindex c61be9738cce..7d5a23e5b767 100644\n--- a/drivers/pci/dwc/Makefile\n+++ b/drivers/pci/dwc/Makefile\n@@ -1,5 +1,6 @@\n obj-$(CONFIG_PCIE_DW) += pcie-designware.o\n obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o\n+obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o\n obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o\n obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o\n ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)\ndiff --git a/drivers/pci/dwc/pcie-designware-ecam.c b/drivers/pci/dwc/pcie-designware-ecam.c\nnew file mode 100644\nindex 000000000000..ede627d7d08b\n--- /dev/null\n+++ b/drivers/pci/dwc/pcie-designware-ecam.c\n@@ -0,0 +1,77 @@\n+/*\n+ * Driver for mostly ECAM compatible Synopsys dw PCIe controllers\n+ * configured by the firmware into RC mode\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ * Copyright (C) 2014 ARM Limited\n+ * Copyright (C) 2017 Linaro Limited\n+ *\n+ * Authors: Will Deacon <will.deacon@arm.com>\n+ * Ard Biesheuvel <ard.biesheuvel@linaro.org>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/of_address.h>\n+#include <linux/of_pci.h>\n+#include <linux/pci-ecam.h>\n+#include <linux/platform_device.h>\n+\n+static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where,\n+\t\t\t\t int size, u32 *val)\n+{\n+\tstruct pci_config_window *cfg = bus->sysdata;\n+\n+\t/*\n+\t * The Synopsys dw PCIe controller in RC mode will not filter type 0\n+\t * config TLPs sent to devices 1 and up on its downstream port,\n+\t * resulting in devices appearing multiple times on bus 0 unless we\n+\t * filter them here.\n+\t */\n+\tif (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) {\n+\t\t*val = 0xffffffff;\n+\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n+\t}\n+\treturn pci_generic_config_read(bus, devfn, where, size, val);\n+}\n+\n+static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where,\n+\t\t\t\t int size, u32 val)\n+{\n+\tstruct pci_config_window *cfg = bus->sysdata;\n+\n+\tif (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0)\n+\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n+\n+\treturn pci_generic_config_write(bus, devfn, where, size, val);\n+}\n+\n+static struct pci_ecam_ops pci_dw_ecam_bus_ops = {\n+\t.pci_ops.map_bus\t\t= pci_ecam_map_bus,\n+\t.pci_ops.read\t\t\t= pci_dw_ecam_config_read,\n+\t.pci_ops.write\t\t\t= pci_dw_ecam_config_write,\n+\t.bus_shift\t\t\t= 20,\n+};\n+\n+static const struct of_device_id pci_dw_ecam_of_match[] = {\n+\t{ .compatible = \"marvell,armada8k-pcie-ecam\" },\n+\t{ .compatible = \"socionext,synquacer-pcie-ecam\" },\n+\t{ .compatible = \"snps,dw-pcie-ecam\" },\n+\t{ },\n+};\n+\n+static int pci_dw_ecam_probe(struct platform_device *pdev)\n+{\n+\treturn pci_host_common_probe(pdev, &pci_dw_ecam_bus_ops);\n+}\n+\n+static struct platform_driver pci_dw_ecam_driver = {\n+\t.driver.name\t\t\t= \"pcie-designware-ecam\",\n+\t.driver.of_match_table\t\t= pci_dw_ecam_of_match,\n+\t.driver.suppress_bind_attrs\t= true,\n+\t.probe\t\t\t\t= pci_dw_ecam_probe,\n+};\n+builtin_platform_driver(pci_dw_ecam_driver);\n", "prefixes": [ "v3", "1/2" ] }