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GET /api/patches/806660/?format=api
{ "id": 806660, "url": "http://patchwork.ozlabs.org/api/patches/806660/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com>", "list_archive_url": null, "date": "2017-08-28T16:38:02", "name": "[Qemu,devel,v7,4/5] msf2: Add Smartfusion2 SoC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c09a6e4bd4d602fdd6cd297ce343ec7f1e04b209", "submitter": { "id": 64324, "url": "http://patchwork.ozlabs.org/api/people/64324/?format=api", "name": "sundeep subbaraya", "email": "sundeep.lkml@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com/mbox/", "series": [ { "id": 213, "url": "http://patchwork.ozlabs.org/api/series/213/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=213", "date": "2017-08-28T16:37:58", "name": "Add support for Smartfusion2 SoC", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/213/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806660/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"uKrA93y7\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xgyHS2kMsz9s4q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 02:42:44 +1000 (AEST)", "from localhost ([::1]:40628 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmN7a-0005LM-AX\n\tfor incoming@patchwork.ozlabs.org; Mon, 28 Aug 2017 12:42:42 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:45244)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dmN3Z-00024h-W2\n\tfor qemu-devel@nongnu.org; Mon, 28 Aug 2017 12:38:36 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dmN3V-0003Ww-0F\n\tfor qemu-devel@nongnu.org; Mon, 28 Aug 2017 12:38:34 -0400", "from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:37588)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sundeep.lkml@gmail.com>)\n\tid 1dmN3U-0003Te-Nx; Mon, 28 Aug 2017 12:38:28 -0400", "by mail-pf0-x242.google.com with SMTP id a2so632127pfj.4;\n\tMon, 28 Aug 2017 09:38:28 -0700 (PDT)", "from localhost.localdomain ([124.123.70.3])\n\tby smtp.gmail.com with ESMTPSA id\n\tn66sm1935015pfi.44.2017.08.28.09.38.25\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tMon, 28 Aug 2017 09:38:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=C29pAoMUIO8yNG/Bc17m+TaC8keaLeE1eM6hYI5J6mU=;\n\tb=uKrA93y7C4vd52AoCYOgzTyMcFRLXzSjpNNUX3uTn9gMiRxY6iH3Cxqq1byS1jrisn\n\t1p8jDzE+PX1xpbnvBPkPxED2F2krGztR8Ofg029X6BD/E/IOVZlqS89WyPwIkPEQHtfk\n\t6KUNAWOeneFYVXB8ZOOK/5Bb3zGH7dX4qW5+u0O8U8A4jdLFfEBWnUgQVFmYHP+/wXb0\n\tHgRNYM7Ou7pldqrJIWW47KCAhULmbthWBOeP6xbyEYtn5ehjOWdtu3QuS3YmmYmtLGE2\n\tKo88VH7rSnjpRYImDPDNaqwJ0gnhVN4Q+08Qum+TV82NEXykzlSmqeW7SL4CwO6pQxW4\n\taueg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=C29pAoMUIO8yNG/Bc17m+TaC8keaLeE1eM6hYI5J6mU=;\n\tb=eV5K4JrEuTaBDzm87FY8CWAOR2U4FD48QdmHYiuU6IUvXvrzZp+hF2n1bDFBvX7Gf/\n\tjmmd+Rrfuph9JbikoABaBEwhuQt4k7H0YQfDR7saRMoeX/mzFOXLux4Bm9F4N3RxF4hM\n\txj30RNUPUZqh0zfMTKbnYxb1fSJaKFIL3c7wS85Tl3XMPDV2eTtZziB5x9IiqZpwtIwG\n\tThubvGjG38eJeo77A5XXj6RVUCOY55S2qTNM3FLAGf7EuHMWupqQCZIcU/zc3Cl4WDws\n\t6Xvrrbm6409xHTVIa3A8e6dreyJ9pN/ZKCDkM6IIQzbpygMjj0uUXOHbe8Fc6yOft/Ht\n\t3yTw==", "X-Gm-Message-State": "AHYfb5h4ScRvAFQRjTTm/76gmqa775D8i3yBIW1z+dVRBgawuI1pG48g\n\t1+0oV64Ac7divKz8", "X-Google-Smtp-Source": "ADKCNb5Z9UaLMioDhhrWhOudknKRPRwMDk0Rs4jUjtP964xaGEZwisGqLqkNjwYFdXa9sEJ3L8d+3w==", "X-Received": "by 10.99.2.2 with SMTP id 2mr1158328pgc.382.1503938307540;\n\tMon, 28 Aug 2017 09:38:27 -0700 (PDT)", "From": "Subbaraya Sundeep <sundeep.lkml@gmail.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org", "Date": "Mon, 28 Aug 2017 22:08:02 +0530", "Message-Id": "<1503938283-12404-5-git-send-email-sundeep.lkml@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "In-Reply-To": "<1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com>", "References": "<1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c00::242", "Subject": "[Qemu-devel] [Qemu devel v7 PATCH 4/5] msf2: Add Smartfusion2 SoC", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Subbaraya Sundeep <sundeep.lkml@gmail.com>,\n\tf4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Smartfusion2 SoC has hardened Microcontroller subsystem\nand flash based FPGA fabric. This patch adds support for\nMicrocontroller subsystem in the SoC.\n\nSigned-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>\n---\n default-configs/arm-softmmu.mak | 1 +\n hw/arm/Makefile.objs | 1 +\n hw/arm/msf2-soc.c | 215 ++++++++++++++++++++++++++++++++++++++++\n include/hw/arm/msf2-soc.h | 66 ++++++++++++\n 4 files changed, 283 insertions(+)\n create mode 100644 hw/arm/msf2-soc.c\n create mode 100644 include/hw/arm/msf2-soc.h", "diff": "diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak\nindex bbdd3c1..5059d13 100644\n--- a/default-configs/arm-softmmu.mak\n+++ b/default-configs/arm-softmmu.mak\n@@ -129,3 +129,4 @@ CONFIG_ACPI=y\n CONFIG_SMBIOS=y\n CONFIG_ASPEED_SOC=y\n CONFIG_GPIO_KEY=y\n+CONFIG_MSF2=y\ndiff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\nindex a2e56ec..df36a03 100644\n--- a/hw/arm/Makefile.objs\n+++ b/hw/arm/Makefile.objs\n@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n obj-$(CONFIG_MPS2) += mps2.o\n+obj-$(CONFIG_MSF2) += msf2-soc.o\ndiff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c\nnew file mode 100644\nindex 0000000..276eec5\n--- /dev/null\n+++ b/hw/arm/msf2-soc.c\n@@ -0,0 +1,215 @@\n+/*\n+ * SmartFusion2 SoC emulation.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu-common.h\"\n+#include \"hw/arm/arm.h\"\n+#include \"exec/address-spaces.h\"\n+#include \"hw/char/serial.h\"\n+#include \"hw/boards.h\"\n+#include \"sysemu/block-backend.h\"\n+#include \"qemu/cutils.h\"\n+#include \"hw/arm/msf2-soc.h\"\n+\n+#define MSF2_TIMER_BASE 0x40004000\n+#define MSF2_SYSREG_BASE 0x40038000\n+\n+#define ENVM_BASE_ADDRESS 0x60000000\n+\n+#define SRAM_BASE_ADDRESS 0x20000000\n+\n+#define MSF2_ENVM_SIZE (512 * K_BYTE)\n+#define MSF2_ESRAM_SIZE (64 * K_BYTE)\n+\n+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };\n+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };\n+\n+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };\n+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };\n+static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };\n+\n+static void m2sxxx_soc_initfn(Object *obj)\n+{\n+ MSF2State *s = MSF2_SOC(obj);\n+ int i;\n+\n+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);\n+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());\n+\n+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);\n+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());\n+\n+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);\n+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());\n+\n+ for (i = 0; i < MSF2_NUM_SPIS; i++) {\n+ object_initialize(&s->spi[i], sizeof(s->spi[i]),\n+ TYPE_MSS_SPI);\n+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());\n+ }\n+}\n+\n+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)\n+{\n+ MSF2State *s = MSF2_SOC(dev_soc);\n+ DeviceState *dev, *armv7m;\n+ SysBusDevice *busdev;\n+ Error *err = NULL;\n+ int i;\n+\n+ MemoryRegion *system_memory = get_system_memory();\n+ MemoryRegion *nvm = g_new(MemoryRegion, 1);\n+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);\n+ MemoryRegion *sram = g_new(MemoryRegion, 1);\n+\n+ memory_region_init_ram(nvm, NULL, \"MSF2.eNVM\", s->envm_size,\n+ &error_fatal);\n+\n+ /*\n+ * On power-on, the eNVM region 0x60000000 is automatically\n+ * remapped to the Cortex-M3 processor executable region\n+ * start address (0x0). We do not support remapping other eNVM,\n+ * eSRAM and DDR regions by guest(via Sysreg) currently.\n+ */\n+ memory_region_init_alias(nvm_alias, NULL, \"MSF2.eNVM.alias\",\n+ nvm, 0, s->envm_size);\n+\n+ memory_region_set_readonly(nvm, true);\n+ memory_region_set_readonly(nvm_alias, true);\n+\n+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);\n+ memory_region_add_subregion(system_memory, 0, nvm_alias);\n+\n+ memory_region_init_ram(sram, NULL, \"MSF2.eSRAM\", s->esram_size,\n+ &error_fatal);\n+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);\n+\n+ armv7m = DEVICE(&s->armv7m);\n+ qdev_prop_set_uint32(armv7m, \"num-irq\", 81);\n+ qdev_prop_set_string(armv7m, \"cpu-model\", \"cortex-m3\");\n+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n+ \"memory\", &error_abort);\n+ object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+\n+ system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;\n+\n+ for (i = 0; i < MSF2_NUM_UARTS; i++) {\n+ if (serial_hds[i]) {\n+ serial_mm_init(get_system_memory(), uart_addr[i], 2,\n+ qdev_get_gpio_in(armv7m, uart_irq[i]),\n+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);\n+ }\n+ }\n+\n+ dev = DEVICE(&s->timer);\n+ /* APB0 clock is the timer input clock */\n+ qdev_prop_set_uint32(dev, \"clock-frequency\", s->m3clk / s->apb0div);\n+ object_property_set_bool(OBJECT(&s->timer), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+ busdev = SYS_BUS_DEVICE(dev);\n+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);\n+ sysbus_connect_irq(busdev, 0,\n+ qdev_get_gpio_in(armv7m, timer_irq[0]));\n+ sysbus_connect_irq(busdev, 1,\n+ qdev_get_gpio_in(armv7m, timer_irq[1]));\n+\n+ dev = DEVICE(&s->sysreg);\n+ qdev_prop_set_uint32(dev, \"apb0divisor\", s->apb0div);\n+ qdev_prop_set_uint32(dev, \"apb1divisor\", s->apb1div);\n+ object_property_set_bool(OBJECT(&s->sysreg), true, \"realized\", &err);\n+ if (err != NULL) {\n+ error_propagate(errp, err);\n+ return;\n+ }\n+ busdev = SYS_BUS_DEVICE(dev);\n+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);\n+\n+ for (i = 0; i < MSF2_NUM_SPIS; i++) {\n+ gchar *bus_name = g_strdup_printf(\"spi%d\", i);\n+\n+ object_property_set_bool(OBJECT(&s->spi[i]), true, \"realized\", &err);\n+ if (err != NULL) {\n+ g_free(bus_name);\n+ error_propagate(errp, err);\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n+ qdev_get_gpio_in(armv7m, spi_irq[i]));\n+\n+ /* Alias controller SPI bus to the SoC itself */\n+ object_property_add_alias(OBJECT(s), bus_name,\n+ OBJECT(&s->spi[i]), \"spi\",\n+ &error_abort);\n+ g_free(bus_name);\n+ }\n+}\n+\n+static Property m2sxxx_soc_properties[] = {\n+ /*\n+ * part name specifies the type of SmartFusion2 device variant(this\n+ * property is for information purpose only.\n+ */\n+ DEFINE_PROP_STRING(\"part-name\", MSF2State, part_name),\n+ DEFINE_PROP_UINT64(\"eNVM-size\", MSF2State, envm_size, MSF2_ENVM_SIZE),\n+ DEFINE_PROP_UINT64(\"eSRAM-size\", MSF2State, esram_size, MSF2_ESRAM_SIZE),\n+ /* Libero GUI shows 100Mhz as default for clocks */\n+ DEFINE_PROP_UINT32(\"m3clk\", MSF2State, m3clk, 100 * 1000000),\n+ /* default divisors in Libero GUI */\n+ DEFINE_PROP_UINT32(\"apb0div\", MSF2State, apb0div, 2),\n+ DEFINE_PROP_UINT32(\"apb1div\", MSF2State, apb1div, 2),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = m2sxxx_soc_realize;\n+ dc->props = m2sxxx_soc_properties;\n+}\n+\n+static const TypeInfo m2sxxx_soc_info = {\n+ .name = TYPE_MSF2_SOC,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(MSF2State),\n+ .instance_init = m2sxxx_soc_initfn,\n+ .class_init = m2sxxx_soc_class_init,\n+};\n+\n+static void m2sxxx_soc_types(void)\n+{\n+ type_register_static(&m2sxxx_soc_info);\n+}\n+\n+type_init(m2sxxx_soc_types)\ndiff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h\nnew file mode 100644\nindex 0000000..eb239fa\n--- /dev/null\n+++ b/include/hw/arm/msf2-soc.h\n@@ -0,0 +1,66 @@\n+/*\n+ * Microsemi Smartfusion2 SoC\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_ARM_MSF2_SOC_H\n+#define HW_ARM_MSF2_SOC_H\n+\n+#include \"hw/arm/armv7m.h\"\n+#include \"hw/timer/mss-timer.h\"\n+#include \"hw/misc/msf2-sysreg.h\"\n+#include \"hw/ssi/mss-spi.h\"\n+\n+#define TYPE_MSF2_SOC \"msf2-soc\"\n+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)\n+\n+#define MSF2_NUM_SPIS 2\n+#define MSF2_NUM_UARTS 2\n+\n+/*\n+ * System timer consists of two programmable 32-bit\n+ * decrementing counters that generate individual interrupts to\n+ * the Cortex-M3 processor\n+ */\n+#define MSF2_NUM_TIMERS 2\n+\n+typedef struct MSF2State {\n+ /*< private >*/\n+ SysBusDevice parent_obj;\n+ /*< public >*/\n+\n+ ARMv7MState armv7m;\n+\n+ char *part_name;\n+ uint64_t envm_size;\n+ uint64_t esram_size;\n+\n+ uint32_t m3clk;\n+ uint32_t apb0div;\n+ uint32_t apb1div;\n+\n+ MSF2SysregState sysreg;\n+ MSSTimerState timer;\n+ MSSSpiState spi[MSF2_NUM_SPIS];\n+} MSF2State;\n+\n+#endif\n", "prefixes": [ "Qemu", "devel", "v7", "4/5" ] }