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GET /api/patches/806634/?format=api
{ "id": 806634, "url": "http://patchwork.ozlabs.org/api/patches/806634/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828152517.24506-2-jlu@pengutronix.de/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828152517.24506-2-jlu@pengutronix.de>", "list_archive_url": null, "date": "2017-08-28T15:25:16", "name": "[1/2] bus: mbus: fix window size calculation for 4GB windows", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "4519f1efd27d3409a50fd32903913f8b3e0f0c69", "submitter": { "id": 16217, "url": "http://patchwork.ozlabs.org/api/people/16217/?format=api", "name": "Jan Lübbe", "email": "jlu@pengutronix.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828152517.24506-2-jlu@pengutronix.de/mbox/", "series": [ { "id": 195, "url": "http://patchwork.ozlabs.org/api/series/195/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=195", "date": "2017-08-28T15:25:17", "name": "fix 4GB DRAM window support on mvebu", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/195/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806634/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806634/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgwZV4YDgz9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 01:25:38 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751184AbdH1PZg (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 11:25:36 -0400", "from metis.ext.4.pengutronix.de ([92.198.50.35]:51719 \"EHLO\n\tmetis.ext.4.pengutronix.de\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751259AbdH1PZe (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 11:25:34 -0400", "from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7])\n\tby metis.ext.pengutronix.de with esmtps\n\t(TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2)\n\t(envelope-from <jlu@pengutronix.de>)\n\tid 1dmLus-00080o-Cc; Mon, 28 Aug 2017 17:25:30 +0200", "from jlu by dude.hi.pengutronix.de with local (Exim 4.89)\n\t(envelope-from <jlu@pengutronix.de>)\n\tid 1dmLur-0006O2-Jg; Mon, 28 Aug 2017 17:25:29 +0200" ], "From": "Jan Luebbe <jlu@pengutronix.de>", "To": "Gregory Clement <gregory.clement@free-electrons.com>,\n\tAndrew Lunn <andrew@lunn.ch>,\n\tThomas Petazzoni <thomas.petazzoni@free-electrons.com>,\n\tJason Cooper <jason@lakedaemon.net>", "Cc": "linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, kernel@pengutronix.de,\n\tJan Luebbe <jlu@pengutronix.de>", "Subject": "[PATCH 1/2] bus: mbus: fix window size calculation for 4GB windows", "Date": "Mon, 28 Aug 2017 17:25:16 +0200", "Message-Id": "<20170828152517.24506-2-jlu@pengutronix.de>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170828152517.24506-1-jlu@pengutronix.de>", "References": "<20170828152517.24506-1-jlu@pengutronix.de>", "X-SA-Exim-Connect-IP": "2001:67c:670:100:1d::7", "X-SA-Exim-Mail-From": "jlu@pengutronix.de", "X-SA-Exim-Scanned": "No (on metis.ext.pengutronix.de);\n\tSAEximRunCond expanded to false", "X-PTX-Original-Recipient": "linux-pci@vger.kernel.org", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "At least the Armada XP SoC supports 4GB on a single DRAM window. Because\nthe size register values contain the actual size - 1, the MSB is set in\nthat case. For example, the SDRAM window's control register's value is\n0xffffffe1 for 4GB (bits 31 to 24 contain the size).\n\nThe MBUS driver reads back each window's size from registers and\ncalculates the actual size as (control_reg | ~DDR_SIZE_MASK) + 1, which\noverflows for 32 bit values, resulting in other miscalculations further\non (a bad RAM window for the CESA crypto engine calculated by\nmvebu_mbus_setup_cpu_target_nooverlap() in my case).\n\nThis patch changes the type in 'struct mbus_dram_window' from u32 to\nu64, which allows us to keep using the same register calculation code in\nmost MBUS-using drivers (which calculate ->size - 1 again).\n\nSigned-off-by: Jan Luebbe <jlu@pengutronix.de>\n---\n drivers/bus/mvebu-mbus.c | 2 +-\n include/linux/mbus.h | 4 ++--\n 2 files changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c\nindex c7f396903184..70db4d5638a6 100644\n--- a/drivers/bus/mvebu-mbus.c\n+++ b/drivers/bus/mvebu-mbus.c\n@@ -720,7 +720,7 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)\n \t\t\tif (mbus->hw_io_coherency)\n \t\t\t\tw->mbus_attr |= ATTR_HW_COHERENCY;\n \t\t\tw->base = base & DDR_BASE_CS_LOW_MASK;\n-\t\t\tw->size = (size | ~DDR_SIZE_MASK) + 1;\n+\t\t\tw->size = (u64)(size | ~DDR_SIZE_MASK) + 1;\n \t\t}\n \t}\n \tmvebu_mbus_dram_info.num_cs = cs;\ndiff --git a/include/linux/mbus.h b/include/linux/mbus.h\nindex 0d3f14fd2621..4773145246ed 100644\n--- a/include/linux/mbus.h\n+++ b/include/linux/mbus.h\n@@ -31,8 +31,8 @@ struct mbus_dram_target_info\n \tstruct mbus_dram_window {\n \t\tu8\tcs_index;\n \t\tu8\tmbus_attr;\n-\t\tu32\tbase;\n-\t\tu32\tsize;\n+\t\tu64\tbase;\n+\t\tu64\tsize;\n \t} cs[4];\n };\n \n", "prefixes": [ "1/2" ] }