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GET /api/patches/806571/?format=api
{ "id": 806571, "url": "http://patchwork.ozlabs.org/api/patches/806571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/alpine.LNX.2.20.13.1708281554010.20460@monopod.intra.ispras.ru/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<alpine.LNX.2.20.13.1708281554010.20460@monopod.intra.ispras.ru>", "list_archive_url": null, "date": "2017-08-28T13:06:26", "name": "ira-costs: avoid missing base registers in record_address_regs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0e52933571a01378e6a09f0af939780d3144ffe6", "submitter": { "id": 5136, "url": "http://patchwork.ozlabs.org/api/people/5136/?format=api", "name": "Alexander Monakov", "email": "amonakov@ispras.ru" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/alpine.LNX.2.20.13.1708281554010.20460@monopod.intra.ispras.ru/mbox/", "series": [ { "id": 165, "url": "http://patchwork.ozlabs.org/api/series/165/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=165", "date": "2017-08-28T13:06:26", "name": "ira-costs: avoid missing base registers in record_address_regs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/165/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806571/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806571/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-461017-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461017-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"RKP9GMoE\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xgsV85nN0z9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 23:06:39 +1000 (AEST)", "(qmail 27127 invoked by alias); 28 Aug 2017 13:06:31 -0000", "(qmail 27112 invoked by uid 89); 28 Aug 2017 13:06:29 -0000", "from bran.ispras.ru (HELO smtp.ispras.ru) (83.149.199.196) by\n\tsourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 28 Aug 2017 13:06:28 +0000", "from monopod.intra.ispras.ru (monopod.intra.ispras.ru\n\t[10.10.3.121])\tby smtp.ispras.ru (Postfix) with ESMTP id\n\t6E7C55FB56; Mon, 28 Aug 2017 16:06:26 +0300 (MSK)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:mime-version:content-type; q=dns;\n\ts=default; b=QIdN6eWLY26EYc84/TYZP5UYxTEqjsW7O7I0eXFI7bE56f5a2w\n\tiyyXRodTiEWKYDJyRkXsFm8iSnsOrmfl2rdxDB+ah+gOus0HXomfM/hjrJ9Qteg+\n\twprRYkYc8KOuE5uICol+ihCz+DsXhq2DnCR8KJwd2/N69TA9loUknFIp8=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:cc:subject:message-id:mime-version:content-type; s=\n\tdefault; bh=UqgSi0EtQhM3mFyebAZI6Z7Ca1w=; b=RKP9GMoEWr9u2Ez9LCoE\n\tMrcC7TnCmmkbsbYq9W5DfMY7Gmwus6lpd11LVWMulZe0wXCMlGZFX6rWMPF+DeBE\n\tE1jL1GkwbVGPt1O3EiSeW7BJqfnIJ3hOC1V1EqTC9GCSZhTeAF+uch9iQb+HPlDc\n\teopv4F8SPnmfq2MLRB8YEXE=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-24.7 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "smtp.ispras.ru", "Date": "Mon, 28 Aug 2017 16:06:26 +0300 (MSK)", "From": "Alexander Monakov <amonakov@ispras.ru>", "To": "gcc-patches@gcc.gnu.org", "cc": "\"Vladimir N. Makarov\" <vmakarov@redhat.com>", "Subject": "[PATCH] ira-costs: avoid missing base registers in\n\trecord_address_regs", "Message-ID": "<alpine.LNX.2.20.13.1708281554010.20460@monopod.intra.ispras.ru>", "User-Agent": "Alpine 2.20.13 (LNX 116 2015-12-14)", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=US-ASCII" }, "content": "Hello,\n\nThe code in record_address_regs shown in the following patch assumes that\nif a given target cannot have two registers in a memory address, then the\nsole register, if present, must be the leftmost operand in the PLUS chain.\n\nI think this is not true if the target uses unspecs to signify special\naddressing modes such as TLS. In that case the unspec can be to the left\nof the register, and this function won't see the register.\n\nThe proposed fix is to always recurse into non-constant operands like in the\nadjacent case of index registers being the same as base registers. OK to apply?\n\n(most popular targets have MAX_REGS_PER_ADDRESS == 2, so this problem doesn't\narise)\n\nAlexander\n\n\t* ira-costs.c (record_address_regs): Handle both operands of PLUS for\n\tMAX_REGS_PER_ADDRESS == 1.", "diff": "diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c\nindex 2cd102a0810..1690e889471 100644\n--- a/gcc/ira-costs.c\n+++ b/gcc/ira-costs.c\n@@ -1138,17 +1138,12 @@ record_address_regs (machine_mode mode, addr_space_t as, rtx x,\n \tif (code1 == SUBREG)\n \t arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);\n \n-\t/* If this machine only allows one register per address, it\n-\t must be in the first operand. */\n-\tif (MAX_REGS_PER_ADDRESS == 1)\n-\t record_address_regs (mode, as, arg0, 0, PLUS, code1, scale);\n-\n-\t/* If index and base registers are the same on this machine,\n+\t/* If index registers do not appear, or coincide with base registers,\n \t just record registers in any non-constant operands. We\n \t assume here, as well as in the tests below, that all\n \t addresses are in canonical form. */\n-\telse if (INDEX_REG_CLASS\n-\t\t == base_reg_class (VOIDmode, as, PLUS, SCRATCH))\n+\tif (MAX_REGS_PER_ADDRESS == 1\n+\t || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH))\n \t {\n \t record_address_regs (mode, as, arg0, context, PLUS, code1, scale);\n \t if (! CONSTANT_P (arg1))\n", "prefixes": [] }