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{
    "id": 806553,
    "url": "http://patchwork.ozlabs.org/api/patches/806553/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170828121604.15968-4-romain.perier@collabora.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170828121604.15968-4-romain.perier@collabora.com>",
    "list_archive_url": null,
    "date": "2017-08-28T12:16:03",
    "name": "[3/4] nvmem: rockchip: add support for RK3368",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": true,
    "hash": "e18fdb1c93ebf41647ee166a19c675cbbed8887e",
    "submitter": {
        "id": 70720,
        "url": "http://patchwork.ozlabs.org/api/people/70720/?format=api",
        "name": "Romain Perier",
        "email": "romain.perier@collabora.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170828121604.15968-4-romain.perier@collabora.com/mbox/",
    "series": [
        {
            "id": 153,
            "url": "http://patchwork.ozlabs.org/api/series/153/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=153",
            "date": "2017-08-28T12:16:00",
            "name": "rockchip: Add efuse support for RK3368 SoCs",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/153/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806553/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806553/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgrN46CTmz9s8w\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 22:16:20 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751258AbdH1MQU (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 08:16:20 -0400",
            "from bhuna.collabora.co.uk ([46.235.227.227]:54041 \"EHLO\n\tbhuna.collabora.co.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751232AbdH1MQT (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Mon, 28 Aug 2017 08:16:19 -0400",
            "from [127.0.0.1] (localhost [127.0.0.1])\n\t(Authenticated sender: rperier) with ESMTPSA id B3B6D26C8F9"
        ],
        "From": "Romain Perier <romain.perier@collabora.com>",
        "To": "Michael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org,\n\tHeiko Stuebner <heiko@sntech.de>,\n\tSrinivas Kandagatla <srinivas.kandagatla@linaro.org>",
        "Cc": "devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,\n\tIan Campbell <ijc+devicetree@hellion.org.uk>,\n\tPawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, \n\tKumar Gala <galak@codeaurora.org>, linux-arm-kernel@lists.infradead.org, \n\tlinux-rockchip@lists.infradead.org,\n\tRomain Perier <romain.perier@collabora.com>",
        "Subject": "[PATCH 3/4] nvmem: rockchip: add support for RK3368",
        "Date": "Mon, 28 Aug 2017 14:16:03 +0200",
        "Message-Id": "<20170828121604.15968-4-romain.perier@collabora.com>",
        "X-Mailer": "git-send-email 2.11.0",
        "In-Reply-To": "<20170828121604.15968-1-romain.perier@collabora.com>",
        "References": "<20170828121604.15968-1-romain.perier@collabora.com>",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "This adds the necessary functions and data for handling support on RK3368\nSoCs.\n\nSigned-off-by: Romain Perier <romain.perier@collabora.com>\n---\n .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  1 +\n drivers/nvmem/rockchip-efuse.c                     | 80 ++++++++++++++++++++++\n 2 files changed, 81 insertions(+)",
    "diff": "diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt\nindex 1ff02afdc55a..60bec4782806 100644\n--- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt\n+++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt\n@@ -6,6 +6,7 @@ Required properties:\n   - \"rockchip,rk3188-efuse\" - for RK3188 SoCs.\n   - \"rockchip,rk3228-efuse\" - for RK3228 SoCs.\n   - \"rockchip,rk3288-efuse\" - for RK3288 SoCs.\n+  - \"rockchip,rk3368-efuse\" - for RK3368 SoCs.\n   - \"rockchip,rk3399-efuse\" - for RK3399 SoCs.\n - reg: Should contain the registers location and exact eFuse size\n - clocks: Should be the clock id of eFuse\ndiff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c\nindex 63e3eb55f3ac..4e11f251035f 100644\n--- a/drivers/nvmem/rockchip-efuse.c\n+++ b/drivers/nvmem/rockchip-efuse.c\n@@ -14,6 +14,7 @@\n  * more details.\n  */\n \n+#include <linux/arm-smccc.h>\n #include <linux/clk.h>\n #include <linux/delay.h>\n #include <linux/device.h>\n@@ -46,9 +47,17 @@\n #define REG_EFUSE_CTRL\t\t0x0000\n #define REG_EFUSE_DOUT\t\t0x0004\n \n+/* SMC function IDs for SiP Service queries */\n+#define ROCKCHIP_SIP_ACCESS_REG\t0x82000002\n+\n+/* SIP access registers: read or write */\n+#define ROCKCHIP_SIP_SECURE_REG_RD\t0x0\n+#define ROCKCHIP_SIP_SECURE_REG_WR\t0x1\n+\n struct rockchip_efuse_chip {\n \tstruct device *dev;\n \tvoid __iomem *base;\n+\tphys_addr_t phys;\n \tstruct clk *clk;\n };\n \n@@ -92,6 +101,72 @@ static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,\n \treturn 0;\n }\n \n+static u32 smc_reg_read(u32 addr_phy)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, 0, addr_phy,\n+\t\t      ROCKCHIP_SIP_SECURE_REG_RD, 0, 0, 0, 0, &res);\n+\tif (res.a0)\n+\t\tpr_err(\"%s error: %d, addr phy: 0x%x\\n\", __func__, (int)res.a0,\n+\t\t       addr_phy);\n+\treturn res.a1;\n+}\n+\n+static u32 smc_reg_write(u32 addr_phy, u32 val)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, val, addr_phy,\n+\t\t      ROCKCHIP_SIP_SECURE_REG_WR, 0, 0, 0, 0, &res);\n+\tif (res.a0)\n+\t\tpr_err(\"%s error: %d, addr phy: 0x%x\\n\", __func__, (int)res.a0,\n+                       addr_phy);\n+\treturn res.a0;\n+}\n+\n+static int rockchip_rk3368_efuse_read(void *context, unsigned int offset,\n+\t\t\t\t      void *val, size_t bytes)\n+{\n+\tstruct rockchip_efuse_chip *efuse = context;\n+\tu8 *buf = val;\n+\tint ret;\n+\n+\tret = clk_prepare_enable(efuse->clk);\n+\tif (ret < 0) {\n+\t\tdev_err(efuse->dev, \"failed to prepare/enable efuse clk\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB);\n+\tudelay(1);\n+\twhile (bytes--) {\n+\t\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL,\n+\t\t\t      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &\n+\t\t\t      (~(RK3288_A_MASK << RK3288_A_SHIFT)));\n+\t\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL,\n+\t\t\t      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |\n+\t\t\t      ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT));\n+\n+\t\tudelay(1);\n+\t\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL,\n+\t\t\t      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) |\n+\t\t\t      RK3288_STROBE);\n+\t\tudelay(1);\n+\t\t*buf++ = smc_reg_read(efuse->phys + REG_EFUSE_DOUT);\n+\t\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL,\n+\t\t\t      smc_reg_read(efuse->phys + REG_EFUSE_CTRL) &\n+\t\t\t      (~RK3288_STROBE));\n+\t\tudelay(1);\n+\t}\n+\n+\t/* Switch to standby mode */\n+\tsmc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB);\n+\n+\tclk_disable_unprepare(efuse->clk);\n+\treturn 0;\n+}\n+\n static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,\n \t\t\t\t      void *val, size_t bytes)\n {\n@@ -178,6 +253,10 @@ static const struct of_device_id rockchip_efuse_match[] = {\n \t\t.data = (void *)&rockchip_rk3288_efuse_read,\n \t},\n \t{\n+\t\t.compatible = \"rockchip,rk3368-efuse\",\n+\t\t.data = (void *)&rockchip_rk3368_efuse_read,\n+\t},\n+\t{\n \t\t.compatible = \"rockchip,rk3399-efuse\",\n \t\t.data = (void *)&rockchip_rk3399_efuse_read,\n \t},\n@@ -205,6 +284,7 @@ static int rockchip_efuse_probe(struct platform_device *pdev)\n \t\treturn -ENOMEM;\n \n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tefuse->phys = res->start;\n \tefuse->base = devm_ioremap_resource(&pdev->dev, res);\n \tif (IS_ERR(efuse->base))\n \t\treturn PTR_ERR(efuse->base);\n",
    "prefixes": [
        "3/4"
    ]
}