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{
    "id": 806519,
    "url": "http://patchwork.ozlabs.org/api/patches/806519/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-10-Zhiqiang.Hou@nxp.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170828105301.8511-10-Zhiqiang.Hou@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-28T10:53:01",
    "name": "[PATCHv5,9/9] PCI: dwc: remove the obsolete fixups",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "365e52667aa577a5272132787f1320f3be8aba5c",
    "submitter": {
        "id": 67929,
        "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api",
        "name": "Z.Q. Hou",
        "email": "zhiqiang.hou@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-10-Zhiqiang.Hou@nxp.com/mbox/",
    "series": [
        {
            "id": 133,
            "url": "http://patchwork.ozlabs.org/api/series/133/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=133",
            "date": "2017-08-28T10:52:52",
            "name": "PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/133/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806519/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806519/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>",
        "To": "<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>",
        "CC": "<minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,\n\t<niklas.cassel@axis.com>, <jesper.nilsson@axis.com>,\n\tHou Zhiqiang <Zhiqiang.Hou@nxp.com>",
        "Subject": "[PATCHv5 9/9] PCI: dwc: remove the obsolete fixups",
        "Date": "Mon, 28 Aug 2017 18:53:01 +0800",
        "Message-ID": "<20170828105301.8511-10-Zhiqiang.Hou@nxp.com>",
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        "In-Reply-To": "<20170828105301.8511-1-Zhiqiang.Hou@nxp.com>",
        "References": "<20170828105301.8511-1-Zhiqiang.Hou@nxp.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
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        "List-ID": "<linux-pci.vger.kernel.org>",
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    },
    "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nNow, the dw_pcie_setup_rc() works well, so remove the obsolete fixups:\nRemove the Class field fix code from layerscape pcie driver.\nRemove the line to enable write permission of DBI RO register from\nartpec6 pcie driver.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\nAcked-by: Roy Zang <tie-fei.zang@freescale.com>\n---\nV5:\n - No change\n\n drivers/pci/dwc/pci-layerscape.c | 9 ---------\n drivers/pci/dwc/pcie-artpec6.c   | 6 ------\n 2 files changed, 15 deletions(-)",
    "diff": "diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\nindex 65f5d543fe89..c24dd77c6424 100644\n--- a/drivers/pci/dwc/pci-layerscape.c\n+++ b/drivers/pci/dwc/pci-layerscape.c\n@@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)\n \tiowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);\n }\n \n-/* Fix class value */\n-static void ls_pcie_fix_class(struct ls_pcie *pcie)\n-{\n-\tstruct dw_pcie *pci = pcie->pci;\n-\n-\tiowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);\n-}\n-\n /* Drop MSG TLP except for Vendor MSG */\n static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)\n {\n@@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)\n \tls_pcie_disable_outbound_atus(pcie);\n \n \tdw_pcie_dbi_ro_wr_en(pci);\n-\tls_pcie_fix_class(pcie);\n \tls_pcie_clear_multifunction(pcie);\n \tdw_pcie_dbi_ro_wr_dis(pci);\n \ndiff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c\nindex 5d81f1d884e3..d153491f600f 100644\n--- a/drivers/pci/dwc/pcie-artpec6.c\n+++ b/drivers/pci/dwc/pcie-artpec6.c\n@@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)\n \tartpec6_pcie_writel(artpec6_pcie, PCIECFG, val);\n \tusleep_range(100, 200);\n \n-\t/*\n-\t * Enable writing to config regs. This is required as the Synopsys\n-\t * driver changes the class code. That register needs DBI write enable.\n-\t */\n-\tdw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);\n-\n \t/* setup root complex */\n \tdw_pcie_setup_rc(pp);\n \n",
    "prefixes": [
        "PATCHv5",
        "9/9"
    ]
}