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{
    "id": 806517,
    "url": "http://patchwork.ozlabs.org/api/patches/806517/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-8-Zhiqiang.Hou@nxp.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
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        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170828105301.8511-8-Zhiqiang.Hou@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-28T10:52:59",
    "name": "[PATCHv5,7/9] PCI: designware: add accessors for write permission of DBI read-only registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "725cfafac4def446742377c437ac009d754c444f",
    "submitter": {
        "id": 67929,
        "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api",
        "name": "Z.Q. Hou",
        "email": "zhiqiang.hou@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-8-Zhiqiang.Hou@nxp.com/mbox/",
    "series": [
        {
            "id": 133,
            "url": "http://patchwork.ozlabs.org/api/series/133/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=133",
            "date": "2017-08-28T10:52:52",
            "name": "PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/133/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806517/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806517/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>",
        "To": "<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>",
        "CC": "<minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,\n\t<niklas.cassel@axis.com>, <jesper.nilsson@axis.com>,\n\tHou Zhiqiang <Zhiqiang.Hou@nxp.com>",
        "Subject": "[PATCHv5 7/9] PCI: designware: add accessors for write permission\n\tof DBI read-only registers",
        "Date": "Mon, 28 Aug 2017 18:52:59 +0800",
        "Message-ID": "<20170828105301.8511-8-Zhiqiang.Hou@nxp.com>",
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        "References": "<20170828105301.8511-1-Zhiqiang.Hou@nxp.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
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        "List-ID": "<linux-pci.vger.kernel.org>",
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    "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nThe read-only DBI registers can be written over when set the \"Write\nto RO Registers Using DBI\" (DBI_RO_WR_EN) field of the register\nMISC_CONTROL_1_OFF. And change to use the accessors instead accessing\nthe register MISC_CONTROL_1_OFF directly.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\nAcked-by: Joao Pinto <jpinto@synopsys.com>\nAcked-by: Roy Zang <tie-fei.zang@freescale.com>\n---\nV5:\n - Squashed patch v4 6/9 and 7/9 together\n\n drivers/pci/dwc/pci-layerscape.c  |  5 ++---\n drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++\n 2 files changed, 27 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\nindex 8b5083aedf16..65f5d543fe89 100644\n--- a/drivers/pci/dwc/pci-layerscape.c\n+++ b/drivers/pci/dwc/pci-layerscape.c\n@@ -33,7 +33,6 @@\n \n /* PEX Internal Configuration Registers */\n #define PCIE_STRFMR1\t\t0x71c /* Symbol Timer & Filter Mask Register1 */\n-#define PCIE_DBI_RO_WR_EN\t0x8bc /* DBI Read-Only Write Enable Register */\n \n #define PCIE_IATU_NUM\t\t6\n \n@@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)\n \t */\n \tls_pcie_disable_outbound_atus(pcie);\n \n-\tiowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n+\tdw_pcie_dbi_ro_wr_en(pci);\n \tls_pcie_fix_class(pcie);\n \tls_pcie_clear_multifunction(pcie);\n-\tiowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n+\tdw_pcie_dbi_ro_wr_dis(pci);\n \n \tls_pcie_drop_msg_tlp(pcie);\n \ndiff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h\nindex 7366c8167404..0c5f874345f6 100644\n--- a/drivers/pci/dwc/pcie-designware.h\n+++ b/drivers/pci/dwc/pcie-designware.h\n@@ -76,6 +76,9 @@\n #define PCIE_ATU_FUNC(x)\t\t(((x) & 0x7) << 16)\n #define PCIE_ATU_UPPER_TARGET\t\t0x91C\n \n+#define PCIE_MISC_CONTROL_1_OFF\t\t0x8BC\n+#define PCIE_DBI_RO_WR_EN\t\t(0x1 << 0)\n+\n /*\n  * iATU Unroll-specific register definitions\n  * From 4.80 core version the address translation will be made by unroll\n@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)\n \treturn __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);\n }\n \n+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)\n+{\n+\tu32 reg;\n+\tu32 val;\n+\n+\treg = PCIE_MISC_CONTROL_1_OFF;\n+\tval = dw_pcie_readl_dbi(pci, reg);\n+\tval |= PCIE_DBI_RO_WR_EN;\n+\tdw_pcie_writel_dbi(pci, reg, val);\n+}\n+\n+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)\n+{\n+\tu32 reg;\n+\tu32 val;\n+\n+\treg = PCIE_MISC_CONTROL_1_OFF;\n+\tval = dw_pcie_readl_dbi(pci, reg);\n+\tval &= ~PCIE_DBI_RO_WR_EN;\n+\tdw_pcie_writel_dbi(pci, reg, val);\n+}\n+\n #ifdef CONFIG_PCIE_DW_HOST\n irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);\n void dw_pcie_msi_init(struct pcie_port *pp);\n",
    "prefixes": [
        "PATCHv5",
        "7/9"
    ]
}