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{
    "id": 806516,
    "url": "http://patchwork.ozlabs.org/api/patches/806516/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-7-Zhiqiang.Hou@nxp.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
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        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170828105301.8511-7-Zhiqiang.Hou@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-28T10:52:58",
    "name": "[PATCHv5,6/9] PCI: layerscape: Disable the outbound windows configured by bootloader",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "c5be1a755bb2cd1ad6e40350ec467a7f7d902418",
    "submitter": {
        "id": 67929,
        "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api",
        "name": "Z.Q. Hou",
        "email": "zhiqiang.hou@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-7-Zhiqiang.Hou@nxp.com/mbox/",
    "series": [
        {
            "id": 133,
            "url": "http://patchwork.ozlabs.org/api/series/133/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=133",
            "date": "2017-08-28T10:52:52",
            "name": "PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/133/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806516/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806516/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>",
        "To": "<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>",
        "CC": "<minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,\n\t<niklas.cassel@axis.com>, <jesper.nilsson@axis.com>,\n\tHou Zhiqiang <Zhiqiang.Hou@nxp.com>",
        "Subject": "[PATCHv5 6/9] PCI: layerscape: Disable the outbound windows\n\tconfigured by bootloader",
        "Date": "Mon, 28 Aug 2017 18:52:58 +0800",
        "Message-ID": "<20170828105301.8511-7-Zhiqiang.Hou@nxp.com>",
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        "References": "<20170828105301.8511-1-Zhiqiang.Hou@nxp.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
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    },
    "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nDisable all the outbound windows to avoid one transaction hitting\nmultiple outbound windows, because the function dw_pcie_setup_rc\nwill re-configure the outbound windows which maybe confict with\nthe bootloader configured.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\nAcked-by: Roy Zang <tie-fei.zang@freescale.com>\n---\nV5:\n - No change\n\n drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)",
    "diff": "diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\nindex 27234dae4cba..8b5083aedf16 100644\n--- a/drivers/pci/dwc/pci-layerscape.c\n+++ b/drivers/pci/dwc/pci-layerscape.c\n@@ -35,6 +35,8 @@\n #define PCIE_STRFMR1\t\t0x71c /* Symbol Timer & Filter Mask Register1 */\n #define PCIE_DBI_RO_WR_EN\t0x8bc /* DBI Read-Only Write Enable Register */\n \n+#define PCIE_IATU_NUM\t\t6\n+\n struct ls_pcie_drvdata {\n \tu32 lut_offset;\n \tu32 ltssm_shift;\n@@ -91,6 +93,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)\n \tiowrite32(val, pci->dbi_base + PCIE_STRFMR1);\n }\n \n+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < PCIE_IATU_NUM; i++)\n+\t\tdw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);\n+}\n+\n static int ls1021_pcie_link_up(struct dw_pcie *pci)\n {\n \tu32 state;\n@@ -128,6 +138,13 @@ static int ls_pcie_host_init(struct pcie_port *pp)\n \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n \tstruct ls_pcie *pcie = to_ls_pcie(pci);\n \n+\t/*\n+\t * Disable the outbound windows configured by bootloader to avoid\n+\t * one transaction hitting multiple outbound windows and the function\n+\t * dw_pcie_setup_rc will re-configure the outbound windows.\n+\t */\n+\tls_pcie_disable_outbound_atus(pcie);\n+\n \tiowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n \tls_pcie_fix_class(pcie);\n \tls_pcie_clear_multifunction(pcie);\n",
    "prefixes": [
        "PATCHv5",
        "6/9"
    ]
}