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{
    "id": 806514,
    "url": "http://patchwork.ozlabs.org/api/patches/806514/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-5-Zhiqiang.Hou@nxp.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170828105301.8511-5-Zhiqiang.Hou@nxp.com>",
    "list_archive_url": null,
    "date": "2017-08-28T10:52:56",
    "name": "[PATCHv5,4/9] PCI: layerscape: move ls1021 specific host_init behind the common one",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "9fd0f23c8cfe7a66a7edcb2a6bb6b91e3ca6596d",
    "submitter": {
        "id": 67929,
        "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api",
        "name": "Z.Q. Hou",
        "email": "zhiqiang.hou@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170828105301.8511-5-Zhiqiang.Hou@nxp.com/mbox/",
    "series": [
        {
            "id": 133,
            "url": "http://patchwork.ozlabs.org/api/series/133/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=133",
            "date": "2017-08-28T10:52:52",
            "name": "PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/133/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806514/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806514/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-pci-owner@vger.kernel.org>",
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        "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>",
        "To": "<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>",
        "CC": "<minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,\n\t<niklas.cassel@axis.com>, <jesper.nilsson@axis.com>,\n\tHou Zhiqiang <Zhiqiang.Hou@nxp.com>",
        "Subject": "[PATCHv5 4/9] PCI: layerscape: move ls1021 specific host_init\n\tbehind the common one",
        "Date": "Mon, 28 Aug 2017 18:52:56 +0800",
        "Message-ID": "<20170828105301.8511-5-Zhiqiang.Hou@nxp.com>",
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        "References": "<20170828105301.8511-1-Zhiqiang.Hou@nxp.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
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    "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nTo prepare for calling the common host_init in ls1021 spceific\nhost_init, moves ls1021 specific host_init behind the common\nhost_init function.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\nAcked-by: Roy Zang <tie-fei.zang@freescale.com>\n---\nV5:\n - New patch, split from 4/9 patch v4\n\n drivers/pci/dwc/pci-layerscape.c | 64 ++++++++++++++++++++--------------------\n 1 file changed, 32 insertions(+), 32 deletions(-)",
    "diff": "diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\nindex 3aa34214643c..160035efa4d9 100644\n--- a/drivers/pci/dwc/pci-layerscape.c\n+++ b/drivers/pci/dwc/pci-layerscape.c\n@@ -108,6 +108,38 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)\n \treturn 1;\n }\n \n+static int ls_pcie_link_up(struct dw_pcie *pci)\n+{\n+\tstruct ls_pcie *pcie = to_ls_pcie(pci);\n+\tu32 state;\n+\n+\tstate = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>\n+\t\t pcie->drvdata->ltssm_shift) &\n+\t\t LTSSM_STATE_MASK;\n+\n+\tif (state < LTSSM_PCIE_L0)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static int ls_pcie_host_init(struct pcie_port *pp)\n+{\n+\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n+\tstruct ls_pcie *pcie = to_ls_pcie(pci);\n+\n+\tiowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n+\tls_pcie_fix_class(pcie);\n+\tls_pcie_clear_multifunction(pcie);\n+\tiowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n+\n+\tls_pcie_drop_msg_tlp(pcie);\n+\n+\tdw_pcie_setup_rc(pp);\n+\n+\treturn 0;\n+}\n+\n static int ls1021_pcie_host_init(struct pcie_port *pp)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n@@ -144,38 +176,6 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)\n \treturn 0;\n }\n \n-static int ls_pcie_link_up(struct dw_pcie *pci)\n-{\n-\tstruct ls_pcie *pcie = to_ls_pcie(pci);\n-\tu32 state;\n-\n-\tstate = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>\n-\t\t pcie->drvdata->ltssm_shift) &\n-\t\t LTSSM_STATE_MASK;\n-\n-\tif (state < LTSSM_PCIE_L0)\n-\t\treturn 0;\n-\n-\treturn 1;\n-}\n-\n-static int ls_pcie_host_init(struct pcie_port *pp)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n-\tstruct ls_pcie *pcie = to_ls_pcie(pci);\n-\n-\tiowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n-\tls_pcie_fix_class(pcie);\n-\tls_pcie_clear_multifunction(pcie);\n-\tiowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);\n-\n-\tls_pcie_drop_msg_tlp(pcie);\n-\n-\tdw_pcie_setup_rc(pp);\n-\n-\treturn 0;\n-}\n-\n static int ls_pcie_msi_host_init(struct pcie_port *pp,\n \t\t\t\t struct msi_controller *chip)\n {\n",
    "prefixes": [
        "PATCHv5",
        "4/9"
    ]
}