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GET /api/patches/806473/?format=api
{ "id": 806473, "url": "http://patchwork.ozlabs.org/api/patches/806473/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503914654-19963-2-git-send-email-fabrice.gasnier@st.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503914654-19963-2-git-send-email-fabrice.gasnier@st.com>", "list_archive_url": null, "date": "2017-08-28T10:04:06", "name": "[RESEND,v3,1/9] dt-bindings: mfd: Add STM32 LPTimer binding", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "b0b3c7dfa4d644d3108169099f52b32eaf466868", "submitter": { "id": 65902, "url": "http://patchwork.ozlabs.org/api/people/65902/?format=api", "name": "Fabrice Gasnier", "email": "fabrice.gasnier@st.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503914654-19963-2-git-send-email-fabrice.gasnier@st.com/mbox/", "series": [ { "id": 125, "url": "http://patchwork.ozlabs.org/api/series/125/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=125", "date": "2017-08-28T10:04:06", "name": "Add STM32 LPTimer: PWM, trigger and counter", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/125/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806473/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806473/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgnVS06BQz9sNq\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 20:06:40 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751667AbdH1KFZ (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 06:05:25 -0400", "from mx07-00178001.pphosted.com ([62.209.51.94]:6258 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751546AbdH1KFU (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Mon, 28 Aug 2017 06:05:20 -0400", "from pps.filterd (m0046668.ppops.net [127.0.0.1])\n\tby mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7SA4ROJ021483; Mon, 28 Aug 2017 12:04:36 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx07-.pphosted.com with ESMTP id 2cjxevhefp-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tMon, 28 Aug 2017 12:04:36 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3BC7A34;\n\tMon, 28 Aug 2017 10:04:36 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 14C171FE8;\n\tMon, 28 Aug 2017 10:04:36 +0000 (GMT)", "from localhost (10.75.127.45) by SFHDAG5NODE3.st.com (10.75.127.15)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tMon, 28 Aug 2017 12:04:35 +0200" ], "From": "Fabrice Gasnier <fabrice.gasnier@st.com>", "To": "<lee.jones@linaro.org>, <benjamin.gaignard@linaro.org>,\n\t<jic23@kernel.org>, <thierry.reding@gmail.com>, <robh+dt@kernel.org>", "CC": "<mark.rutland@arm.com>, <alexandre.torgue@st.com>,\n\t<mcoquelin.stm32@gmail.com>, <fabrice.gasnier@st.com>,\n\t<benjamin.gaignard@st.com>, <linux-iio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, \n\t<linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>,\n\t<vilhelm.gray@gmail.com>", "Subject": "[RESEND PATCH v3 1/9] dt-bindings: mfd: Add STM32 LPTimer binding", "Date": "Mon, 28 Aug 2017 12:04:06 +0200", "Message-ID": "<1503914654-19963-2-git-send-email-fabrice.gasnier@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "References": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.75.127.45]", "X-ClientProxiedBy": "SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG5NODE3.st.com\n\t(10.75.127.15)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_06:, , signatures=0", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add documentation for STMicroelectronics STM32 Low-Power Timer binding.\n\nSigned-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>\nAcked-by: Jonathan Cameron <jic23@kernel.org>\nAcked-by: Rob Herring <robh@kernel.org>\n---\nChanges in v3:\n- Rob's comment on node name: timer@...\n\nChanges in v2:\n- Lee's comments: s/Low Power/Low-Power/, remove 0x in example, improve\n properties descriptions\n---\n .../devicetree/bindings/mfd/stm32-lptimer.txt | 48 ++++++++++++++++++++++\n 1 file changed, 48 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/stm32-lptimer.txt", "diff": "diff --git a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt\nnew file mode 100644\nindex 0000000..2a9ff29\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt\n@@ -0,0 +1,48 @@\n+STMicroelectronics STM32 Low-Power Timer\n+\n+The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several\n+functions:\n+- PWM output (with programmable prescaler, configurable polarity)\n+- Quadrature encoder, counter\n+- Trigger source for STM32 ADC/DAC (LPTIM_OUT)\n+\n+Required properties:\n+- compatible:\t\tMust be \"st,stm32-lptimer\".\n+- reg:\t\t\tOffset and length of the device's register set.\n+- clocks:\t\tPhandle to the clock used by the LP Timer module.\n+- clock-names:\t\tMust be \"mux\".\n+- #address-cells:\tShould be '<1>'.\n+- #size-cells:\t\tShould be '<0>'.\n+\n+Optional subnodes:\n+- pwm:\t\t\tSee ../pwm/pwm-stm32-lp.txt\n+- counter:\t\tSee ../iio/timer/stm32-lptimer-cnt.txt\n+- trigger:\t\tSee ../iio/timer/stm32-lptimer-trigger.txt\n+\n+Example:\n+\n+\ttimer@40002400 {\n+\t\tcompatible = \"st,stm32-lptimer\";\n+\t\treg = <0x40002400 0x400>;\n+\t\tclocks = <&timer_clk>;\n+\t\tclock-names = \"mux\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tpwm {\n+\t\t\tcompatible = \"st,stm32-pwm-lp\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&lppwm1_pins>;\n+\t\t};\n+\n+\t\ttrigger@0 {\n+\t\t\tcompatible = \"st,stm32-lptimer-trigger\";\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\tcounter {\n+\t\t\tcompatible = \"st,stm32-lptimer-counter\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&lptim1_in_pins>;\n+\t\t};\n+\t};\n", "prefixes": [ "RESEND", "v3", "1/9" ] }