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GET /api/patches/806472/?format=api
{ "id": 806472, "url": "http://patchwork.ozlabs.org/api/patches/806472/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/1503914654-19963-10-git-send-email-fabrice.gasnier@st.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503914654-19963-10-git-send-email-fabrice.gasnier@st.com>", "list_archive_url": null, "date": "2017-08-28T10:04:14", "name": "[RESEND,v3,9/9] iio: adc: stm32: add support for lptimer triggers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "04108170de3ce729d5da58fce5d401f13066b694", "submitter": { "id": 65902, "url": "http://patchwork.ozlabs.org/api/people/65902/?format=api", "name": "Fabrice Gasnier", "email": "fabrice.gasnier@st.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/1503914654-19963-10-git-send-email-fabrice.gasnier@st.com/mbox/", "series": [ { "id": 122, "url": "http://patchwork.ozlabs.org/api/series/122/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=122", "date": "2017-08-28T10:04:06", "name": "Add STM32 LPTimer: PWM, trigger and counter", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/122/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806472/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806472/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pwm-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pwm-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgnVM3F9sz9sNq\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 20:06:35 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751833AbdH1KGV (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 06:06:21 -0400", "from mx08-00178001.pphosted.com ([91.207.212.93]:35109 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751660AbdH1KFZ (ORCPT\n\t<rfc822; linux-pwm@vger.kernel.org>); Mon, 28 Aug 2017 06:05:25 -0400", "from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7SA4e13015962; Mon, 28 Aug 2017 12:04:43 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-.pphosted.com with ESMTP id 2cjyveha79-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tMon, 28 Aug 2017 12:04:43 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 75F4738;\n\tMon, 28 Aug 2017 10:04:42 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4A46D200A;\n\tMon, 28 Aug 2017 10:04:42 +0000 (GMT)", "from localhost (10.75.127.48) by SFHDAG5NODE3.st.com (10.75.127.15)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tMon, 28 Aug 2017 12:04:41 +0200" ], "From": "Fabrice Gasnier <fabrice.gasnier@st.com>", "To": "<lee.jones@linaro.org>, <benjamin.gaignard@linaro.org>,\n\t<jic23@kernel.org>, <thierry.reding@gmail.com>, <robh+dt@kernel.org>", "CC": "<mark.rutland@arm.com>, <alexandre.torgue@st.com>,\n\t<mcoquelin.stm32@gmail.com>, <fabrice.gasnier@st.com>,\n\t<benjamin.gaignard@st.com>, <linux-iio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>,\n\t<vilhelm.gray@gmail.com>", "Subject": "[RESEND PATCH v3 9/9] iio: adc: stm32: add support for lptimer\n\ttriggers", "Date": "Mon, 28 Aug 2017 12:04:14 +0200", "Message-ID": "<1503914654-19963-10-git-send-email-fabrice.gasnier@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "References": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.75.127.48]", "X-ClientProxiedBy": "SFHDAG6NODE1.st.com (10.75.127.16) To SFHDAG5NODE3.st.com\n\t(10.75.127.15)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_06:, , signatures=0", "Sender": "linux-pwm-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pwm.vger.kernel.org>", "X-Mailing-List": "linux-pwm@vger.kernel.org" }, "content": "STM32 ADC supports hardware triggers like STM32 Low-Power Timer.\nFor instance, STM32H7 ADC may be triggered by instances 1, 2 or 3.\nAdd hardware triggered mode so Low-Power Timer Trigger driver can\nvalidate device.\n\nSigned-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>\nAcked-by: Jonathan Cameron <jic23@kernel.org>\n---\n drivers/iio/adc/stm32-adc.c | 14 ++++++++++++--\n 1 file changed, 12 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c\nindex 5bfcc1f..1147d7e 100644\n--- a/drivers/iio/adc/stm32-adc.c\n+++ b/drivers/iio/adc/stm32-adc.c\n@@ -25,6 +25,7 @@\n #include <linux/dmaengine.h>\n #include <linux/iio/iio.h>\n #include <linux/iio/buffer.h>\n+#include <linux/iio/timer/stm32-lptim-trigger.h>\n #include <linux/iio/timer/stm32-timer-trigger.h>\n #include <linux/iio/trigger.h>\n #include <linux/iio/trigger_consumer.h>\n@@ -182,6 +183,11 @@ enum stm32_adc_extsel {\n \tSTM32_EXT13,\n \tSTM32_EXT14,\n \tSTM32_EXT15,\n+\tSTM32_EXT16,\n+\tSTM32_EXT17,\n+\tSTM32_EXT18,\n+\tSTM32_EXT19,\n+\tSTM32_EXT20,\n };\n \n /**\n@@ -480,6 +486,9 @@ struct stm32_adc_info {\n \t{ TIM4_TRGO, STM32_EXT12 },\n \t{ TIM6_TRGO, STM32_EXT13 },\n \t{ TIM3_CH4, STM32_EXT15 },\n+\t{ LPTIM1_OUT, STM32_EXT18 },\n+\t{ LPTIM2_OUT, STM32_EXT19 },\n+\t{ LPTIM3_OUT, STM32_EXT20 },\n \t{},\n };\n \n@@ -995,7 +1004,8 @@ static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,\n \t\t * Checking both stm32 timer trigger type and trig name\n \t\t * should be safe against arbitrary trigger names.\n \t\t */\n-\t\tif (is_stm32_timer_trigger(trig) &&\n+\t\tif ((is_stm32_timer_trigger(trig) ||\n+\t\t is_stm32_lptim_trigger(trig)) &&\n \t\t !strcmp(adc->cfg->trigs[i].name, trig->name)) {\n \t\t\treturn adc->cfg->trigs[i].extsel;\n \t\t}\n@@ -1634,7 +1644,7 @@ static int stm32_adc_probe(struct platform_device *pdev)\n \tindio_dev->dev.parent = &pdev->dev;\n \tindio_dev->dev.of_node = pdev->dev.of_node;\n \tindio_dev->info = &stm32_adc_iio_info;\n-\tindio_dev->modes = INDIO_DIRECT_MODE;\n+\tindio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;\n \n \tplatform_set_drvdata(pdev, adc);\n \n", "prefixes": [ "RESEND", "v3", "9/9" ] }