Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/806468/?format=api
{ "id": 806468, "url": "http://patchwork.ozlabs.org/api/patches/806468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/1503914654-19963-9-git-send-email-fabrice.gasnier@st.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503914654-19963-9-git-send-email-fabrice.gasnier@st.com>", "list_archive_url": null, "date": "2017-08-28T10:04:13", "name": "[RESEND,v3,8/9] iio: counter: Add support for STM32 LPTimer", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "cfe2714bddba6457554c471de5dd93135138e608", "submitter": { "id": 65902, "url": "http://patchwork.ozlabs.org/api/people/65902/?format=api", "name": "Fabrice Gasnier", "email": "fabrice.gasnier@st.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/1503914654-19963-9-git-send-email-fabrice.gasnier@st.com/mbox/", "series": [ { "id": 122, "url": "http://patchwork.ozlabs.org/api/series/122/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=122", "date": "2017-08-28T10:04:06", "name": "Add STM32 LPTimer: PWM, trigger and counter", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/122/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806468/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pwm-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pwm-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgnTX5lbKz9sPk\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 20:05:52 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751763AbdH1KFh (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 06:05:37 -0400", "from mx08-00178001.pphosted.com ([91.207.212.93]:33126 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751755AbdH1KFf (ORCPT\n\t<rfc822; linux-pwm@vger.kernel.org>); Mon, 28 Aug 2017 06:05:35 -0400", "from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7SA3m5e004998; Mon, 28 Aug 2017 12:04:43 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-.pphosted.com with ESMTP id 2cjx459ns8-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tMon, 28 Aug 2017 12:04:43 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 189DB49;\n\tMon, 28 Aug 2017 10:04:41 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8B53923DC;\n\tMon, 28 Aug 2017 10:04:41 +0000 (GMT)", "from localhost (10.75.127.50) by SFHDAG5NODE3.st.com (10.75.127.15)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tMon, 28 Aug 2017 12:04:40 +0200" ], "From": "Fabrice Gasnier <fabrice.gasnier@st.com>", "To": "<lee.jones@linaro.org>, <benjamin.gaignard@linaro.org>,\n\t<jic23@kernel.org>, <thierry.reding@gmail.com>, <robh+dt@kernel.org>", "CC": "<mark.rutland@arm.com>, <alexandre.torgue@st.com>,\n\t<mcoquelin.stm32@gmail.com>, <fabrice.gasnier@st.com>,\n\t<benjamin.gaignard@st.com>, <linux-iio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>,\n\t<vilhelm.gray@gmail.com>", "Subject": "[RESEND PATCH v3 8/9] iio: counter: Add support for STM32 LPTimer", "Date": "Mon, 28 Aug 2017 12:04:13 +0200", "Message-ID": "<1503914654-19963-9-git-send-email-fabrice.gasnier@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "References": "<1503914654-19963-1-git-send-email-fabrice.gasnier@st.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.75.127.50]", "X-ClientProxiedBy": "SFHDAG3NODE2.st.com (10.75.127.8) To SFHDAG5NODE3.st.com\n\t(10.75.127.15)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_06:, , signatures=0", "Sender": "linux-pwm-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pwm.vger.kernel.org>", "X-Mailing-List": "linux-pwm@vger.kernel.org" }, "content": "Add support for STM32 Low-Power Timer, that can be used as counter\nor quadrature encoder.\n\nSigned-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>\nReviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>\n---\nChanges in v2:\n- s/Low Power/Low-Power\n- update few comments\n---\n .../ABI/testing/sysfs-bus-iio-lptimer-stm32 | 57 +++\n drivers/iio/counter/Kconfig | 9 +\n drivers/iio/counter/Makefile | 1 +\n drivers/iio/counter/stm32-lptimer-cnt.c | 383 +++++++++++++++++++++\n 4 files changed, 450 insertions(+)\n create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32\n create mode 100644 drivers/iio/counter/stm32-lptimer-cnt.c", "diff": "diff --git a/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32\nnew file mode 100644\nindex 0000000..ad2cc63\n--- /dev/null\n+++ b/Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32\n@@ -0,0 +1,57 @@\n+What:\t\t/sys/bus/iio/devices/iio:deviceX/in_count0_preset\n+KernelVersion:\t4.13\n+Contact:\tfabrice.gasnier@st.com\n+Description:\n+\t\tReading returns the current preset value. Writing sets the\n+\t\tpreset value. Encoder counts continuously from 0 to preset\n+\t\tvalue, depending on direction (up/down).\n+\n+What:\t\t/sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available\n+KernelVersion:\t4.13\n+Contact:\tfabrice.gasnier@st.com\n+Description:\n+\t\tReading returns the list possible quadrature modes.\n+\n+What:\t\t/sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode\n+KernelVersion:\t4.13\n+Contact:\tfabrice.gasnier@st.com\n+Description:\n+\t\tConfigure the device counter quadrature modes:\n+\t\t- non-quadrature:\n+\t\t\tEncoder IN1 input servers as the count input (up\n+\t\t\tdirection).\n+\t\t- quadrature:\n+\t\t\tEncoder IN1 and IN2 inputs are mixed to get direction\n+\t\t\tand count.\n+\n+What:\t\t/sys/bus/iio/devices/iio:deviceX/in_count_polarity_available\n+KernelVersion:\t4.13\n+Contact:\tfabrice.gasnier@st.com\n+Description:\n+\t\tReading returns the list possible active edges.\n+\n+What:\t\t/sys/bus/iio/devices/iio:deviceX/in_count0_polarity\n+KernelVersion:\t4.13\n+Contact:\tfabrice.gasnier@st.com\n+Description:\n+\t\tConfigure the device encoder/counter active edge:\n+\t\t- rising-edge\n+\t\t- falling-edge\n+\t\t- both-edges\n+\n+\t\tIn non-quadrature mode, device counts up on active edge.\n+\t\tIn quadrature mode, encoder counting scenarios are as follows:\n+\t\t----------------------------------------------------------------\n+\t\t| Active | Level on | IN1 signal | IN2 signal |\n+\t\t| edge | opposite |------------------------------------------\n+\t\t| | signal | Rising | Falling | Rising | Falling |\n+\t\t----------------------------------------------------------------\n+\t\t| Rising | High -> | Down | - | Up | - |\n+\t\t| edge | Low -> | Up | - | Down | - |\n+\t\t----------------------------------------------------------------\n+\t\t| Falling | High -> | - | Up | - | Down |\n+\t\t| edge | Low -> | - | Down | - | Up |\n+\t\t----------------------------------------------------------------\n+\t\t| Both | High -> | Down | Up | Up | Down |\n+\t\t| edges | Low -> | Up | Down | Down | Up |\n+\t\t----------------------------------------------------------------\ndiff --git a/drivers/iio/counter/Kconfig b/drivers/iio/counter/Kconfig\nindex b37e5fc..474e1ac 100644\n--- a/drivers/iio/counter/Kconfig\n+++ b/drivers/iio/counter/Kconfig\n@@ -21,4 +21,13 @@ config 104_QUAD_8\n \t The base port addresses for the devices may be configured via the base\n \t array module parameter.\n \n+config STM32_LPTIMER_CNT\n+\ttristate \"STM32 LP Timer encoder counter driver\"\n+\tdepends on MFD_STM32_LPTIMER || COMPILE_TEST\n+\thelp\n+\t Select this option to enable STM32 Low-Power Timer quadrature encoder\n+\t and counter driver.\n+\n+\t To compile this driver as a module, choose M here: the\n+\t module will be called stm32-lptimer-cnt.\n endmenu\ndiff --git a/drivers/iio/counter/Makefile b/drivers/iio/counter/Makefile\nindex 007e884..1b9a896 100644\n--- a/drivers/iio/counter/Makefile\n+++ b/drivers/iio/counter/Makefile\n@@ -5,3 +5,4 @@\n # When adding new entries keep the list in alphabetical order\n \n obj-$(CONFIG_104_QUAD_8)\t+= 104-quad-8.o\n+obj-$(CONFIG_STM32_LPTIMER_CNT)\t+= stm32-lptimer-cnt.o\ndiff --git a/drivers/iio/counter/stm32-lptimer-cnt.c b/drivers/iio/counter/stm32-lptimer-cnt.c\nnew file mode 100644\nindex 0000000..1c5909b\n--- /dev/null\n+++ b/drivers/iio/counter/stm32-lptimer-cnt.c\n@@ -0,0 +1,383 @@\n+/*\n+ * STM32 Low-Power Timer Encoder and Counter driver\n+ *\n+ * Copyright (C) STMicroelectronics 2017\n+ *\n+ * Author: Fabrice Gasnier <fabrice.gasnier@st.com>\n+ *\n+ * Inspired by 104-quad-8 and stm32-timer-trigger drivers.\n+ *\n+ * License terms: GNU General Public License (GPL), version 2\n+ */\n+\n+#include <linux/bitfield.h>\n+#include <linux/iio/iio.h>\n+#include <linux/mfd/stm32-lptimer.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+struct stm32_lptim_cnt {\n+\tstruct device *dev;\n+\tstruct regmap *regmap;\n+\tstruct clk *clk;\n+\tu32 preset;\n+\tu32 polarity;\n+\tu32 quadrature_mode;\n+};\n+\n+static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)\n+{\n+\tu32 val;\n+\tint ret;\n+\n+\tret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn FIELD_GET(STM32_LPTIM_ENABLE, val);\n+}\n+\n+static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,\n+\t\t\t\t\tint enable)\n+{\n+\tint ret;\n+\tu32 val;\n+\n+\tval = FIELD_PREP(STM32_LPTIM_ENABLE, enable);\n+\tret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!enable) {\n+\t\tclk_disable(priv->clk);\n+\t\treturn 0;\n+\t}\n+\n+\t/* LP timer must be enabled before writing CMP & ARR */\n+\tret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->preset);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* ensure CMP & ARR registers are properly written */\n+\tret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,\n+\t\t\t\t (val & STM32_LPTIM_CMPOK_ARROK),\n+\t\t\t\t 100, 1000);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(priv->regmap, STM32_LPTIM_ICR,\n+\t\t\t STM32_LPTIM_CMPOKCF_ARROKCF);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = clk_enable(priv->clk);\n+\tif (ret) {\n+\t\tregmap_write(priv->regmap, STM32_LPTIM_CR, 0);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Start LP timer in continuous mode */\n+\treturn regmap_update_bits(priv->regmap, STM32_LPTIM_CR,\n+\t\t\t\t STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);\n+}\n+\n+static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)\n+{\n+\tu32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |\n+\t\t STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;\n+\tu32 val;\n+\n+\t/* Setup LP timer encoder/counter and polarity, without prescaler */\n+\tif (priv->quadrature_mode)\n+\t\tval = enable ? STM32_LPTIM_ENC : 0;\n+\telse\n+\t\tval = enable ? STM32_LPTIM_COUNTMODE : 0;\n+\tval |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);\n+\n+\treturn regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);\n+}\n+\n+static int stm32_lptim_write_raw(struct iio_dev *indio_dev,\n+\t\t\t\t struct iio_chan_spec const *chan,\n+\t\t\t\t int val, int val2, long mask)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tswitch (mask) {\n+\tcase IIO_CHAN_INFO_ENABLE:\n+\t\tif (val < 0 || val > 1)\n+\t\t\treturn -EINVAL;\n+\n+\t\t/* Check nobody uses the timer, or already disabled/enabled */\n+\t\tret = stm32_lptim_is_enabled(priv);\n+\t\tif ((ret < 0) || (!ret && !val))\n+\t\t\treturn ret;\n+\t\tif (val && ret)\n+\t\t\treturn -EBUSY;\n+\n+\t\tret = stm32_lptim_setup(priv, val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\treturn stm32_lptim_set_enable_state(priv, val);\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int stm32_lptim_read_raw(struct iio_dev *indio_dev,\n+\t\t\t\tstruct iio_chan_spec const *chan,\n+\t\t\t\tint *val, int *val2, long mask)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\tu32 dat;\n+\tint ret;\n+\n+\tswitch (mask) {\n+\tcase IIO_CHAN_INFO_RAW:\n+\t\tret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*val = dat;\n+\t\treturn IIO_VAL_INT;\n+\n+\tcase IIO_CHAN_INFO_ENABLE:\n+\t\tret = stm32_lptim_is_enabled(priv);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\t*val = ret;\n+\t\treturn IIO_VAL_INT;\n+\n+\tcase IIO_CHAN_INFO_SCALE:\n+\t\t/* Non-quadrature mode: scale = 1 */\n+\t\t*val = 1;\n+\t\t*val2 = 0;\n+\t\tif (priv->quadrature_mode) {\n+\t\t\t/*\n+\t\t\t * Quadrature encoder mode:\n+\t\t\t * - both edges, quarter cycle, scale is 0.25\n+\t\t\t * - either rising/falling edge scale is 0.5\n+\t\t\t */\n+\t\t\tif (priv->polarity > 1)\n+\t\t\t\t*val2 = 2;\n+\t\t\telse\n+\t\t\t\t*val2 = 1;\n+\t\t}\n+\t\treturn IIO_VAL_FRACTIONAL_LOG2;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static const struct iio_info stm32_lptim_cnt_iio_info = {\n+\t.read_raw = stm32_lptim_read_raw,\n+\t.write_raw = stm32_lptim_write_raw,\n+\t.driver_module = THIS_MODULE,\n+};\n+\n+static const char *const stm32_lptim_quadrature_modes[] = {\n+\t\"non-quadrature\",\n+\t\"quadrature\",\n+};\n+\n+static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev,\n+\t\t\t\t\t const struct iio_chan_spec *chan)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\n+\treturn priv->quadrature_mode;\n+}\n+\n+static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev,\n+\t\t\t\t\t const struct iio_chan_spec *chan,\n+\t\t\t\t\t unsigned int type)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\n+\tif (stm32_lptim_is_enabled(priv))\n+\t\treturn -EBUSY;\n+\n+\tpriv->quadrature_mode = type;\n+\n+\treturn 0;\n+}\n+\n+static const struct iio_enum stm32_lptim_quadrature_mode_en = {\n+\t.items = stm32_lptim_quadrature_modes,\n+\t.num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes),\n+\t.get = stm32_lptim_get_quadrature_mode,\n+\t.set = stm32_lptim_set_quadrature_mode,\n+};\n+\n+static const char * const stm32_lptim_cnt_polarity[] = {\n+\t\"rising-edge\", \"falling-edge\", \"both-edges\",\n+};\n+\n+static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev,\n+\t\t\t\t\tconst struct iio_chan_spec *chan)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\n+\treturn priv->polarity;\n+}\n+\n+static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev,\n+\t\t\t\t\tconst struct iio_chan_spec *chan,\n+\t\t\t\t\tunsigned int type)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\n+\tif (stm32_lptim_is_enabled(priv))\n+\t\treturn -EBUSY;\n+\n+\tpriv->polarity = type;\n+\n+\treturn 0;\n+}\n+\n+static const struct iio_enum stm32_lptim_cnt_polarity_en = {\n+\t.items = stm32_lptim_cnt_polarity,\n+\t.num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity),\n+\t.get = stm32_lptim_cnt_get_polarity,\n+\t.set = stm32_lptim_cnt_set_polarity,\n+};\n+\n+static ssize_t stm32_lptim_cnt_get_preset(struct iio_dev *indio_dev,\n+\t\t\t\t\t uintptr_t private,\n+\t\t\t\t\t const struct iio_chan_spec *chan,\n+\t\t\t\t\t char *buf)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\n+\treturn snprintf(buf, PAGE_SIZE, \"%u\\n\", priv->preset);\n+}\n+\n+static ssize_t stm32_lptim_cnt_set_preset(struct iio_dev *indio_dev,\n+\t\t\t\t\t uintptr_t private,\n+\t\t\t\t\t const struct iio_chan_spec *chan,\n+\t\t\t\t\t const char *buf, size_t len)\n+{\n+\tstruct stm32_lptim_cnt *priv = iio_priv(indio_dev);\n+\tint ret;\n+\n+\tif (stm32_lptim_is_enabled(priv))\n+\t\treturn -EBUSY;\n+\n+\tret = kstrtouint(buf, 0, &priv->preset);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (priv->preset > STM32_LPTIM_MAX_ARR)\n+\t\treturn -EINVAL;\n+\n+\treturn len;\n+}\n+\n+/* LP timer with encoder */\n+static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {\n+\t{\n+\t\t.name = \"preset\",\n+\t\t.shared = IIO_SEPARATE,\n+\t\t.read = stm32_lptim_cnt_get_preset,\n+\t\t.write = stm32_lptim_cnt_set_preset,\n+\t},\n+\tIIO_ENUM(\"polarity\", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),\n+\tIIO_ENUM_AVAILABLE(\"polarity\", &stm32_lptim_cnt_polarity_en),\n+\tIIO_ENUM(\"quadrature_mode\", IIO_SEPARATE,\n+\t\t &stm32_lptim_quadrature_mode_en),\n+\tIIO_ENUM_AVAILABLE(\"quadrature_mode\", &stm32_lptim_quadrature_mode_en),\n+\t{}\n+};\n+\n+static const struct iio_chan_spec stm32_lptim_enc_channels = {\n+\t.type = IIO_COUNT,\n+\t.channel = 0,\n+\t.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |\n+\t\t\t BIT(IIO_CHAN_INFO_ENABLE) |\n+\t\t\t BIT(IIO_CHAN_INFO_SCALE),\n+\t.ext_info = stm32_lptim_enc_ext_info,\n+\t.indexed = 1,\n+};\n+\n+/* LP timer without encoder (counter only) */\n+static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {\n+\t{\n+\t\t.name = \"preset\",\n+\t\t.shared = IIO_SEPARATE,\n+\t\t.read = stm32_lptim_cnt_get_preset,\n+\t\t.write = stm32_lptim_cnt_set_preset,\n+\t},\n+\tIIO_ENUM(\"polarity\", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),\n+\tIIO_ENUM_AVAILABLE(\"polarity\", &stm32_lptim_cnt_polarity_en),\n+\t{}\n+};\n+\n+static const struct iio_chan_spec stm32_lptim_cnt_channels = {\n+\t.type = IIO_COUNT,\n+\t.channel = 0,\n+\t.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |\n+\t\t\t BIT(IIO_CHAN_INFO_ENABLE) |\n+\t\t\t BIT(IIO_CHAN_INFO_SCALE),\n+\t.ext_info = stm32_lptim_cnt_ext_info,\n+\t.indexed = 1,\n+};\n+\n+static int stm32_lptim_cnt_probe(struct platform_device *pdev)\n+{\n+\tstruct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);\n+\tstruct stm32_lptim_cnt *priv;\n+\tstruct iio_dev *indio_dev;\n+\n+\tif (IS_ERR_OR_NULL(ddata))\n+\t\treturn -EINVAL;\n+\n+\tindio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));\n+\tif (!indio_dev)\n+\t\treturn -ENOMEM;\n+\n+\tpriv = iio_priv(indio_dev);\n+\tpriv->dev = &pdev->dev;\n+\tpriv->regmap = ddata->regmap;\n+\tpriv->clk = ddata->clk;\n+\tpriv->preset = STM32_LPTIM_MAX_ARR;\n+\n+\tindio_dev->name = dev_name(&pdev->dev);\n+\tindio_dev->dev.parent = &pdev->dev;\n+\tindio_dev->dev.of_node = pdev->dev.of_node;\n+\tindio_dev->info = &stm32_lptim_cnt_iio_info;\n+\tif (ddata->has_encoder)\n+\t\tindio_dev->channels = &stm32_lptim_enc_channels;\n+\telse\n+\t\tindio_dev->channels = &stm32_lptim_cnt_channels;\n+\tindio_dev->num_channels = 1;\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\treturn devm_iio_device_register(&pdev->dev, indio_dev);\n+}\n+\n+static const struct of_device_id stm32_lptim_cnt_of_match[] = {\n+\t{ .compatible = \"st,stm32-lptimer-counter\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);\n+\n+static struct platform_driver stm32_lptim_cnt_driver = {\n+\t.probe = stm32_lptim_cnt_probe,\n+\t.driver = {\n+\t\t.name = \"stm32-lptimer-counter\",\n+\t\t.of_match_table = stm32_lptim_cnt_of_match,\n+\t},\n+};\n+module_platform_driver(stm32_lptim_cnt_driver);\n+\n+MODULE_AUTHOR(\"Fabrice Gasnier <fabrice.gasnier@st.com>\");\n+MODULE_ALIAS(\"platform:stm32-lptimer-counter\");\n+MODULE_DESCRIPTION(\"STMicroelectronics STM32 LPTIM counter driver\");\n+MODULE_LICENSE(\"GPL v2\");\n", "prefixes": [ "RESEND", "v3", "8/9" ] }