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GET /api/patches/806458/?format=api
{ "id": 806458, "url": "http://patchwork.ozlabs.org/api/patches/806458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170828091533.15133-4-ran.wang_1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828091533.15133-4-ran.wang_1@nxp.com>", "list_archive_url": null, "date": "2017-08-28T09:15:29", "name": "[U-Boot,v4,4/8] armv8: Add workaround for USB erratum A-009007", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "bff937ab194eeb0ba9b0f50e666efd12dd95a8e4", "submitter": { "id": 71939, "url": "http://patchwork.ozlabs.org/api/people/71939/?format=api", "name": "Ran Wang", "email": "ran.wang_1@nxp.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170828091533.15133-4-ran.wang_1@nxp.com/mbox/", "series": [ { "id": 118, "url": "http://patchwork.ozlabs.org/api/series/118/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=118", "date": "2017-08-28T09:15:26", "name": "[U-Boot,v4,1/8] armv8: Add workaround for USB erratum A-009008", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/118/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806458/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806458/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 28 Aug 2017 09:32:52 +0000 (UTC)", "from CY4PR03CA0008.namprd03.prod.outlook.com (10.168.162.18) by\n\tMWHPR03MB3326.namprd03.prod.outlook.com (10.174.249.144) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1385.9; Mon, 28 Aug 2017 09:32:50 +0000", "from BN1BFFO11FD043.protection.gbl (2a01:111:f400:7c10::1:166) by\n\tCY4PR03CA0008.outlook.office365.com (2603:10b6:903:33::18) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1362.18\n\tvia Frontend Transport; Mon, 28 Aug 2017 09:32:50 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1BFFO11FD043.mail.protection.outlook.com (10.58.144.106) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.1341.15 via Frontend Transport; Mon, 28 Aug 2017 09:32:49 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv7S9WYom028765; Mon, 28 Aug 2017 02:32:46 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tSPF_HELO_PASS\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Ran Wang <ran.wang_1@nxp.com>", "To": "open list <u-boot@lists.denx.de>, York Sun <york.sun@nxp.com>", "Date": "Mon, 28 Aug 2017 17:15:29 +0800", "Message-ID": "<20170828091533.15133-4-ran.wang_1@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170828091533.15133-1-ran.wang_1@nxp.com>", "References": "<20170828091533.15133-1-ran.wang_1@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131483863702175160;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:MWHPR03MB3326; ", "X-MS-TrafficTypeDiagnostic": "MWHPR03MB3326:", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Microsoft-Antispam-PRVS": "<MWHPR03MB3326417D45049290C1648BF2F19E0@MWHPR03MB3326.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(601004)(2401047)(13018025)(8121501046)(13016025)(5005006)(93006095)(93001095)(3002001)(100000703101)(100105400095)(10201501046)(6055026)(6096035)(20161123561025)(20161123559100)(20161123565025)(20161123563025)(20161123556025)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR03MB3326; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR03MB3326; ", "X-Forefront-PRVS": "0413C9F1ED", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Aug 2017 09:32:49.8743\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR03MB3326", "Cc": "Priyanka Jain <priyanka.jain@nxp.com>,\n\tSuresh Gupta <suresh.bhagat@nxp.com>, ran.wang_1@nxp.com", "Subject": "[U-Boot] [PATCH v4 4/8] armv8: Add workaround for USB erratum\n\tA-009007", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Rx Compliance tests may fail intermittently at high\njitter frequencies using default register values.\n\nProgram register USB_PHY_RX_OVRD_IN_HI in certain sequence\nto make the Rx compliance test pass.\n\nSigned-off-by: Sriram Dash <sriram.dash@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Suresh Gupta <suresh.bhagat@nxp.com>\nSigned-off-by: Ran Wang <ran.wang_1@nxp.com>\n---\nChange in v4:\n\tUpdate commit message about register setting.\n\tRename some registers which belong to SCFG.\n\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009007():\n\t1.Put a blank line after variable declaration.\n\t2.Create a mcro to run for each USB for easier to read and maintain.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++++-\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 40 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++\n 4 files changed, 68 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 9449d629ea..c5c5f4e130 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -25,6 +25,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -50,6 +51,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -89,6 +91,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -239,7 +242,14 @@ config SYS_FSL_ERRATUM_A009798\n \tbool \"Workaround for USB PHY erratum A009798\"\n \n config SYS_FSL_ERRATUM_A008997\n-\tbool \"Workaround for USB PHY erratum A008997\"\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A008997\n+\n+config SYS_FSL_ERRATUM_A009007\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A009007\n \n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 78be5853cb..f92ff7733c 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -126,6 +126,44 @@ static void erratum_a008997(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */\n }\n \n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);\t\\\n+\tout_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#endif\n+\n+static void erratum_a009007(void)\n+{\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tvoid __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)SCFG_USB_PHY2;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)SCFG_USB_PHY3;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tvoid __iomem *dcsr = (void __iomem *)DCSR_BASE;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -275,6 +313,7 @@ void fsl_lsch3_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -553,6 +592,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 1601ec6baa..130dc4bfbe 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -348,6 +348,14 @@ struct ccsr_gur {\n #define SCFG_USB_TXVREFTUNE\t\t\t0x9\n #define SCFG_USB_SQRXTUNE_MASK\t\t0x7\n #define SCFG_USB_PCSTXSWINGFULL\t\t0x47\n+#define SCFG_USB_PHY1\t\t\t0x084F0000\n+#define SCFG_USB_PHY2\t\t\t0x08500000\n+#define SCFG_USB_PHY3\t\t\t0x08510000\n+#define SCFG_USB_PHY_RX_OVRD_IN_HI\t\t0x200c\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n \n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 3b2e9eaa8b..3e03d7b4c3 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -137,6 +137,15 @@\n #define SCFG_USB_SQRXTUNE_MASK\t0x7\n #define SCFG_QSPICLKCTLR\t0x10\n \n+#define DCSR_BASE\t\t0x700000000ULL\n+#define DCSR_USB_PHY1\t\t\t0x4600000\n+#define DCSR_USB_PHY2\t\t\t0x4610000\n+#define DCSR_USB_PHY_RX_OVRD_IN_HI\t0x200C\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n+\n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n #define TP_ITYP_TYPE(x)\t(((x) & 0x6) >> 1)\t/* Initiator Type */\n #define TP_ITYP_TYPE_ARM\t0x0\n", "prefixes": [ "U-Boot", "v4", "4/8" ] }