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{ "id": 806438, "url": "http://patchwork.ozlabs.org/api/patches/806438/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/87o9r0t7wt.fsf@linaro.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<87o9r0t7wt.fsf@linaro.org>", "list_archive_url": null, "date": "2017-08-28T08:26:26", "name": "Add wider_subreg_mode helper functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "77fa6f3f55c500c992a56e010917e70c08aea0ef", "submitter": { "id": 5450, "url": "http://patchwork.ozlabs.org/api/people/5450/?format=api", "name": "Richard Sandiford", "email": "richard.sandiford@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/87o9r0t7wt.fsf@linaro.org/mbox/", "series": [ { "id": 103, "url": "http://patchwork.ozlabs.org/api/series/103/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=103", "date": "2017-08-28T08:26:26", "name": "Add wider_subreg_mode helper functions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/103/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806438/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806438/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-460998-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; 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Mon, 28 Aug 2017 01:26:22 -0700 (PDT)", "from localhost ([95.145.139.63]) by smtp.gmail.com with ESMTPSA id\n\tp4sm9321085wrd.50.2017.08.28.01.26.18 for\n\t<gcc-patches@gcc.gnu.org> (version=TLS1_2\n\tcipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 28 Aug 2017 01:26:19 -0700 (PDT)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:date:message-id:mime-version:content-type; q=dns; s=\n\tdefault; b=MJvKC+eVk8y/XVtfASch6NAsmWsVU2dw0hTCkvHsp3EOu1OgU41jK\n\tPfH2OlLipiS8Av4Z/wYbVv0pqy8qzMtWo5VDTRpi5qDNixNZLzz9sklY2D+xgi2r\n\tSbU4SP0QxtppP2XkjFdQk/wOWSR36TjwVU+Ym8WJB3n7OXgQYjHUQc=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:from\n\t:to:subject:date:message-id:mime-version:content-type; s=\n\tdefault; bh=ufkluHz+mkg7F6JtDJR95VUFobc=; b=FOv3KpCqt04SXemtOGJ/\n\tGV5mupoV9g5ILVf3ufj3ig5rV5lFCCwAbMJiMIX1Z8pOXUVkGONjTY+szFrvDPxh\n\tK8JvBSD80MbaX+7UEirBnfEVr7BTiNqqc6zlN/NniXQR6sO5nR/YODuWhuit8uI8\n\t4PqYm/Zucqy0SL/Fp4WsZQ4=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-11.0 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "mail-wm0-f47.google.com", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id\n\t:user-agent:mime-version;\n\tbh=oxgA68k1PPSSZ/hFuw/n37IPUHq3S8EPqmqqa3iTZA4=;\n\tb=BxQIhHadM01BzprXz5l/5zY+il9EkTXt7SU2Iq3qcaTokxK8i/4kuUtA7rDWIwqAmG\n\t5J1CC9Jd7Dkxs5Trc8PuN41aZKekJ+2VfUtdGf4Hp3ywbdE6dXnpURgiIp82NET5WSdR\n\tM6wrTMFXrQq60lOiKirwsBq6jKz3M6+MBNJ+ZrUW3RADkS2KJ+Pk2Wiazi/YzxpsriTq\n\tbLqnNa8PNMu3cWiFtXYS1wpN5z8KW7dlx6i4iVyW7nBRCYJywehw4FywmGMGeobDXeX1\n\tMOOjkOiUhOQlJhA/0zPrvQJ4WdJFMAjJSCAwcfKKyLkc08AbaRF3YwitdpqSotU7IeXO\n\ttHMA==", "X-Gm-Message-State": "AHYfb5gZOGAaCRJSfM8nLX7DY4/wpp9ZolA4JzNl/rO5QKFr9INGRygz\tsu2MbBTn+hfuxT+YDoPKsQ==", "X-Received": "by 10.28.150.215 with SMTP id y206mr3004887wmd.164.1503908780158;\n\tMon, 28 Aug 2017 01:26:20 -0700 (PDT)", "From": "Richard Sandiford <richard.sandiford@linaro.org>", "To": "gcc-patches@gcc.gnu.org", "Mail-Followup-To": "gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org", "Subject": "Add wider_subreg_mode helper functions", "Date": "Mon, 28 Aug 2017 09:26:26 +0100", "Message-ID": "<87o9r0t7wt.fsf@linaro.org>", "User-Agent": "Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux)", "MIME-Version": "1.0", "Content-Type": "text/plain" }, "content": "This patch adds helper functions that say which of the two modes\ninvolved in a subreg is the larger, preferring the outer mode in\nthe event of a tie. It also converts IRA and reload to track modes\ninstead of byte sizes, since this is slightly more convenient when\nvariable-sized modes are added later.\n\nTested on aarch64-linux-gnu and x86_64-linux-gnu, and by checking\nthere was no change in the testsuite assembly output for at least\none target per CPU. OK to install?\n\nRichard\n\n\n2017-08-28 Richard Sandiford <richard.sandiford@linaro.org>\n\t Alan Hayward <alan.hayward@arm.com>\n\t David Sherwood <david.sherwood@arm.com>\n\ngcc/\n\t* rtl.h (wider_subreg_mode): New function.\n\t* ira.h (ira_sort_regnos_for_alter_reg): Take a machine_mode *\n\trather than an unsigned int *.\n\t* ira-color.c (regno_max_ref_width): Replace with...\n\t(regno_max_ref_mode): ...this new variable.\n\t(coalesced_pseudo_reg_slot_compare): Update accordingly.\n\tUse wider_subreg_mode.\n\t(ira_sort_regnos_for_alter_reg): Likewise. Take a machine_mode *\n\trather than an unsigned int *.\n\t* lra-constraints.c (uses_hard_regs_p): Use wider_subreg_mode.\n\t(process_alt_operands): Likewise.\n\t(invariant_p): Likewise.\n\t* lra-spills.c (assign_mem_slot): Likewise.\n\t(add_pseudo_to_slot): Likewise.\n\t* lra.c (collect_non_operand_hard_regs): Likewise.\n\t(add_regs_to_insn_regno_info): Likewise.\n\t* reload1.c (regno_max_ref_width): Replace with...\n\t(regno_max_ref_mode): ...this new variable.\n\t(reload): Update accordingly. Update call to\n\tira_sort_regnos_for_alter_reg.\n\t(alter_reg): Update to use regno_max_ref_mode. Call wider_subreg_mode.\n\t(init_eliminable_invariants): Update to use regno_max_ref_mode.\n\t(scan_paradoxical_subregs): Likewise.", "diff": "Index: gcc/rtl.h\n===================================================================\n--- gcc/rtl.h\t2017-08-28 09:23:51.181220876 +0100\n+++ gcc/rtl.h\t2017-08-28 09:23:56.230220860 +0100\n@@ -2840,6 +2840,24 @@ subreg_lowpart_offset (machine_mode oute\n \t\t\t\t GET_MODE_SIZE (innermode));\n }\n \n+/* Given that a subreg has outer mode OUTERMODE and inner mode INNERMODE,\n+ return the mode that is big enough to hold both the outer and inner\n+ values. Prefer the outer mode in the event of a tie. */\n+\n+inline machine_mode\n+wider_subreg_mode (machine_mode outermode, machine_mode innermode)\n+{\n+ return partial_subreg_p (outermode, innermode) ? innermode : outermode;\n+}\n+\n+/* Likewise for subreg X. */\n+\n+inline machine_mode\n+wider_subreg_mode (const_rtx x)\n+{\n+ return wider_subreg_mode (GET_MODE (x), GET_MODE (SUBREG_REG (x)));\n+}\n+\n extern unsigned int subreg_size_highpart_offset (unsigned int, unsigned int);\n \n /* Return the SUBREG_BYTE for an OUTERMODE highpart of an INNERMODE value. */\nIndex: gcc/ira.h\n===================================================================\n--- gcc/ira.h\t2017-08-28 09:22:51.676686496 +0100\n+++ gcc/ira.h\t2017-08-28 09:23:56.227520860 +0100\n@@ -195,7 +195,7 @@ extern void ira_set_pseudo_classes (bool\n extern void ira_expand_reg_equiv (void);\n extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);\n \n-extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);\n+extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *);\n extern void ira_mark_allocation_change (int);\n extern void ira_mark_memory_move_deletion (int, int);\n extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,\nIndex: gcc/ira-color.c\n===================================================================\n--- gcc/ira-color.c\t2017-08-28 09:22:51.676686496 +0100\n+++ gcc/ira-color.c\t2017-08-28 09:23:56.226620860 +0100\n@@ -3908,7 +3908,7 @@ coalesced_pseudo_reg_freq_compare (const\n \n /* Widest width in which each pseudo reg is referred to (via subreg).\n It is used for sorting pseudo registers. */\n-static unsigned int *regno_max_ref_width;\n+static machine_mode *regno_max_ref_mode;\n \n /* Sort pseudos according their slot numbers (putting ones with\n smaller numbers first, or last when the frame pointer is not\n@@ -3921,7 +3921,7 @@ coalesced_pseudo_reg_slot_compare (const\n ira_allocno_t a1 = ira_regno_allocno_map[regno1];\n ira_allocno_t a2 = ira_regno_allocno_map[regno2];\n int diff, slot_num1, slot_num2;\n- int total_size1, total_size2;\n+ machine_mode mode1, mode2;\n \n if (a1 == NULL || ALLOCNO_HARD_REGNO (a1) >= 0)\n {\n@@ -3936,11 +3936,11 @@ coalesced_pseudo_reg_slot_compare (const\n if ((diff = slot_num1 - slot_num2) != 0)\n return (frame_pointer_needed\n \t || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff);\n- total_size1 = MAX (PSEUDO_REGNO_BYTES (regno1),\n-\t\t regno_max_ref_width[regno1]);\n- total_size2 = MAX (PSEUDO_REGNO_BYTES (regno2),\n-\t\t regno_max_ref_width[regno2]);\n- if ((diff = total_size2 - total_size1) != 0)\n+ mode1 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno1),\n+\t\t\t regno_max_ref_mode[regno1]);\n+ mode2 = wider_subreg_mode (PSEUDO_REGNO_MODE (regno2),\n+\t\t\t regno_max_ref_mode[regno2]);\n+ if ((diff = GET_MODE_SIZE (mode2) - GET_MODE_SIZE (mode1)) != 0)\n return diff;\n return regno1 - regno2;\n }\n@@ -4144,7 +4144,7 @@ coalesce_spill_slots (ira_allocno_t *spi\n reload. */\n void\n ira_sort_regnos_for_alter_reg (int *pseudo_regnos, int n,\n-\t\t\t unsigned int *reg_max_ref_width)\n+\t\t\t machine_mode *reg_max_ref_mode)\n {\n int max_regno = max_reg_num ();\n int i, regno, num, slot_num;\n@@ -4225,10 +4225,14 @@ ira_sort_regnos_for_alter_reg (int *pseu\n \t ira_assert (ALLOCNO_HARD_REGNO (a) < 0);\n \t ALLOCNO_HARD_REGNO (a) = -slot_num;\n \t if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL)\n-\t fprintf (ira_dump_file, \" a%dr%d(%d,%d)\",\n-\t\t ALLOCNO_NUM (a), ALLOCNO_REGNO (a), ALLOCNO_FREQ (a),\n-\t\t MAX (PSEUDO_REGNO_BYTES (ALLOCNO_REGNO (a)),\n-\t\t\t reg_max_ref_width[ALLOCNO_REGNO (a)]));\n+\t {\n+\t machine_mode mode = wider_subreg_mode\n+\t\t(PSEUDO_REGNO_MODE (ALLOCNO_REGNO (a)),\n+\t\t reg_max_ref_mode[ALLOCNO_REGNO (a)]);\n+\t fprintf (ira_dump_file, \" a%dr%d(%d,%d)\",\n+\t\t ALLOCNO_NUM (a), ALLOCNO_REGNO (a), ALLOCNO_FREQ (a),\n+\t\t GET_MODE_SIZE (mode));\n+\t }\n \n \t if (a == allocno)\n \t break;\n@@ -4239,7 +4243,7 @@ ira_sort_regnos_for_alter_reg (int *pseu\n ira_spilled_reg_stack_slots_num = slot_num - 1;\n ira_free (spilled_coalesced_allocnos);\n /* Sort regnos according the slot numbers. */\n- regno_max_ref_width = reg_max_ref_width;\n+ regno_max_ref_mode = reg_max_ref_mode;\n qsort (pseudo_regnos, n, sizeof (int), coalesced_pseudo_reg_slot_compare);\n FOR_EACH_ALLOCNO (a, ai)\n ALLOCNO_ADD_DATA (a) = NULL;\nIndex: gcc/lra-constraints.c\n===================================================================\n--- gcc/lra-constraints.c\t2017-08-28 09:23:40.551863444 +0100\n+++ gcc/lra-constraints.c\t2017-08-28 09:23:56.227520860 +0100\n@@ -1772,10 +1772,9 @@ uses_hard_regs_p (rtx x, HARD_REG_SET se\n mode = GET_MODE (x);\n if (code == SUBREG)\n {\n+ mode = wider_subreg_mode (x);\n x = SUBREG_REG (x);\n code = GET_CODE (x);\n- if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode))\n-\tmode = GET_MODE (x);\n }\n \n if (REG_P (x))\n@@ -1953,10 +1952,8 @@ process_alt_operands (int only_alternati\n biggest_mode[nop] = GET_MODE (op);\n if (GET_CODE (op) == SUBREG)\n \t{\n+\t biggest_mode[nop] = wider_subreg_mode (op);\n \t operand_reg[nop] = reg = SUBREG_REG (op);\n-\t if (GET_MODE_SIZE (biggest_mode[nop])\n-\t < GET_MODE_SIZE (GET_MODE (reg)))\n-\t biggest_mode[nop] = GET_MODE (reg);\n \t}\n if (! REG_P (reg))\n \toperand_reg[nop] = NULL_RTX;\n@@ -5665,8 +5662,7 @@ invariant_p (const_rtx x)\n {\n x = SUBREG_REG (x);\n code = GET_CODE (x);\n- if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode))\n-\tmode = GET_MODE (x);\n+ mode = wider_subreg_mode (mode, GET_MODE (x));\n }\n \n if (MEM_P (x))\nIndex: gcc/lra-spills.c\n===================================================================\n--- gcc/lra-spills.c\t2017-08-28 09:23:42.709863597 +0100\n+++ gcc/lra-spills.c\t2017-08-28 09:23:56.227520860 +0100\n@@ -134,8 +134,7 @@ assign_mem_slot (int i)\n machine_mode mode = GET_MODE (regno_reg_rtx[i]);\n HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i);\n machine_mode wider_mode\n- = (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (lra_reg_info[i].biggest_mode)\n- ? mode : lra_reg_info[i].biggest_mode);\n+ = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode);\n HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode);\n HOST_WIDE_INT adjust = 0;\n \n@@ -311,10 +310,8 @@ add_pseudo_to_slot (int regno, int slot_\n and a total size which provides room for paradoxical subregs.\n We need to make sure the size and alignment of the slot are\n sufficient for both. */\n- machine_mode mode = (GET_MODE_SIZE (PSEUDO_REGNO_MODE (regno))\n-\t\t >= GET_MODE_SIZE (lra_reg_info[regno].biggest_mode)\n-\t\t ? PSEUDO_REGNO_MODE (regno)\n-\t\t : lra_reg_info[regno].biggest_mode);\n+ machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),\n+\t\t\t\t\t lra_reg_info[regno].biggest_mode);\n unsigned int align = spill_slot_alignment (mode);\n slots[slot_num].align = MAX (slots[slot_num].align, align);\n slots[slot_num].size = MAX (slots[slot_num].size, GET_MODE_SIZE (mode));\nIndex: gcc/lra.c\n===================================================================\n--- gcc/lra.c\t2017-08-28 09:23:38.966863332 +0100\n+++ gcc/lra.c\t2017-08-28 09:23:56.229320860 +0100\n@@ -831,12 +831,11 @@ collect_non_operand_hard_regs (rtx *x, l\n subreg_p = false;\n if (code == SUBREG)\n {\n+ mode = wider_subreg_mode (op);\n if (read_modify_subreg_p (op))\n \tsubreg_p = true;\n op = SUBREG_REG (op);\n code = GET_CODE (op);\n- if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op)))\n-\tmode = GET_MODE (op);\n }\n if (REG_P (op))\n {\n@@ -1426,12 +1425,11 @@ add_regs_to_insn_regno_info (lra_insn_re\n subreg_p = false;\n if (GET_CODE (x) == SUBREG)\n {\n+ mode = wider_subreg_mode (x);\n if (read_modify_subreg_p (x))\n \tsubreg_p = true;\n x = SUBREG_REG (x);\n code = GET_CODE (x);\n- if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)))\n-\tmode = GET_MODE (x);\n }\n if (REG_P (x))\n {\nIndex: gcc/reload1.c\n===================================================================\n--- gcc/reload1.c\t2017-08-28 09:23:42.710863597 +0100\n+++ gcc/reload1.c\t2017-08-28 09:23:56.229320860 +0100\n@@ -97,8 +97,8 @@ #define spill_indirect_levels\t\t\t\\\n in the current insn. */\n static HARD_REG_SET reg_is_output_reload;\n \n-/* Widest width in which each pseudo reg is referred to (via subreg). */\n-static unsigned int *reg_max_ref_width;\n+/* Widest mode in which each pseudo reg is referred to (via subreg). */\n+static machine_mode *reg_max_ref_mode;\n \n /* Vector to remember old contents of reg_renumber before spilling. */\n static short *reg_old_renumber;\n@@ -832,7 +832,7 @@ reload (rtx_insn *first, int global)\n if (ira_conflicts_p)\n /* Ask IRA to order pseudo-registers for better stack slot\n sharing. */\n- ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);\n+ ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);\n \n for (i = 0; i < n; i++)\n alter_reg (temp_pseudo_reg_arr[i], -1, false);\n@@ -1254,7 +1254,7 @@ reload (rtx_insn *first, int global)\n /* Indicate that we no longer have known memory locations or constants. */\n free_reg_equiv ();\n \n- free (reg_max_ref_width);\n+ free (reg_max_ref_mode);\n free (reg_old_renumber);\n free (pseudo_previous_regs);\n free (pseudo_forbidden_regs);\n@@ -2146,8 +2146,9 @@ alter_reg (int i, int from_reg, bool don\n machine_mode mode = GET_MODE (regno_reg_rtx[i]);\n unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);\n unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);\n- unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);\n- unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;\n+ machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);\n+ unsigned int total_size = GET_MODE_SIZE (wider_mode);\n+ unsigned int min_align = GET_MODE_BITSIZE (reg_max_ref_mode[i]);\n int adjust = 0;\n \n something_was_spilled = true;\n@@ -4085,9 +4086,9 @@ init_eliminable_invariants (rtx_insn *fi\n \n grow_reg_equivs ();\n if (do_subregs)\n- reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);\n+ reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);\n else\n- reg_max_ref_width = NULL;\n+ reg_max_ref_mode = NULL;\n \n num_eliminable_invariants = 0;\n \n@@ -4406,7 +4407,7 @@ finish_spills (int global)\n return something_changed;\n }\n \f\n-/* Find all paradoxical subregs within X and update reg_max_ref_width. */\n+/* Find all paradoxical subregs within X and update reg_max_ref_mode. */\n \n static void\n scan_paradoxical_subregs (rtx x)\n@@ -4429,13 +4430,14 @@ scan_paradoxical_subregs (rtx x)\n return;\n \n case SUBREG:\n- if (REG_P (SUBREG_REG (x))\n-\t && (GET_MODE_SIZE (GET_MODE (x))\n-\t > reg_max_ref_width[REGNO (SUBREG_REG (x))]))\n+ if (REG_P (SUBREG_REG (x)))\n \t{\n-\t reg_max_ref_width[REGNO (SUBREG_REG (x))]\n-\t = GET_MODE_SIZE (GET_MODE (x));\n-\t mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));\n+\t unsigned int regno = REGNO (SUBREG_REG (x));\n+\t if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))\n+\t {\n+\t reg_max_ref_mode[regno] = GET_MODE (x);\n+\t mark_home_live_1 (regno, GET_MODE (x));\n+\t }\n \t}\n return;\n \n", "prefixes": [] }