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GET /api/patches/806385/?format=api
{ "id": 806385, "url": "http://patchwork.ozlabs.org/api/patches/806385/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1503901744-21087-2-git-send-email-peng.fan@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503901744-21087-2-git-send-email-peng.fan@nxp.com>", "list_archive_url": null, "date": "2017-08-28T06:28:54", "name": "[U-Boot,V2,02/12] arm: dts: include dts for imx6sabresd", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "5e45a9ae2ff8026bcf353088e77ca4f297ecc5de", "submitter": { "id": 67896, "url": "http://patchwork.ozlabs.org/api/people/67896/?format=api", "name": "Peng Fan", "email": "peng.fan@nxp.com" }, "delegate": { "id": 1693, "url": "http://patchwork.ozlabs.org/api/users/1693/?format=api", "username": "sbabic", "first_name": "Stefano", "last_name": "Babic", "email": "sbabic@denx.de" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1503901744-21087-2-git-send-email-peng.fan@nxp.com/mbox/", "series": [ { "id": 83, "url": "http://patchwork.ozlabs.org/api/series/83/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=83", "date": "2017-08-28T06:28:53", "name": "[U-Boot,V2,01/12] scripts: spl: fix typo", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/83/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806385/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806385/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", 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s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=l/rHFszFMQJbM9aAwBlbcNev7gMo1DcGMyDZyPKNH7o=;\n\tb=V9UBixSycDrZFGb09op0k6pJmoPCvUaGDadP3kWAqqC/UG+idBkYoOoxuAJ3SVgese7slr3RSOyHMm/qgg2ASNZWdQNh2ZqxEVGwOYu7ej3F7KycLG+7NWyhXA1S0OWgNKN/AbsbK3VgJpIVXrGh/gNqjMsxV1aQ85z2l0NGSJ8=", "From": "Peng Fan <peng.fan@nxp.com>", "To": "sbabic@denx.de", "Date": "Mon, 28 Aug 2017 14:28:54 +0800", "Message-Id": "<1503901744-21087-2-git-send-email-peng.fan@nxp.com>", "X-Mailer": "git-send-email 2.6.2", "In-Reply-To": "<1503901744-21087-1-git-send-email-peng.fan@nxp.com>", "References": "<1503901744-21087-1-git-send-email-peng.fan@nxp.com>", "MIME-Version": "1.0", "X-Originating-IP": "[192.158.241.86]", "X-ClientProxiedBy": "HK2PR02CA0204.apcprd02.prod.outlook.com\n\t(2603:1096:201:20::16) To VI1PR04MB3229.eurprd04.prod.outlook.com\n\t(2603:10a6:802:6::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f2c4d57a-e78d-46ca-5912-08d4edde29e2", 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06:29:38.0429\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR04MB3229", "Cc": "u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH V2 02/12] arm: dts: include dts for imx6sabresd", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Import dts from commit aae4e7a8bc(\"Linux 4.13-rc4\") for imx6sabresd board.\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\nCc: Stefano Babic <sbabic@denx.de>\n---\n\nV2: none\n\n arch/arm/dts/Makefile | 3 +\n arch/arm/dts/imx6dl-sabresd.dts | 22 ++\n arch/arm/dts/imx6dl.dtsi | 242 +++++++++++++\n arch/arm/dts/imx6q-sabresd.dts | 30 ++\n arch/arm/dts/imx6q.dtsi | 164 ++++++++-\n arch/arm/dts/imx6qdl-sabresd.dtsi | 738 ++++++++++++++++++++++++++++++++++++++\n arch/arm/dts/imx6qdl.dtsi | 100 ++++--\n arch/arm/dts/imx6qp-sabresd.dts | 93 +++++\n arch/arm/dts/imx6qp.dtsi | 153 ++++++++\n arch/arm/dts/imx6sx-sdb-reva.dts | 143 ++++++++\n arch/arm/dts/imx6sx-sdb.dts | 147 ++++++++\n arch/arm/dts/imx6sx-sdb.dtsi | 612 +++++++++++++++++++++++++++++++\n 12 files changed, 2422 insertions(+), 25 deletions(-)\n create mode 100644 arch/arm/dts/imx6dl-sabresd.dts\n create mode 100644 arch/arm/dts/imx6q-sabresd.dts\n create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi\n create mode 100644 arch/arm/dts/imx6qp-sabresd.dts\n create mode 100644 arch/arm/dts/imx6qp.dtsi\n create mode 100644 arch/arm/dts/imx6sx-sdb-reva.dts\n create mode 100644 arch/arm/dts/imx6sx-sdb.dts\n create mode 100644 arch/arm/dts/imx6sx-sdb.dtsi", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 762429c..242e4f1 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -357,7 +357,10 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \\\n \timx6sll-evk.dtb \\\n \timx6dl-icore.dtb \\\n \timx6dl-icore-rqs.dtb \\\n+\timx6dl-sabresd.dtb \\\n \timx6q-cm-fx6.dtb \\\n+\timx6q-sabresd.dtb \\\n+\timx6qp-sabresd.dtb \\\n \timx6q-icore.dtb \\\n \timx6q-icore-rqs.dtb \\\n \timx6q-logicpd.dtb \\\ndiff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts\nnew file mode 100644\nindex 0000000..9607afe\n--- /dev/null\n+++ b/arch/arm/dts/imx6dl-sabresd.dts\n@@ -0,0 +1,22 @@\n+/*\n+ * Copyright (C) 2013 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"imx6dl.dtsi\"\n+#include \"imx6qdl-sabresd.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 DualLite SABRE Smart Device Board\";\n+\tcompatible = \"fsl,imx6dl-sabresd\", \"fsl,imx6dl\";\n+};\n+\n+&ipu1_csi1_from_ipu1_csi1_mux {\n+\tclock-lanes = <0>;\n+\tdata-lanes = <1 2>;\n+};\ndiff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi\nindex 9a4c22c..8475e6c 100644\n--- a/arch/arm/dts/imx6dl.dtsi\n+++ b/arch/arm/dts/imx6dl.dtsi\n@@ -100,6 +100,11 @@\n \t\t};\n \t};\n \n+\tcapture-subsystem {\n+\t\tcompatible = \"fsl,imx-capture-subsystem\";\n+\t\tports = <&ipu1_csi0>, <&ipu1_csi1>;\n+\t};\n+\n \tdisplay-subsystem {\n \t\tcompatible = \"fsl,imx-display-subsystem\";\n \t\tports = <&ipu1_di0>, <&ipu1_di1>;\n@@ -111,6 +116,169 @@\n \t};\n };\n \n+&gpio1 {\n+\tgpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,\n+\t\t <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,\n+\t\t <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,\n+\t\t <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,\n+\t\t <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,\n+\t\t <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,\n+\t\t <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;\n+};\n+\n+&gpio2 {\n+\tgpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,\n+\t\t <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,\n+\t\t <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,\n+\t\t <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,\n+\t\t <&iomuxc 28 113 4>;\n+};\n+\n+&gpio3 {\n+\tgpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,\n+\t\t <&iomuxc 16 81 16>;\n+};\n+\n+&gpio4 {\n+\tgpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,\n+\t\t <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,\n+\t\t <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,\n+\t\t <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,\n+\t\t <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;\n+};\n+\n+&gpio5 {\n+\tgpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,\n+\t\t <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,\n+\t\t <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,\n+\t\t <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;\n+};\n+\n+&gpio6 {\n+\tgpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,\n+\t\t <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,\n+\t\t <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,\n+\t\t <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,\n+\t\t <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,\n+\t\t <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;\n+};\n+\n+&gpio7 {\n+\tgpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,\n+\t\t <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,\n+\t\t <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;\n+};\n+\n+&gpr {\n+\tipu1_csi0_mux: ipu1_csi0_mux@34 {\n+\t\tcompatible = \"video-mux\";\n+\t\tmux-controls = <&mux 0>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tipu1_csi0_mux_from_mipi_vc0: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tipu1_csi0_mux_from_mipi_vc1: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tipu1_csi0_mux_from_mipi_vc2: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\n+\t\t\tipu1_csi0_mux_from_mipi_vc3: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\n+\t\t\tipu1_csi0_mux_from_parallel_sensor: endpoint {\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\n+\t\t\tipu1_csi0_mux_to_ipu1_csi0: endpoint {\n+\t\t\t\tremote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tipu1_csi1_mux: ipu1_csi1_mux@34 {\n+\t\tcompatible = \"video-mux\";\n+\t\tmux-controls = <&mux 1>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tipu1_csi1_mux_from_mipi_vc0: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tipu1_csi1_mux_from_mipi_vc1: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tipu1_csi1_mux_from_mipi_vc2: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\n+\t\t\tipu1_csi1_mux_from_mipi_vc3: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\n+\t\t\tipu1_csi1_mux_from_parallel_sensor: endpoint {\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\n+\t\t\tipu1_csi1_mux_to_ipu1_csi1: endpoint {\n+\t\t\t\tremote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &gpt {\n \tcompatible = \"fsl,imx6dl-gpt\";\n };\n@@ -119,6 +287,12 @@\n \tcompatible = \"fsl,imx6dl-hdmi\";\n };\n \n+&ipu1_csi1 {\n+\tipu1_csi1_from_ipu1_csi1_mux: endpoint {\n+\t\tremote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;\n+\t};\n+};\n+\n &ldb {\n \tclocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,\n \t\t <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,\n@@ -128,6 +302,74 @@\n \t\t \"di0\", \"di1\";\n };\n \n+&mipi_csi {\n+\tport@1 {\n+\t\treg = <1>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmipi_vc0_to_ipu1_csi0_mux: endpoint@0 {\n+\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;\n+\t\t};\n+\n+\t\tmipi_vc0_to_ipu1_csi1_mux: endpoint@1 {\n+\t\t\tremote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;\n+\t\t};\n+\t};\n+\n+\tport@2 {\n+\t\treg = <2>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmipi_vc1_to_ipu1_csi0_mux: endpoint@0 {\n+\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;\n+\t\t};\n+\n+\t\tmipi_vc1_to_ipu1_csi1_mux: endpoint@1 {\n+\t\t\tremote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;\n+\t\t};\n+\t};\n+\n+\tport@3 {\n+\t\treg = <3>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmipi_vc2_to_ipu1_csi0_mux: endpoint@0 {\n+\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;\n+\t\t};\n+\n+\t\tmipi_vc2_to_ipu1_csi1_mux: endpoint@1 {\n+\t\t\tremote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;\n+\t\t};\n+\t};\n+\n+\tport@4 {\n+\t\treg = <4>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmipi_vc3_to_ipu1_csi0_mux: endpoint@0 {\n+\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;\n+\t\t};\n+\n+\t\tmipi_vc3_to_ipu1_csi1_mux: endpoint@1 {\n+\t\t\tremote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;\n+\t\t};\n+\t};\n+};\n+\n+&mux {\n+\tmux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */\n+\t\t\t<0x34 0x00000038>, /* IPU_CSI1_MUX */\n+\t\t\t<0x0c 0x0000000c>, /* HDMI_MUX_CTL */\n+\t\t\t<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */\n+\t\t\t<0x0c 0x00000300>, /* LVDS1_MUX_CTL */\n+\t\t\t<0x28 0x00000003>, /* DCIC1_MUX_CTL */\n+\t\t\t<0x28 0x0000000c>; /* DCIC2_MUX_CTL */\n+};\n+\n &vpu {\n \tcompatible = \"fsl,imx6dl-vpu\", \"cnm,coda960\";\n };\ndiff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts\nnew file mode 100644\nindex 0000000..527772b\n--- /dev/null\n+++ b/arch/arm/dts/imx6q-sabresd.dts\n@@ -0,0 +1,30 @@\n+/*\n+ * Copyright 2012 Freescale Semiconductor, Inc.\n+ * Copyright 2011 Linaro Ltd.\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+/dts-v1/;\n+\n+#include \"imx6q.dtsi\"\n+#include \"imx6qdl-sabresd.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 Quad SABRE Smart Device Board\";\n+\tcompatible = \"fsl,imx6q-sabresd\", \"fsl,imx6q\";\n+};\n+\n+&sata {\n+\tstatus = \"okay\";\n+};\n+\n+&ipu1_csi1_from_mipi_vc1 {\n+\tclock-lanes = <0>;\n+\tdata-lanes = <1 2>;\n+};\ndiff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi\nindex c30c836..90a74173 100644\n--- a/arch/arm/dts/imx6q.dtsi\n+++ b/arch/arm/dts/imx6q.dtsi\n@@ -125,7 +125,7 @@\n \t\t\tclocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,\n \t\t\t\t <&clks IMX6QDL_CLK_GPU2D_CORE>;\n \t\t\tclock-names = \"bus\", \"core\";\n-\t\t\tpower-domains = <&gpc 1>;\n+\t\t\tpower-domains = <&pd_pu>;\n \t\t};\n \n \t\tipu2: ipu@02800000 {\n@@ -143,10 +143,18 @@\n \n \t\t\tipu2_csi0: port@0 {\n \t\t\t\treg = <0>;\n+\n+\t\t\t\tipu2_csi0_from_mipi_vc2: endpoint {\n+\t\t\t\t\tremote-endpoint = <&mipi_vc2_to_ipu2_csi0>;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tipu2_csi1: port@1 {\n \t\t\t\treg = <1>;\n+\n+\t\t\t\tipu2_csi1_from_ipu2_csi1_mux: endpoint {\n+\t\t\t\t\tremote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tipu2_di0: port@2 {\n@@ -198,6 +206,11 @@\n \t\t};\n \t};\n \n+\tcapture-subsystem {\n+\t\tcompatible = \"fsl,imx-capture-subsystem\";\n+\t\tports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;\n+\t};\n+\n \tdisplay-subsystem {\n \t\tcompatible = \"fsl,imx-display-subsystem\";\n \t\tports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;\n@@ -209,6 +222,105 @@\n \t};\n };\n \n+&gpio1 {\n+\tgpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,\n+\t\t <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,\n+\t\t <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,\n+\t\t <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,\n+\t\t <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,\n+\t\t <&iomuxc 22 116 10>;\n+};\n+\n+&gpio2 {\n+\tgpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,\n+\t\t <&iomuxc 31 44 1>;\n+};\n+\n+&gpio3 {\n+\tgpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;\n+};\n+\n+&gpio4 {\n+\tgpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;\n+};\n+\n+&gpio5 {\n+\tgpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,\n+\t\t <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;\n+};\n+\n+&gpio6 {\n+\tgpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,\n+\t\t <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,\n+\t\t <&iomuxc 31 86 1>;\n+};\n+\n+&gpio7 {\n+\tgpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;\n+};\n+\n+&gpr {\n+\tipu1_csi0_mux {\n+\t\tcompatible = \"video-mux\";\n+\t\tmux-controls = <&mux 0>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tipu1_csi0_mux_from_mipi_vc0: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tipu1_csi0_mux_from_parallel_sensor: endpoint {\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tipu1_csi0_mux_to_ipu1_csi0: endpoint {\n+\t\t\t\tremote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tipu2_csi1_mux {\n+\t\tcompatible = \"video-mux\";\n+\t\tmux-controls = <&mux 1>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tipu2_csi1_mux_from_mipi_vc3: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tipu2_csi1_mux_from_parallel_sensor: endpoint {\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tipu2_csi1_mux_to_ipu2_csi1: endpoint {\n+\t\t\t\tremote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &hdmi {\n \tcompatible = \"fsl,imx6q-hdmi\";\n \n@@ -229,6 +341,12 @@\n \t};\n };\n \n+&ipu1_csi1 {\n+\tipu1_csi1_from_mipi_vc1: endpoint {\n+\t\tremote-endpoint = <&mipi_vc1_to_ipu1_csi1>;\n+\t};\n+};\n+\n &ldb {\n \tclocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,\n \t\t <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,\n@@ -275,6 +393,40 @@\n \t};\n };\n \n+&mipi_csi {\n+\tport@1 {\n+\t\treg = <1>;\n+\n+\t\tmipi_vc0_to_ipu1_csi0_mux: endpoint {\n+\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;\n+\t\t};\n+\t};\n+\n+\tport@2 {\n+\t\treg = <2>;\n+\n+\t\tmipi_vc1_to_ipu1_csi1: endpoint {\n+\t\t\tremote-endpoint = <&ipu1_csi1_from_mipi_vc1>;\n+\t\t};\n+\t};\n+\n+\tport@3 {\n+\t\treg = <3>;\n+\n+\t\tmipi_vc2_to_ipu2_csi0: endpoint {\n+\t\t\tremote-endpoint = <&ipu2_csi0_from_mipi_vc2>;\n+\t\t};\n+\t};\n+\n+\tport@4 {\n+\t\treg = <4>;\n+\n+\t\tmipi_vc3_to_ipu2_csi1_mux: endpoint {\n+\t\t\tremote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;\n+\t\t};\n+\t};\n+};\n+\n &mipi_dsi {\n \tports {\n \t\tport@2 {\n@@ -295,6 +447,16 @@\n \t};\n };\n \n+&mux {\n+\tmux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */\n+\t\t\t<0x04 0x00100000>, /* MIPI_IPU2_MUX */\n+\t\t\t<0x0c 0x0000000c>, /* HDMI_MUX_CTL */\n+\t\t\t<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */\n+\t\t\t<0x0c 0x00000300>, /* LVDS1_MUX_CTL */\n+\t\t\t<0x28 0x00000003>, /* DCIC1_MUX_CTL */\n+\t\t\t<0x28 0x0000000c>; /* DCIC2_MUX_CTL */\n+};\n+\n &vpu {\n \tcompatible = \"fsl,imx6q-vpu\", \"cnm,coda960\";\n };\ndiff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi\nnew file mode 100644\nindex 0000000..b72b6fa\n--- /dev/null\n+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi\n@@ -0,0 +1,738 @@\n+/*\n+ * Copyright 2012 Freescale Semiconductor, Inc.\n+ * Copyright 2011 Linaro Ltd.\n+ *\n+ * The code contained herein is licensed under the GNU General Public\n+ * License. You may obtain a copy of the GNU General Public License\n+ * Version 2 or later at the following locations:\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+\n+#include <dt-bindings/clock/imx6qdl-clock.h>\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+\n+/ {\n+\tchosen {\n+\t\tstdout-path = &uart1;\n+\t};\n+\n+\tmemory {\n+\t\treg = <0x10000000 0x40000000>;\n+\t};\n+\n+\tregulators {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\treg_usb_otg_vbus: regulator@0 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <0>;\n+\t\t\tregulator-name = \"usb_otg_vbus\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t\tgpio = <&gpio3 22 0>;\n+\t\t\tenable-active-high;\n+\t\t\tvin-supply = <&swbst_reg>;\n+\t\t};\n+\n+\t\treg_usb_h1_vbus: regulator@1 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <1>;\n+\t\t\tregulator-name = \"usb_h1_vbus\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t\tgpio = <&gpio1 29 0>;\n+\t\t\tenable-active-high;\n+\t\t\tvin-supply = <&swbst_reg>;\n+\t\t};\n+\n+\t\treg_audio: regulator@2 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <2>;\n+\t\t\tregulator-name = \"wm8962-supply\";\n+\t\t\tgpio = <&gpio4 10 0>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\n+\t\treg_pcie: regulator@3 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <3>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_pcie_reg>;\n+\t\t\tregulator-name = \"MPCIE_3V3\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\tgpio = <&gpio3 19 0>;\n+\t\t\tregulator-always-on;\n+\t\t\tenable-active-high;\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_gpio_keys>;\n+\n+\t\tpower {\n+\t\t\tlabel = \"Power Button\";\n+\t\t\tgpios = <&gpio3 29 GPIO_ACTIVE_LOW>;\n+\t\t\twakeup-source;\n+\t\t\tlinux,code = <KEY_POWER>;\n+\t\t};\n+\n+\t\tvolume-up {\n+\t\t\tlabel = \"Volume Up\";\n+\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n+\t\t\twakeup-source;\n+\t\t\tlinux,code = <KEY_VOLUMEUP>;\n+\t\t};\n+\n+\t\tvolume-down {\n+\t\t\tlabel = \"Volume Down\";\n+\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n+\t\t\twakeup-source;\n+\t\t\tlinux,code = <KEY_VOLUMEDOWN>;\n+\t\t};\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"fsl,imx6q-sabresd-wm8962\",\n+\t\t\t \"fsl,imx-audio-wm8962\";\n+\t\tmodel = \"wm8962-audio\";\n+\t\tssi-controller = <&ssi2>;\n+\t\taudio-codec = <&codec>;\n+\t\taudio-routing =\n+\t\t\t\"Headphone Jack\", \"HPOUTL\",\n+\t\t\t\"Headphone Jack\", \"HPOUTR\",\n+\t\t\t\"Ext Spk\", \"SPKOUTL\",\n+\t\t\t\"Ext Spk\", \"SPKOUTR\",\n+\t\t\t\"AMIC\", \"MICBIAS\",\n+\t\t\t\"IN3R\", \"AMIC\";\n+\t\tmux-int-port = <2>;\n+\t\tmux-ext-port = <3>;\n+\t};\n+\n+\tbacklight_lvds: backlight-lvds {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&pwm1 0 5000000>;\n+\t\tbrightness-levels = <0 4 8 16 32 64 128 255>;\n+\t\tdefault-brightness-level = <7>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_gpio_leds>;\n+\n+\t\tred {\n+\t\t\tgpios = <&gpio1 2 0>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\t};\n+\n+\tpanel {\n+\t\tcompatible = \"hannstar,hsd100pxn1\";\n+\t\tbacklight = <&backlight_lvds>;\n+\n+\t\tport {\n+\t\t\tpanel_in: endpoint {\n+\t\t\t\tremote-endpoint = <&lvds0_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&ipu1_csi0_from_ipu1_csi0_mux {\n+\tbus-width = <8>;\n+\tdata-shift = <12>; /* Lines 19:12 used */\n+\thsync-active = <1>;\n+\tvsync-active = <1>;\n+};\n+\n+&ipu1_csi0_mux_from_parallel_sensor {\n+\tremote-endpoint = <&ov5642_to_ipu1_csi0_mux>;\n+};\n+\n+&ipu1_csi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_ipu1_csi0>;\n+};\n+\n+&mipi_csi {\n+\tstatus = \"okay\";\n+\n+\tport@0 {\n+\t\treg = <0>;\n+\n+\t\tmipi_csi2_in: endpoint {\n+\t\t\tremote-endpoint = <&ov5640_to_mipi_csi2>;\n+\t\t\tclock-lanes = <0>;\n+\t\t\tdata-lanes = <1 2>;\n+\t\t};\n+\t};\n+};\n+\n+&audmux {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_audmux>;\n+\tstatus = \"okay\";\n+};\n+\n+&clks {\n+\tassigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,\n+\t\t\t <&clks IMX6QDL_CLK_LDB_DI1_SEL>;\n+\tassigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,\n+\t\t\t\t <&clks IMX6QDL_CLK_PLL3_USB_OTG>;\n+};\n+\n+&ecspi1 {\n+\tcs-gpios = <&gpio4 9 0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_ecspi1>;\n+\tstatus = \"okay\";\n+\n+\tflash: m25p80@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"st,m25p32\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <20000000>;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&fec {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enet>;\n+\tphy-mode = \"rgmii\";\n+\tphy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;\n+\tstatus = \"okay\";\n+};\n+\n+&hdmi {\n+\tddc-i2c-bus = <&i2c2>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c1 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c1>;\n+\tstatus = \"okay\";\n+\n+\tcodec: wm8962@1a {\n+\t\tcompatible = \"wlf,wm8962\";\n+\t\treg = <0x1a>;\n+\t\tclocks = <&clks IMX6QDL_CLK_CKO>;\n+\t\tDCVDD-supply = <®_audio>;\n+\t\tDBVDD-supply = <®_audio>;\n+\t\tAVDD-supply = <®_audio>;\n+\t\tCPVDD-supply = <®_audio>;\n+\t\tMICVDD-supply = <®_audio>;\n+\t\tPLLVDD-supply = <®_audio>;\n+\t\tSPKVDD1-supply = <®_audio>;\n+\t\tSPKVDD2-supply = <®_audio>;\n+\t\tgpio-cfg = <\n+\t\t\t0x0000 /* 0:Default */\n+\t\t\t0x0000 /* 1:Default */\n+\t\t\t0x0013 /* 2:FN_DMICCLK */\n+\t\t\t0x0000 /* 3:Default */\n+\t\t\t0x8014 /* 4:FN_DMICCDAT */\n+\t\t\t0x0000 /* 5:Default */\n+\t\t>;\n+\t};\n+\n+\tov5642: camera@3c {\n+\t\tcompatible = \"ovti,ov5642\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_ov5642>;\n+\t\tclocks = <&clks IMX6QDL_CLK_CKO>;\n+\t\tclock-names = \"xclk\";\n+\t\treg = <0x3c>;\n+\t\tDOVDD-supply = <&vgen4_reg>; /* 1.8v */\n+\t\tAVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3\n+\t\t\t\t\t\trev B board is VGEN5 */\n+\t\tDVDD-supply = <&vgen2_reg>; /* 1.5v*/\n+\t\tpowerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n+\t\tstatus = \"disabled\";\n+\n+\t\tport {\n+\t\t\tov5642_to_ipu1_csi0_mux: endpoint {\n+\t\t\t\tremote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;\n+\t\t\t\tbus-width = <8>;\n+\t\t\t\thsync-active = <1>;\n+\t\t\t\tvsync-active = <1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c2>;\n+\tstatus = \"okay\";\n+\n+\tov5640: camera@3c {\n+\t\tcompatible = \"ovti,ov5640\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_ov5640>;\n+\t\treg = <0x3c>;\n+\t\tclocks = <&clks IMX6QDL_CLK_CKO>;\n+\t\tclock-names = \"xclk\";\n+\t\tDOVDD-supply = <&vgen4_reg>; /* 1.8v */\n+\t\tAVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3\n+\t\t\t\t\t\trev B board is VGEN5 */\n+\t\tDVDD-supply = <&vgen2_reg>; /* 1.5v*/\n+\t\tpowerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;\n+\n+\t\tport {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tov5640_to_mipi_csi2: endpoint {\n+\t\t\t\tremote-endpoint = <&mipi_csi2_in>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpmic: pfuze100@08 {\n+\t\tcompatible = \"fsl,pfuze100\";\n+\t\treg = <0x08>;\n+\n+\t\tregulators {\n+\t\t\tsw1a_reg: sw1ab {\n+\t\t\t\tregulator-min-microvolt = <300000>;\n+\t\t\t\tregulator-max-microvolt = <1875000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw1c_reg: sw1c {\n+\t\t\t\tregulator-min-microvolt = <300000>;\n+\t\t\t\tregulator-max-microvolt = <1875000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw2_reg: sw2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw3a_reg: sw3a {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw3b_reg: sw3b {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw4_reg: sw4 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t};\n+\n+\t\t\tswbst_reg: swbst {\n+\t\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\t\tregulator-max-microvolt = <5150000>;\n+\t\t\t};\n+\n+\t\t\tsnvs_reg: vsnvs {\n+\t\t\t\tregulator-min-microvolt = <1000000>;\n+\t\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvref_reg: vrefddr {\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen1_reg: vgen1 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t};\n+\n+\t\t\tvgen2_reg: vgen2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t};\n+\n+\t\t\tvgen3_reg: vgen3 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t};\n+\n+\t\t\tvgen4_reg: vgen4 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen5_reg: vgen5 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen6_reg: vgen6 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&i2c3 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c3>;\n+\tstatus = \"okay\";\n+\n+\tegalax_ts@04 {\n+\t\tcompatible = \"eeti,egalax_ts\";\n+\t\treg = <0x04>;\n+\t\tinterrupt-parent = <&gpio6>;\n+\t\tinterrupts = <7 2>;\n+\t\twakeup-gpios = <&gpio6 7 0>;\n+\t};\n+};\n+\n+&iomuxc {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_hog>;\n+\n+\timx6qdl-sabresd {\n+\t\tpinctrl_hog: hoggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0\n+\t\t\t\tMX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_audmux: audmuxgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT7__AUD3_RXD\t\t0x130b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT4__AUD3_TXC\t\t0x130b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT5__AUD3_TXD\t\t0x110b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT6__AUD3_TXFS\t\t0x130b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_ecspi1: ecspi1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_KEY_COL1__ECSPI1_MISO\t0x100b1\n+\t\t\t\tMX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI\t0x100b1\n+\t\t\t\tMX6QDL_PAD_KEY_COL0__ECSPI1_SCLK\t0x100b1\n+\t\t\t\tMX6QDL_PAD_KEY_ROW1__GPIO4_IO09\t\t0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_enet: enetgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_ENET_MDIO__ENET_MDIO\t\t0x1b0b0\n+\t\t\t\tMX6QDL_PAD_ENET_MDC__ENET_MDC\t\t0x1b0b0\n+\t\t\t\tMX6QDL_PAD_RGMII_TXC__RGMII_TXC\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_TD0__RGMII_TD0\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_TD1__RGMII_TD1\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_TD2__RGMII_TD2\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_TD3__RGMII_TD3\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL\t0x1b030\n+\t\t\t\tMX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK\t0x1b0b0\n+\t\t\t\tMX6QDL_PAD_RGMII_RXC__RGMII_RXC\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_RD0__RGMII_RD0\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_RD1__RGMII_RD1\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_RD2__RGMII_RD2\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_RD3__RGMII_RD3\t\t0x1b030\n+\t\t\t\tMX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL\t0x1b030\n+\t\t\t\tMX6QDL_PAD_GPIO_16__ENET_REF_CLK\t0x4001b0a8\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_gpio_keys: gpio_keysgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c1: i2c1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT8__I2C1_SDA\t\t0x4001b8b1\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT9__I2C1_SCL\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c2: i2c2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_KEY_COL3__I2C2_SCL\t\t0x4001b8b1\n+\t\t\t\tMX6QDL_PAD_KEY_ROW3__I2C2_SDA\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c3: i2c3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_GPIO_3__I2C3_SCL\t\t0x4001b8b1\n+\t\t\t\tMX6QDL_PAD_GPIO_6__I2C3_SDA\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_ipu1_csi0: ipu1csi0grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_ov5640: ov5640grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_ov5642: ov5642grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0\n+\t\t\t\tMX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_pcie: pciegrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_GPIO_17__GPIO7_IO12\t0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_pcie_reg: pciereggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_EIM_D19__GPIO3_IO19\t0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_pwm1: pwm1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD1_DAT3__PWM1_OUT\t\t0x1b0b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_uart1: uart1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA\t0x1b0b1\n+\t\t\t\tMX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA\t0x1b0b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usbotg: usbotggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_ENET_RX_ER__USB_OTG_ID\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc2: usdhc2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD2_CMD__SD2_CMD\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_CLK__SD2_CLK\t\t0x10059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT0__SD2_DATA0\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT1__SD2_DATA1\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT2__SD2_DATA2\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT3__SD2_DATA3\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D4__SD2_DATA4\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D5__SD2_DATA5\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D6__SD2_DATA6\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D7__SD2_DATA7\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc3: usdhc3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD3_CMD__SD3_CMD\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_CLK__SD3_CLK\t\t0x10059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT0__SD3_DATA0\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT1__SD3_DATA1\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT2__SD3_DATA2\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT3__SD3_DATA3\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT4__SD3_DATA4\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT5__SD3_DATA5\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT6__SD3_DATA6\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT7__SD3_DATA7\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc4: usdhc4grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD4_CMD__SD4_CMD\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_CLK__SD4_CLK\t\t0x10059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT0__SD4_DATA0\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT1__SD4_DATA1\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT2__SD4_DATA2\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT3__SD4_DATA3\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT4__SD4_DATA4\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT5__SD4_DATA5\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT6__SD4_DATA6\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD4_DAT7__SD4_DATA7\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_wdog: wdoggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_GPIO_1__WDOG2_B\t\t0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\t};\n+\n+\tgpio_leds {\n+\t\tpinctrl_gpio_leds: gpioledsgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0\n+\t\t\t>;\n+\t\t};\n+\t};\n+};\n+\n+&ldb {\n+\tstatus = \"okay\";\n+\n+\tlvds-channel@1 {\n+\t\tfsl,data-mapping = \"spwg\";\n+\t\tfsl,data-width = <18>;\n+\t\tstatus = \"okay\";\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\n+\t\t\tlvds0_out: endpoint {\n+\t\t\t\tremote-endpoint = <&panel_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&pcie {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pcie>;\n+\treset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;\n+\tstatus = \"okay\";\n+};\n+\n+&pwm1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm1>;\n+\tstatus = \"okay\";\n+};\n+\n+®_arm {\n+ vin-supply = <&sw1a_reg>;\n+};\n+\n+®_pu {\n+ vin-supply = <&sw1c_reg>;\n+};\n+\n+®_soc {\n+ vin-supply = <&sw1c_reg>;\n+};\n+\n+&snvs_poweroff {\n+\tstatus = \"okay\";\n+};\n+\n+&ssi2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart1>;\n+\tstatus = \"okay\";\n+};\n+\n+&usbh1 {\n+\tvbus-supply = <®_usb_h1_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&usbotg {\n+\tvbus-supply = <®_usb_otg_vbus>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usbotg>;\n+\tdisable-over-current;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc2>;\n+\tbus-width = <8>;\n+\tcd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc3>;\n+\tbus-width = <8>;\n+\tcd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc4>;\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tno-1-8-v;\n+\tstatus = \"okay\";\n+};\n+\n+&wdog1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&wdog2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_wdog>;\n+\tfsl,ext-reset-output;\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi\nindex b13b0b2..a9723b9 100644\n--- a/arch/arm/dts/imx6qdl.dtsi\n+++ b/arch/arm/dts/imx6qdl.dtsi\n@@ -13,9 +13,18 @@\n #include <dt-bindings/clock/imx6qdl-clock.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n \n-#include \"skeleton.dtsi\"\n-\n / {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\t/*\n+\t * The decompressor and also some bootloaders rely on a\n+\t * pre-existing /chosen node to be available to insert the\n+\t * command line and merge other ATAGS info.\n+\t * Also for U-Boot there must be a pre-existing /memory node.\n+\t */\n+\tchosen {};\n+\tmemory { device_type = \"memory\"; reg = <0 0>; };\n+\n \taliases {\n \t\tethernet0 = &fec;\n \t\tcan0 = &can1;\n@@ -147,7 +156,7 @@\n \t\t\t\t <&clks IMX6QDL_CLK_GPU3D_CORE>,\n \t\t\t\t <&clks IMX6QDL_CLK_GPU3D_SHADER>;\n \t\t\tclock-names = \"bus\", \"core\", \"shader\";\n-\t\t\tpower-domains = <&gpc 1>;\n+\t\t\tpower-domains = <&pd_pu>;\n \t\t};\n \n \t\tgpu_2d: gpu@00134000 {\n@@ -157,7 +166,7 @@\n \t\t\tclocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,\n \t\t\t\t <&clks IMX6QDL_CLK_GPU2D_CORE>;\n \t\t\tclock-names = \"bus\", \"core\";\n-\t\t\tpower-domains = <&gpc 1>;\n+\t\t\tpower-domains = <&pd_pu>;\n \t\t};\n \n \t\ttimer@00a00600 {\n@@ -188,7 +197,7 @@\n \t\t\tarm,shared-override;\n \t\t};\n \n-\t\tpcie: pcie@0x01000000 {\n+\t\tpcie: pcie@1ffc000 {\n \t\t\tcompatible = \"fsl,imx6q-pcie\", \"snps,dw-pcie\";\n \t\t\treg = <0x01ffc000 0x04000>,\n \t\t\t <0x01f00000 0x80000>;\n@@ -196,6 +205,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \t\t\tdevice_type = \"pci\";\n+\t\t\tbus-range = <0x00 0xff>;\n \t\t\tranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */\n \t\t\t\t 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */\n \t\t\tnum-lanes = <1>;\n@@ -204,9 +214,9 @@\n \t\t\t#interrupt-cells = <1>;\n \t\t\tinterrupt-map-mask = <0 0 0 0x7>;\n \t\t\tinterrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\t\t<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&clks IMX6QDL_CLK_PCIE_AXI>,\n \t\t\t\t <&clks IMX6QDL_CLK_LVDS1_GATE>,\n \t\t\t\t <&clks IMX6QDL_CLK_PCIE_REF_125M>;\n@@ -424,7 +434,7 @@\n \t\t\t\tclocks = <&clks IMX6QDL_CLK_VPU_AXI>,\n \t\t\t\t\t <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;\n \t\t\t\tclock-names = \"per\", \"ahb\";\n-\t\t\t\tpower-domains = <&gpc 1>;\n+\t\t\t\tpower-domains = <&pd_pu>;\n \t\t\t\tresets = <&src 1>;\n \t\t\t\tiram = <&ocram>;\n \t\t\t};\n@@ -625,8 +635,8 @@\n \t\t\t\tregulator-1p1 {\n \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n \t\t\t\t\tregulator-name = \"vdd1p1\";\n-\t\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\t\tregulator-max-microvolt = <1375000>;\n+\t\t\t\t\tregulator-min-microvolt = <1000000>;\n+\t\t\t\t\tregulator-max-microvolt = <1200000>;\n \t\t\t\t\tregulator-always-on;\n \t\t\t\t\tanatop-reg-offset = <0x110>;\n \t\t\t\t\tanatop-vol-bit-shift = <8>;\n@@ -634,6 +644,7 @@\n \t\t\t\t\tanatop-min-bit-val = <4>;\n \t\t\t\t\tanatop-min-voltage = <800000>;\n \t\t\t\t\tanatop-max-voltage = <1375000>;\n+\t\t\t\t\tanatop-enable-bit = <0>;\n \t\t\t\t};\n \n \t\t\t\tregulator-3p0 {\n@@ -648,20 +659,22 @@\n \t\t\t\t\tanatop-min-bit-val = <0>;\n \t\t\t\t\tanatop-min-voltage = <2625000>;\n \t\t\t\t\tanatop-max-voltage = <3400000>;\n+\t\t\t\t\tanatop-enable-bit = <0>;\n \t\t\t\t};\n \n \t\t\t\tregulator-2p5 {\n \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n \t\t\t\t\tregulator-name = \"vdd2p5\";\n-\t\t\t\t\tregulator-min-microvolt = <2000000>;\n+\t\t\t\t\tregulator-min-microvolt = <2250000>;\n \t\t\t\t\tregulator-max-microvolt = <2750000>;\n \t\t\t\t\tregulator-always-on;\n \t\t\t\t\tanatop-reg-offset = <0x130>;\n \t\t\t\t\tanatop-vol-bit-shift = <8>;\n \t\t\t\t\tanatop-vol-bit-width = <5>;\n \t\t\t\t\tanatop-min-bit-val = <0>;\n-\t\t\t\t\tanatop-min-voltage = <2000000>;\n-\t\t\t\t\tanatop-max-voltage = <2750000>;\n+\t\t\t\t\tanatop-min-voltage = <2100000>;\n+\t\t\t\t\tanatop-max-voltage = <2875000>;\n+\t\t\t\t\tanatop-enable-bit = <0>;\n \t\t\t\t};\n \n \t\t\t\treg_arm: regulator-vddcore {\n@@ -787,19 +800,39 @@\n \t\t\t\tinterrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t\t\t <0 90 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\t\tinterrupt-parent = <&intc>;\n-\t\t\t\tpu-supply = <®_pu>;\n-\t\t\t\tclocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,\n-\t\t\t\t\t <&clks IMX6QDL_CLK_GPU3D_SHADER>,\n-\t\t\t\t\t <&clks IMX6QDL_CLK_GPU2D_CORE>,\n-\t\t\t\t\t <&clks IMX6QDL_CLK_GPU2D_AXI>,\n-\t\t\t\t\t <&clks IMX6QDL_CLK_OPENVG_AXI>,\n-\t\t\t\t\t <&clks IMX6QDL_CLK_VPU_AXI>;\n-\t\t\t\t#power-domain-cells = <1>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_IPG>;\n+\t\t\t\tclock-names = \"ipg\";\n+\n+\t\t\t\tpgc {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tpower-domain@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t\tpd_pu: power-domain@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\tpower-supply = <®_pu>;\n+\t\t\t\t\t\tclocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,\n+\t\t\t\t\t\t <&clks IMX6QDL_CLK_GPU3D_SHADER>,\n+\t\t\t\t\t\t <&clks IMX6QDL_CLK_GPU2D_CORE>,\n+\t\t\t\t\t\t <&clks IMX6QDL_CLK_GPU2D_AXI>,\n+\t\t\t\t\t\t <&clks IMX6QDL_CLK_OPENVG_AXI>,\n+\t\t\t\t\t\t <&clks IMX6QDL_CLK_VPU_AXI>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tgpr: iomuxc-gpr@020e0000 {\n-\t\t\t\tcompatible = \"fsl,imx6q-iomuxc-gpr\", \"syscon\";\n+\t\t\t\tcompatible = \"fsl,imx6q-iomuxc-gpr\", \"syscon\", \"simple-mfd\";\n \t\t\t\treg = <0x020e0000 0x38>;\n+\n+\t\t\t\tmux: mux-controller {\n+\t\t\t\t\tcompatible = \"mmio-mux\";\n+\t\t\t\t\t#mux-control-cells = <1>;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tiomuxc: iomuxc@020e0000 {\n@@ -807,7 +840,7 @@\n \t\t\t\treg = <0x020e0000 0x4000>;\n \t\t\t};\n \n-\t\t\tldb: ldb@020e0008 {\n+\t\t\tldb: ldb {\n \t\t\t\t#address-cells = <1>;\n \t\t\t\t#size-cells = <0>;\n \t\t\t\tcompatible = \"fsl,imx6q-ldb\", \"fsl,imx53-ldb\";\n@@ -1092,10 +1125,14 @@\n \t\t\t};\n \n \t\t\tweim: weim@021b8000 {\n+\t\t\t\t#address-cells = <2>;\n+\t\t\t\t#size-cells = <1>;\n \t\t\t\tcompatible = \"fsl,imx6q-weim\";\n \t\t\t\treg = <0x021b8000 0x4000>;\n \t\t\t\tinterrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\t\tclocks = <&clks IMX6QDL_CLK_EIM_SLOW>;\n+\t\t\t\tfsl,weim-cs-gpr = <&gpr>;\n+\t\t\t\tstatus = \"disabled\";\n \t\t\t};\n \n \t\t\tocotp: ocotp@021bc000 {\n@@ -1121,7 +1158,16 @@\n \t\t\t};\n \n \t\t\tmipi_csi: mipi@021dc000 {\n+\t\t\t\tcompatible = \"fsl,imx6-mipi-csi2\";\n \t\t\t\treg = <0x021dc000 0x4000>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tinterrupts = <0 100 0x04>, <0 101 0x04>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_HSI_TX>,\n+\t\t\t\t\t <&clks IMX6QDL_CLK_VIDEO_27M>,\n+\t\t\t\t\t <&clks IMX6QDL_CLK_EIM_PODF>;\n+\t\t\t\tclock-names = \"dphy\", \"ref\", \"pix\";\n+\t\t\t\tstatus = \"disabled\";\n \t\t\t};\n \n \t\t\tmipi_dsi: mipi@021e0000 {\n@@ -1153,8 +1199,10 @@\n \t\t\t};\n \n \t\t\tvdoa@021e4000 {\n+\t\t\t\tcompatible = \"fsl,imx6q-vdoa\";\n \t\t\t\treg = <0x021e4000 0x4000>;\n \t\t\t\tinterrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_VDOA>;\n \t\t\t};\n \n \t\t\tuart2: serial@021e8000 {\n@@ -1221,6 +1269,10 @@\n \n \t\t\tipu1_csi0: port@0 {\n \t\t\t\treg = <0>;\n+\n+\t\t\t\tipu1_csi0_from_ipu1_csi0_mux: endpoint {\n+\t\t\t\t\tremote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tipu1_csi1: port@1 {\ndiff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts\nnew file mode 100644\nindex 0000000..a8a5004\n--- /dev/null\n+++ b/arch/arm/dts/imx6qp-sabresd.dts\n@@ -0,0 +1,93 @@\n+/*\n+ * Copyright 2016 Freescale Semiconductor, Inc.\n+ *\n+ * This file is dual-licensed: you can use it either under the terms\n+ * of the GPL or the X11 license, at your option. Note that this dual\n+ * licensing only applies to this file, and not this project as a\n+ * whole.\n+ *\n+ * a) This file is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This file is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * Or, alternatively,\n+ *\n+ * b) Permission is hereby granted, free of charge, to any person\n+ * obtaining a copy of this software and associated documentation\n+ * files (the \"Software\"), to deal in the Software without\n+ * restriction, including without limitation the rights to use,\n+ * copy, modify, merge, publish, distribute, sublicense, and/or\n+ * sell copies of the Software, and to permit persons to whom the\n+ * Software is furnished to do so, subject to the following\n+ * conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be\n+ * included in all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ * OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"imx6qp.dtsi\"\n+#include \"imx6qdl-sabresd.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 Quad Plus SABRE Smart Device Board\";\n+\tcompatible = \"fsl,imx6qp-sabresd\", \"fsl,imx6qp\";\n+};\n+\n+®_arm {\n+\tvin-supply = <&sw2_reg>;\n+};\n+\n+&iomuxc {\n+\timx6qdl-sabresd {\n+\t\tpinctrl_usdhc2: usdhc2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD2_CMD__SD2_CMD\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_CLK__SD2_CLK\t\t0x10071\n+\t\t\t\tMX6QDL_PAD_SD2_DAT0__SD2_DATA0\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT1__SD2_DATA1\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT2__SD2_DATA2\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD2_DAT3__SD2_DATA3\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D4__SD2_DATA4\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D5__SD2_DATA5\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D6__SD2_DATA6\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_NANDF_D7__SD2_DATA7\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc3: usdhc3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6QDL_PAD_SD3_CMD__SD3_CMD\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_CLK__SD3_CLK\t\t0x10071\n+\t\t\t\tMX6QDL_PAD_SD3_DAT0__SD3_DATA0\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT1__SD3_DATA1\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT2__SD3_DATA2\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT3__SD3_DATA3\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT4__SD3_DATA4\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT5__SD3_DATA5\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT6__SD3_DATA6\t\t0x17059\n+\t\t\t\tMX6QDL_PAD_SD3_DAT7__SD3_DATA7\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\t};\n+};\n+\n+&pcie {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi\nnew file mode 100644\nindex 0000000..299d863\n--- /dev/null\n+++ b/arch/arm/dts/imx6qp.dtsi\n@@ -0,0 +1,153 @@\n+/*\n+ * Copyright 2016 Freescale Semiconductor, Inc.\n+ *\n+ * This file is dual-licensed: you can use it either under the terms\n+ * of the GPL or the X11 license, at your option. Note that this dual\n+ * licensing only applies to this file, and not this project as a\n+ * whole.\n+ *\n+ * a) This file is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version.\n+ *\n+ * This file is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * Or, alternatively,\n+ *\n+ * b) Permission is hereby granted, free of charge, to any person\n+ * obtaining a copy of this software and associated documentation\n+ * files (the \"Software\"), to deal in the Software without\n+ * restriction, including without limitation the rights to use,\n+ * copy, modify, merge, publish, distribute, sublicense, and/or\n+ * sell copies of the Software, and to permit persons to whom the\n+ * Software is furnished to do so, subject to the following\n+ * conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be\n+ * included in all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ * OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+#include \"imx6q.dtsi\"\n+\n+/ {\n+\tsoc {\n+\t\tocram2: sram@00940000 {\n+\t\t\tcompatible = \"mmio-sram\";\n+\t\t\treg = <0x00940000 0x20000>;\n+\t\t\tclocks = <&clks IMX6QDL_CLK_OCRAM>;\n+\t\t};\n+\n+\t\tocram3: sram@00960000 {\n+\t\t\tcompatible = \"mmio-sram\";\n+\t\t\treg = <0x00960000 0x20000>;\n+\t\t\tclocks = <&clks IMX6QDL_CLK_OCRAM>;\n+\t\t};\n+\n+\t\taips-bus@02100000 {\n+\t\t\tpre1: pre@21c8000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-pre\";\n+\t\t\t\treg = <0x021c8000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRE0>;\n+\t\t\t\tclock-names = \"axi\";\n+\t\t\t\tfsl,iram = <&ocram2>;\n+\t\t\t};\n+\n+\t\t\tpre2: pre@21c9000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-pre\";\n+\t\t\t\treg = <0x021c9000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRE1>;\n+\t\t\t\tclock-names = \"axi\";\n+\t\t\t\tfsl,iram = <&ocram2>;\n+\t\t\t};\n+\n+\t\t\tpre3: pre@21ca000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-pre\";\n+\t\t\t\treg = <0x021ca000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRE2>;\n+\t\t\t\tclock-names = \"axi\";\n+\t\t\t\tfsl,iram = <&ocram3>;\n+\t\t\t};\n+\n+\t\t\tpre4: pre@21cb000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-pre\";\n+\t\t\t\treg = <0x021cb000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRE3>;\n+\t\t\t\tclock-names = \"axi\";\n+\t\t\t\tfsl,iram = <&ocram3>;\n+\t\t\t};\n+\n+\t\t\tprg1: prg@21cc000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-prg\";\n+\t\t\t\treg = <0x021cc000 0x1000>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRG0_APB>,\n+\t\t\t\t\t <&clks IMX6QDL_CLK_PRG0_AXI>;\n+\t\t\t\tclock-names = \"ipg\", \"axi\";\n+\t\t\t\tfsl,pres = <&pre1>, <&pre2>, <&pre3>;\n+\t\t\t};\n+\n+\t\t\tprg2: prg@21cd000 {\n+\t\t\t\tcompatible = \"fsl,imx6qp-prg\";\n+\t\t\t\treg = <0x021cd000 0x1000>;\n+\t\t\t\tclocks = <&clks IMX6QDL_CLK_PRG1_APB>,\n+\t\t\t\t\t <&clks IMX6QDL_CLK_PRG1_AXI>;\n+\t\t\t\tclock-names = \"ipg\", \"axi\";\n+\t\t\t\tfsl,pres = <&pre4>, <&pre2>, <&pre3>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&fec {\n+\t/delete-property/interrupts-extended;\n+\tinterrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t <0 119 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&gpc {\n+\tcompatible = \"fsl,imx6qp-gpc\", \"fsl,imx6q-gpc\";\n+};\n+\n+&ipu1 {\n+\tcompatible = \"fsl,imx6qp-ipu\", \"fsl,imx6q-ipu\";\n+\tfsl,prg = <&prg1>;\n+};\n+\n+&ipu2 {\n+\tcompatible = \"fsl,imx6qp-ipu\", \"fsl,imx6q-ipu\";\n+\tfsl,prg = <&prg2>;\n+};\n+\n+&ldb {\n+\tclocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,\n+\t\t <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,\n+\t\t <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,\n+\t\t <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;\n+\tclock-names = \"di0_pll\", \"di1_pll\",\n+\t\t \"di0_sel\", \"di1_sel\", \"di2_sel\", \"di3_sel\",\n+\t\t \"di0\", \"di1\";\n+};\n+\n+&mmdc0 {\n+\tcompatible = \"fsl,imx6qp-mmdc\", \"fsl,imx6q-mmdc\";\n+};\n+\n+&pcie {\n+\tcompatible = \"fsl,imx6qp-pcie\", \"snps,dw-pcie\";\n+};\ndiff --git a/arch/arm/dts/imx6sx-sdb-reva.dts b/arch/arm/dts/imx6sx-sdb-reva.dts\nnew file mode 100644\nindex 0000000..7100547\n--- /dev/null\n+++ b/arch/arm/dts/imx6sx-sdb-reva.dts\n@@ -0,0 +1,143 @@\n+/*\n+ * Copyright (C) 2015 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include \"imx6sx-sdb.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 SoloX SDB RevA Board\";\n+};\n+\n+&i2c1 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c1>;\n+\tstatus = \"okay\";\n+\n+\tpmic: pfuze100@08 {\n+\t\tcompatible = \"fsl,pfuze100\";\n+\t\treg = <0x08>;\n+\n+\t\tregulators {\n+\t\t\tsw1a_reg: sw1ab {\n+\t\t\t\tregulator-min-microvolt = <300000>;\n+\t\t\t\tregulator-max-microvolt = <1875000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw1c_reg: sw1c {\n+\t\t\t\tregulator-min-microvolt = <300000>;\n+\t\t\t\tregulator-max-microvolt = <1875000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw2_reg: sw2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw3a_reg: sw3a {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw3b_reg: sw3b {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw4_reg: sw4 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t};\n+\n+\t\t\tswbst_reg: swbst {\n+\t\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\t\tregulator-max-microvolt = <5150000>;\n+\t\t\t};\n+\n+\t\t\tsnvs_reg: vsnvs {\n+\t\t\t\tregulator-min-microvolt = <1000000>;\n+\t\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvref_reg: vrefddr {\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen1_reg: vgen1 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen2_reg: vgen2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t};\n+\n+\t\t\tvgen3_reg: vgen3 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen4_reg: vgen4 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen5_reg: vgen5 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen6_reg: vgen6 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&qspi2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_qspi2>;\n+\tstatus = \"okay\";\n+\n+\tflash0: s25fl128s@0 {\n+\t\treg = <0>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spansion,s25fl128s\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <66000000>;\n+\t};\n+\n+\tflash1: s25fl128s@1 {\n+\t\treg = <1>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spansion,s25fl128s\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <66000000>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts\nnew file mode 100644\nindex 0000000..5bb8fd5\n--- /dev/null\n+++ b/arch/arm/dts/imx6sx-sdb.dts\n@@ -0,0 +1,147 @@\n+/*\n+ * Copyright (C) 2015 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include \"imx6sx-sdb.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 SoloX SDB RevB Board\";\n+};\n+\n+&cpu0 {\n+\toperating-points = <\n+\t\t/* kHz uV */\n+\t\t996000 1250000\n+\t\t792000 1175000\n+\t\t396000 1175000\n+\t\t198000 1175000\n+\t\t>;\n+\tfsl,soc-operating-points = <\n+\t\t/* ARM kHz SOC uV */\n+\t\t996000\t1250000\n+\t\t792000\t1175000\n+\t\t396000\t1175000\n+\t\t198000 1175000\n+\t>;\n+};\n+\n+&i2c1 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c1>;\n+\tstatus = \"okay\";\n+\n+\tpmic: pfuze100@08 {\n+\t\tcompatible = \"fsl,pfuze200\";\n+\t\treg = <0x08>;\n+\n+\t\tregulators {\n+\t\t\tsw1a_reg: sw1ab {\n+\t\t\t\tregulator-min-microvolt = <300000>;\n+\t\t\t\tregulator-max-microvolt = <1875000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-ramp-delay = <6250>;\n+\t\t\t};\n+\n+\t\t\tsw2_reg: sw2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw3a_reg: sw3a {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tsw3b_reg: sw3b {\n+\t\t\t\tregulator-min-microvolt = <400000>;\n+\t\t\t\tregulator-max-microvolt = <1975000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tswbst_reg: swbst {\n+\t\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\t\tregulator-max-microvolt = <5150000>;\n+\t\t\t};\n+\n+\t\t\tsnvs_reg: vsnvs {\n+\t\t\t\tregulator-min-microvolt = <1000000>;\n+\t\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvref_reg: vrefddr {\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen1_reg: vgen1 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen2_reg: vgen2 {\n+\t\t\t\tregulator-min-microvolt = <800000>;\n+\t\t\t\tregulator-max-microvolt = <1550000>;\n+\t\t\t};\n+\n+\t\t\tvgen3_reg: vgen3 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen4_reg: vgen4 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen5_reg: vgen5 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\tvgen6_reg: vgen6 {\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&qspi2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_qspi2>;\n+\tstatus = \"okay\";\n+\n+\tflash0: n25q256a@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"micron,n25q256a\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <29000000>;\n+\t\treg = <0>;\n+\t};\n+\n+\tflash1: n25q256a@1 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"micron,n25q256a\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <29000000>;\n+\t\treg = <1>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/imx6sx-sdb.dtsi b/arch/arm/dts/imx6sx-sdb.dtsi\nnew file mode 100644\nindex 0000000..da81552\n--- /dev/null\n+++ b/arch/arm/dts/imx6sx-sdb.dtsi\n@@ -0,0 +1,612 @@\n+/*\n+ * Copyright (C) 2014 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include \"imx6sx.dtsi\"\n+\n+/ {\n+\tmodel = \"Freescale i.MX6 SoloX SDB Board\";\n+\tcompatible = \"fsl,imx6sx-sdb\", \"fsl,imx6sx\";\n+\n+\tchosen {\n+\t\tstdout-path = &uart1;\n+\t};\n+\n+\tmemory {\n+\t\treg = <0x80000000 0x40000000>;\n+\t};\n+\n+\tbacklight {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&pwm3 0 5000000>;\n+\t\tbrightness-levels = <0 4 8 16 32 64 128 255>;\n+\t\tdefault-brightness-level = <6>;\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_gpio_keys>;\n+\n+\t\tvolume-up {\n+\t\t\tlabel = \"Volume Up\";\n+\t\t\tgpios = <&gpio1 18 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_VOLUMEUP>;\n+\t\t};\n+\n+\t\tvolume-down {\n+\t\t\tlabel = \"Volume Down\";\n+\t\t\tgpios = <&gpio1 19 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_VOLUMEDOWN>;\n+\t\t};\n+\t};\n+\n+\tregulators {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tvcc_sd3: regulator@0 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_vcc_sd3>;\n+\t\t\tregulator-name = \"VCC_SD3\";\n+\t\t\tregulator-min-microvolt = <3000000>;\n+\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\tgpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\n+\t\treg_usb_otg1_vbus: regulator@1 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <1>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_usb_otg1>;\n+\t\t\tregulator-name = \"usb_otg1_vbus\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t\tgpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\n+\t\treg_usb_otg2_vbus: regulator@2 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <2>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_usb_otg2>;\n+\t\t\tregulator-name = \"usb_otg2_vbus\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t\tgpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\n+\t\treg_psu_5v: regulator@3 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <3>;\n+\t\t\tregulator-name = \"PSU-5V0\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t};\n+\n+\t\treg_lcd_3v3: regulator@4 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <4>;\n+\t\t\tregulator-name = \"lcd-3v3\";\n+\t\t\tgpio = <&gpio3 27 0>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\n+\t\treg_peri_3v3: regulator@5 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <5>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_peri_3v3>;\n+\t\t\tregulator-name = \"peri_3v3\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\tgpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;\n+\t\t\tenable-active-high;\n+\t\t\tregulator-always-on;\n+\t\t};\n+\n+\t\treg_enet_3v3: regulator@6 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <6>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_enet_3v3>;\n+\t\t\tregulator-name = \"enet_3v3\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\tgpios = <&gpio2 6 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"fsl,imx6sx-sdb-wm8962\", \"fsl,imx-audio-wm8962\";\n+\t\tmodel = \"wm8962-audio\";\n+\t\tssi-controller = <&ssi2>;\n+\t\taudio-codec = <&codec>;\n+\t\taudio-routing =\n+\t\t\t\"Headphone Jack\", \"HPOUTL\",\n+\t\t\t\"Headphone Jack\", \"HPOUTR\",\n+\t\t\t\"Ext Spk\", \"SPKOUTL\",\n+\t\t\t\"Ext Spk\", \"SPKOUTR\",\n+\t\t\t\"AMIC\", \"MICBIAS\",\n+\t\t\t\"IN3R\", \"AMIC\";\n+\t\tmux-int-port = <2>;\n+\t\tmux-ext-port = <6>;\n+\t};\n+};\n+\n+&audmux {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_audmux>;\n+\tstatus = \"okay\";\n+};\n+\n+&fec1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enet1>;\n+\tphy-supply = <®_enet_3v3>;\n+\tphy-mode = \"rgmii\";\n+\tphy-handle = <ðphy1>;\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tethphy1: ethernet-phy@1 {\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\tethphy2: ethernet-phy@2 {\n+\t\t\treg = <2>;\n+\t\t};\n+\t};\n+};\n+\n+&fec2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enet2>;\n+\tphy-mode = \"rgmii\";\n+\tphy-handle = <ðphy2>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c3 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c3>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c4 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c4>;\n+\tstatus = \"okay\";\n+\n+\tcodec: wm8962@1a {\n+\t\tcompatible = \"wlf,wm8962\";\n+\t\treg = <0x1a>;\n+\t\tclocks = <&clks IMX6SX_CLK_AUDIO>;\n+\t\tDCVDD-supply = <&vgen4_reg>;\n+\t\tDBVDD-supply = <&vgen4_reg>;\n+\t\tAVDD-supply = <&vgen4_reg>;\n+\t\tCPVDD-supply = <&vgen4_reg>;\n+\t\tMICVDD-supply = <&vgen3_reg>;\n+\t\tPLLVDD-supply = <&vgen4_reg>;\n+\t\tSPKVDD1-supply = <®_psu_5v>;\n+\t\tSPKVDD2-supply = <®_psu_5v>;\n+\t};\n+};\n+\n+&lcdif1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_lcd>;\n+\tlcd-supply = <®_lcd_3v3>;\n+\tdisplay = <&display0>;\n+\tstatus = \"okay\";\n+\n+\tdisplay0: display0 {\n+\t\tbits-per-pixel = <16>;\n+\t\tbus-width = <24>;\n+\n+\t\tdisplay-timings {\n+\t\t\tnative-mode = <&timing0>;\n+\t\t\ttiming0: timing0 {\n+\t\t\t\tclock-frequency = <33500000>;\n+\t\t\t\thactive = <800>;\n+\t\t\t\tvactive = <480>;\n+\t\t\t\thback-porch = <89>;\n+\t\t\t\thfront-porch = <164>;\n+\t\t\t\tvback-porch = <23>;\n+\t\t\t\tvfront-porch = <10>;\n+\t\t\t\thsync-len = <10>;\n+\t\t\t\tvsync-len = <10>;\n+\t\t\t\thsync-active = <0>;\n+\t\t\t\tvsync-active = <0>;\n+\t\t\t\tde-active = <1>;\n+\t\t\t\tpixelclk-active = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&pwm3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm3>;\n+\tstatus = \"okay\";\n+};\n+\n+&snvs_poweroff {\n+\tstatus = \"okay\";\n+};\n+\n+&sai1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_sai1>;\n+\tstatus = \"disabled\";\n+};\n+\n+&ssi2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart1>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart5 { /* for bluetooth */\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart5>;\n+\tuart-has-rtscts;\n+\tstatus = \"okay\";\n+};\n+\n+&usbotg1 {\n+\tvbus-supply = <®_usb_otg1_vbus>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usb_otg1_id>;\n+\tstatus = \"okay\";\n+};\n+\n+&usbotg2 {\n+\tvbus-supply = <®_usb_otg2_vbus>;\n+\tdr_mode = \"host\";\n+\tstatus = \"okay\";\n+};\n+\n+&usbphy1 {\n+\tfsl,tx-d-cal = <106>;\n+};\n+\n+&usbphy2 {\n+\tfsl,tx-d-cal = <106>;\n+};\n+\n+&usdhc2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc2>;\n+\tnon-removable;\n+\tno-1-8-v;\n+\tkeep-power-in-suspend;\n+\twakeup-source;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc3 {\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n+\tpinctrl-0 = <&pinctrl_usdhc3>;\n+\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n+\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n+\tbus-width = <8>;\n+\tcd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;\n+\tkeep-power-in-suspend;\n+\twakeup-source;\n+\tvmmc-supply = <&vcc_sd3>;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc4>;\n+\tcd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;\n+\tstatus = \"okay\";\n+};\n+\n+&wdog1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_wdog>;\n+\tfsl,ext-reset-output;\n+};\n+\n+&iomuxc {\n+\timx6x-sdb {\n+\t\tpinctrl_audmux: audmuxgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD\t0x120b0\n+\t\t\t\tMX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK\t0x130b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_enet1: enet1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_ENET1_MDIO__ENET1_MDIO\t0xa0b1\n+\t\t\t\tMX6SX_PAD_ENET1_MDC__ENET1_MDC\t\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN\t0x3081\n+\t\t\t\tMX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M\t0x91\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_enet_3v3: enet3v3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_ENET2_COL__GPIO2_IO_6\t\t0x80000000\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_enet2: enet2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC\t0xa0b9\n+\t\t\t\tMX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN\t0xa0b1\n+\t\t\t\tMX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3\t0x3081\n+\t\t\t\tMX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN\t0x3081\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_gpio_keys: gpio_keysgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059\n+\t\t\t\tMX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c1: i2c1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO01__I2C1_SDA\t\t0x4001b8b1\n+\t\t\t\tMX6SX_PAD_GPIO1_IO00__I2C1_SCL\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c3: i2c3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_KEY_ROW4__I2C3_SDA\t\t0x4001b8b1\n+\t\t\t\tMX6SX_PAD_KEY_COL4__I2C3_SCL\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_i2c4: i2c4grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_CSI_DATA07__I2C4_SDA\t\t0x4001b8b1\n+\t\t\t\tMX6SX_PAD_CSI_DATA06__I2C4_SCL\t\t0x4001b8b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_lcd: lcdgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_CLK__LCDIF1_CLK\t0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0\n+\t\t\t\tMX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_peri_3v3: peri3v3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16\t0x80000000\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_pwm3: pwm3grp-1 {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_qspi2: qspi2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1\n+\t\t\t\tMX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_vcc_sd3: vccsd3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_KEY_COL1__GPIO2_IO_11\t\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_sai1: sai1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0\t0x120b0\n+\t\t\t\tMX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0\t0x130b0\n+\t\t\t\tMX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK\t0x130b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_uart1: uart1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO04__UART1_TX\t\t0x1b0b1\n+\t\t\t\tMX6SX_PAD_GPIO1_IO05__UART1_RX\t\t0x1b0b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_uart5: uart5grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_KEY_ROW3__UART5_RX\t\t0x1b0b1\n+\t\t\t\tMX6SX_PAD_KEY_COL3__UART5_TX\t\t0x1b0b1\n+\t\t\t\tMX6SX_PAD_KEY_ROW2__UART5_CTS_B\t\t0x1b0b1\n+\t\t\t\tMX6SX_PAD_KEY_COL2__UART5_RTS_B\t\t0x1b0b1\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usb_otg1: usbotg1grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO09__GPIO1_IO_9\t0x10b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usb_otg1_id: usbotg1idgrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usb_otg2: usbot2ggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO12__GPIO1_IO_12\t0x10b0\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc2: usdhc2grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD2_CMD__USDHC2_CMD\t\t0x17059\n+\t\t\t\tMX6SX_PAD_SD2_CLK__USDHC2_CLK\t\t0x10059\n+\t\t\t\tMX6SX_PAD_SD2_DATA0__USDHC2_DATA0\t0x17059\n+\t\t\t\tMX6SX_PAD_SD2_DATA1__USDHC2_DATA1\t0x17059\n+\t\t\t\tMX6SX_PAD_SD2_DATA2__USDHC2_DATA2\t0x17059\n+\t\t\t\tMX6SX_PAD_SD2_DATA3__USDHC2_DATA3\t0x17059\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc3: usdhc3grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD3_CMD__USDHC3_CMD\t\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_CLK__USDHC3_CLK\t\t0x10059\n+\t\t\t\tMX6SX_PAD_SD3_DATA0__USDHC3_DATA0\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA1__USDHC3_DATA1\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA2__USDHC3_DATA2\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA3__USDHC3_DATA3\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA4__USDHC3_DATA4\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA5__USDHC3_DATA5\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA6__USDHC3_DATA6\t0x17059\n+\t\t\t\tMX6SX_PAD_SD3_DATA7__USDHC3_DATA7\t0x17059\n+\t\t\t\tMX6SX_PAD_KEY_COL0__GPIO2_IO_10\t\t0x17059 /* CD */\n+\t\t\t\tMX6SX_PAD_KEY_ROW0__GPIO2_IO_15\t\t0x17059 /* WP */\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc3_100mhz: usdhc3grp-100mhz {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD3_CMD__USDHC3_CMD\t\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_CLK__USDHC3_CLK\t\t0x100b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA0__USDHC3_DATA0\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA1__USDHC3_DATA1\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA2__USDHC3_DATA2\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA3__USDHC3_DATA3\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA4__USDHC3_DATA4\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA5__USDHC3_DATA5\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA6__USDHC3_DATA6\t0x170b9\n+\t\t\t\tMX6SX_PAD_SD3_DATA7__USDHC3_DATA7\t0x170b9\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc3_200mhz: usdhc3grp-200mhz {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD3_CMD__USDHC3_CMD\t\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_CLK__USDHC3_CLK\t\t0x100f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA0__USDHC3_DATA0\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA1__USDHC3_DATA1\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA2__USDHC3_DATA2\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA3__USDHC3_DATA3\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA4__USDHC3_DATA4\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA5__USDHC3_DATA5\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA6__USDHC3_DATA6\t0x170f9\n+\t\t\t\tMX6SX_PAD_SD3_DATA7__USDHC3_DATA7\t0x170f9\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_usdhc4: usdhc4grp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_SD4_CMD__USDHC4_CMD\t\t0x17059\n+\t\t\t\tMX6SX_PAD_SD4_CLK__USDHC4_CLK\t\t0x10059\n+\t\t\t\tMX6SX_PAD_SD4_DATA0__USDHC4_DATA0\t0x17059\n+\t\t\t\tMX6SX_PAD_SD4_DATA1__USDHC4_DATA1\t0x17059\n+\t\t\t\tMX6SX_PAD_SD4_DATA2__USDHC4_DATA2\t0x17059\n+\t\t\t\tMX6SX_PAD_SD4_DATA3__USDHC4_DATA3\t0x17059\n+\t\t\t\tMX6SX_PAD_SD4_DATA7__GPIO6_IO_21\t0x17059 /* CD */\n+\t\t\t\tMX6SX_PAD_SD4_DATA6__GPIO6_IO_20\t0x17059 /* WP */\n+\t\t\t>;\n+\t\t};\n+\n+\t\tpinctrl_wdog: wdoggrp {\n+\t\t\tfsl,pins = <\n+\t\t\t\tMX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0\n+\t\t\t>;\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "U-Boot", "V2", "02/12" ] }