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GET /api/patches/806382/?format=api
{ "id": 806382, "url": "http://patchwork.ozlabs.org/api/patches/806382/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170828062530.5789-1-aneesh.kumar@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20170828062530.5789-1-aneesh.kumar@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20170828062530.5789-1-aneesh.kumar@linux.vnet.ibm.com/", "date": "2017-08-28T06:25:30", "name": "powerpc/mm/cxl: Add barrier when setting mm cpumask", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d4c1d48ded672b7cfe0dba165bd59855eb3b6e41", "submitter": { "id": 664, "url": "http://patchwork.ozlabs.org/api/people/664/?format=api", "name": "Aneesh Kumar K.V", "email": "aneesh.kumar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170828062530.5789-1-aneesh.kumar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 81, "url": "http://patchwork.ozlabs.org/api/series/81/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=81", "date": "2017-08-28T06:25:30", "name": "powerpc/mm/cxl: Add barrier when setting mm cpumask", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/81/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806382/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806382/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xghfp4w2jz9s8P\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 28 Aug 2017 16:28:34 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xghfp3vYRzDqXs\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 28 Aug 2017 16:28:34 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xghc73KJQzDqGZ\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tMon, 28 Aug 2017 16:26:15 +1000 (AEST)", "from pps.filterd (m0098410.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7S6OSi9038158\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 28 Aug 2017 02:26:13 -0400", "from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cm2rpnhpj-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Mon, 28 Aug 2017 02:26:13 -0400", "from localhost\n\tby e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<aneesh.kumar@linux.vnet.ibm.com>; Mon, 28 Aug 2017 00:26:12 -0600", "from b03cxnp07029.gho.boulder.ibm.com (9.17.130.16)\n\tby e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tMon, 28 Aug 2017 00:26:10 -0600", "from b03ledav002.gho.boulder.ibm.com\n\t(b03ledav002.gho.boulder.ibm.com [9.17.130.233])\n\tby b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7S6Q9D48323436; Sun, 27 Aug 2017 23:26:09 -0700", "from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id B164E136044;\n\tMon, 28 Aug 2017 00:26:09 -0600 (MDT)", "from skywalker.in.ibm.com (unknown [9.124.35.86])\n\tby b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP id\n\tE46BC136040; Mon, 28 Aug 2017 00:26:07 -0600 (MDT)" ], "From": "\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>", "To": "benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au", "Subject": "[PATCH] powerpc/mm/cxl: Add barrier when setting mm cpumask", "Date": "Mon, 28 Aug 2017 11:55:30 +0530", "X-Mailer": "git-send-email 2.13.5", "X-TM-AS-GCONF": "00", "x-cbid": "17082806-0004-0000-0000-000012D5D0BA", "X-IBM-SpamModules-Scores": "", "X-IBM-SpamModules-Versions": "BY=3.00007625; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000225; SDB=6.00908682; UDB=6.00455635;\n\tIPR=6.00688922; \n\tBA=6.00005555; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016893;\n\tXFM=3.00000015; UTC=2017-08-28 06:26:12", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082806-0005-0000-0000-000080E2EFB7", "Message-Id": "<20170828062530.5789-1-aneesh.kumar@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-28_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708280103", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "linuxppc-dev@lists.ozlabs.org,\n\t\"Aneesh Kumar K.V\" <aneesh.kumar@linux.vnet.ibm.com>,\n\tAndrew Donnellan <andrew.donnellan@au1.ibm.com>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "We need to add memory barrier so that the page table walk doesn't happen\nbefore the cpumask is set and made visible to the other cpus. We need\nto use a sync here instead of lwsync because lwsync is not sufficient for\nstore/load ordering.\n\nWe also need to add an if (mm) check so that we do the right thing when called\nwith a kernel context. For kernel context, we have mm = NULL. W.r.t kernel\naddress we can skip setting the mm cpumask.\n\nFixes: 0f4bc0932e (\"powerpc/mm/cxl: Add the fault handling cpu to mm cpumask\")\nCc: Andrew Donnellan <andrew.donnellan@au1.ibm.com>\nReported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n---\n drivers/misc/cxl/fault.c | 14 ++++++++++++--\n 1 file changed, 12 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c\nindex ab507e4ed69b..caed2a523bee 100644\n--- a/drivers/misc/cxl/fault.c\n+++ b/drivers/misc/cxl/fault.c\n@@ -141,9 +141,19 @@ int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar)\n \t/*\n \t * Add the fault handling cpu to task mm cpumask so that we\n \t * can do a safe lockless page table walk when inserting the\n-\t * hash page table entry.\n+\t * hash page table entry. This function get called with a\n+\t * valid mm for all user space applications. Hence using\n+\t * if (mm) check is sufficient here.\n \t */\n-\tcpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));\n+\tif (mm) {\n+\t\tcpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));\n+\t\t/*\n+\t\t * We need to make sure we walk the table only after\n+\t\t * we update the cpumask. The other side of the barrier is\n+\t\t * explained * in serialize_against_pte_lookup()\n+\t\t */\n+\t\tsmp_mb();\n+\t}\n \tif ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) {\n \t\tpr_devel(\"copro_handle_mm_fault failed: %#x\\n\", result);\n \t\treturn result;\n", "prefixes": [] }