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GET /api/patches/806353/?format=api
{ "id": 806353, "url": "http://patchwork.ozlabs.org/api/patches/806353/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170828035327.17146-3-bobby.prani@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828035327.17146-3-bobby.prani@gmail.com>", "list_archive_url": null, "date": "2017-08-28T03:53:26", "name": "[RFC,3/3] mttcg: Implement implicit ordering semantics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c3e59d2edd8046e36f14d2e5fae51b14a7d1c070", "submitter": { "id": 64653, "url": "http://patchwork.ozlabs.org/api/people/64653/?format=api", "name": "Pranith Kumar", "email": "bobby.prani@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170828035327.17146-3-bobby.prani@gmail.com/mbox/", "series": [ { "id": 63, "url": "http://patchwork.ozlabs.org/api/series/63/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=63", "date": "2017-08-28T03:53:26", "name": null, "version": 1, "mbox": "http://patchwork.ozlabs.org/series/63/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806353/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806353/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"HwAHAtEt\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xgdDk0Qq4z9sNr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 13:54:11 +1000 (AEST)", "from localhost ([::1]:36793 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dmB7o-0003kj-Hk\n\tfor incoming@patchwork.ozlabs.org; Sun, 27 Aug 2017 23:54:08 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:55762)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dmB7I-0003jE-0C\n\tfor qemu-devel@nongnu.org; Sun, 27 Aug 2017 23:53:37 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <bobby.prani@gmail.com>) id 1dmB7G-00042k-T6\n\tfor qemu-devel@nongnu.org; Sun, 27 Aug 2017 23:53:36 -0400", "from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34179)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <bobby.prani@gmail.com>)\n\tid 1dmB7D-0003xh-AP; Sun, 27 Aug 2017 23:53:31 -0400", "by mail-yw0-x242.google.com with SMTP id h127so2734835ywf.1;\n\tSun, 27 Aug 2017 20:53:31 -0700 (PDT)", "from localhost.localdomain ([98.192.46.210])\n\tby smtp.gmail.com with ESMTPSA id\n\ti64sm4820865ywi.64.2017.08.27.20.53.29\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 27 Aug 2017 20:53:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=;\n\tb=HwAHAtEtDIZQHZHlwbzcsSIOxxnA54XSXqkewVNX28Kv5f15J1hh8ZA6DfQyqKIqCd\n\tQe54VTIarZeQF2XZWprouccFPkKq00SiWEXxdbuUxokG/3YusYDSiAs/GrR5kqOGhW3b\n\tGeRbBXn6KmGnBWix0BuZmyS80o8kYvN68f45H5Aqgl8W6Yw7EBRTa3CJmrS1f4Lywr0E\n\tUCSaZujo5H8/xUcAPEQ3Y6Af/nr/4wUXHB2ligsC//z060azMW5Pl4HrTHdxd45AonHx\n\tnPQ9HNZxDSqPE3EUmO6wrEVNsL7JPZN8+hASITWHSDYXt5HY6n9rZxMcmTuX1NamxWnW\n\tBhKg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=;\n\tb=H55lNEfAy/sN72TQ8/HopOof0JUZS8dK/Y/qzWPqiU/TuBksAvTr9e1mpfYHNZWmLt\n\td9f807zjFIzJuTWurlJAP6ZE2sqca0qAgNfcIiZxlKz3qkEwUxRjfrli9l+7o57dMvv6\n\tfFSoxx8inSnOCs+2LkB4nLsRfaPbUNFUrpHbJecDQ3APcfCPasRhl7xWPLDWLSq92Oy4\n\t1tkqUuxgWbI6V9KVua6eV3KQSpYxIZ9KKxHKOVZaoZa1OUrIopjVxmGqi4V9vqjWsetX\n\tfnp7KSlJReM7+VMGiSs65UjCdBCasce4Mpm7CutMOeEDiBBXJ2EnH0Gvl+c05TMy2mTi\n\toYHQ==", "X-Gm-Message-State": "AHYfb5g9wXiNd4ZiHsEATG6y1sKYrtCoC4N4mIxisqsHGstl7Cd9u0Uv\n\tmfy1hI1VcWqWlQ==", "X-Received": "by 10.37.14.212 with SMTP id 203mr4858559ybo.164.1503892410621; \n\tSun, 27 Aug 2017 20:53:30 -0700 (PDT)", "From": "Pranith Kumar <bobby.prani@gmail.com>", "To": "alex.bennee@linaro.org, Claudio Fontana <claudio.fontana@huawei.com>,\n\tRichard Henderson <rth@twiddle.net>,\n\tAndrzej Zaborowski <balrogg@gmail.com>,\n\tAurelien Jarno <aurelien@aurel32.net>,\n\tqemu-arm@nongnu.org (open list:AArch64 target),\n\tqemu-devel@nongnu.org (open list:All patches CC here)", "Date": "Sun, 27 Aug 2017 23:53:26 -0400", "Message-Id": "<20170828035327.17146-3-bobby.prani@gmail.com>", "X-Mailer": "git-send-email 2.13.0", "In-Reply-To": "<20170828035327.17146-1-bobby.prani@gmail.com>", "References": "<20170828035327.17146-1-bobby.prani@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:4002:c05::242", "Subject": "[Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering\n\tsemantics", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "pbonzini@redhat.com, qemu-devel@nongnu.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Currently, we cannot use mttcg for running strong memory model guests\non weak memory model hosts due to missing ordering semantics.\n\nWe implicitly generate fence instructions for stronger guests if an\nordering mismatch is detected. We generate fences only for the orders\nfor which fence instructions are necessary, for example a fence is not\nnecessary between a store and a subsequent load on x86 since its\nabsence in the guest binary tells that ordering need not be\nensured. Also note that if we find multiple subsequent fence\ninstructions in the generated IR, we combine them in the TCG\noptimization pass.\n\nThis patch allows us to boot an x86 guest on ARM64 hosts using mttcg.\n\nSigned-off-by: Pranith Kumar <bobby.prani@gmail.com>\n---\n tcg/aarch64/tcg-target.h | 2 ++\n tcg/arm/tcg-target.h | 2 ++\n tcg/mips/tcg-target.h | 2 ++\n tcg/ppc/tcg-target.h | 2 ++\n tcg/tcg-op.c | 17 +++++++++++++++++\n tcg/tcg-op.h | 1 +\n 6 files changed, 26 insertions(+)", "diff": "diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\nindex 55a46ac825..b41a248bee 100644\n--- a/tcg/aarch64/tcg-target.h\n+++ b/tcg/aarch64/tcg-target.h\n@@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n __builtin___clear_cache((char *)start, (char *)stop);\n }\n \n+#define TCG_TARGET_DEFAULT_MO (0)\n+\n #endif /* AARCH64_TCG_TARGET_H */\ndiff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h\nindex 5ef1086710..a38be15a39 100644\n--- a/tcg/arm/tcg-target.h\n+++ b/tcg/arm/tcg-target.h\n@@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n __builtin___clear_cache((char *) start, (char *) stop);\n }\n \n+#define TCG_TARGET_DEFAULT_MO (0)\n+\n #endif\ndiff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h\nindex d75cb63ed3..e9558d15bc 100644\n--- a/tcg/mips/tcg-target.h\n+++ b/tcg/mips/tcg-target.h\n@@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n cacheflush ((void *)start, stop-start, ICACHE);\n }\n \n+#define TCG_TARGET_DEFAULT_MO (0)\n+\n #endif\ndiff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h\nindex 5f4a40a5b4..5a092b038a 100644\n--- a/tcg/ppc/tcg-target.h\n+++ b/tcg/ppc/tcg-target.h\n@@ -125,4 +125,6 @@ extern bool have_isa_3_00;\n \n void flush_icache_range(uintptr_t start, uintptr_t stop);\n \n+#define TCG_TARGET_DEFAULT_MO (0)\n+\n #endif\ndiff --git a/tcg/tcg-op.c b/tcg/tcg-op.c\nindex 87f673ef49..085fe66fb2 100644\n--- a/tcg/tcg-op.c\n+++ b/tcg/tcg-op.c\n@@ -28,6 +28,7 @@\n #include \"exec/exec-all.h\"\n #include \"tcg.h\"\n #include \"tcg-op.h\"\n+#include \"tcg-mo.h\"\n #include \"trace-tcg.h\"\n #include \"trace/mem.h\"\n \n@@ -2662,8 +2663,21 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,\n #endif\n }\n \n+void tcg_gen_req_mo(TCGBar type)\n+{\n+#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)\n+ TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO);\n+ if (order_mismatch) {\n+ tcg_gen_mb(order_mismatch | TCG_BAR_SC);\n+ }\n+#else\n+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n+#endif\n+}\n+\n void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST);\n memop = tcg_canonicalize_memop(memop, 0, 0);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 0));\n@@ -2672,6 +2686,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST);\n memop = tcg_canonicalize_memop(memop, 0, 1);\n trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,\n addr, trace_mem_get_info(memop, 1));\n@@ -2680,6 +2695,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);\n if (memop & MO_SIGN) {\n@@ -2698,6 +2714,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n \n void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)\n {\n+ tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST);\n if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {\n tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);\n return;\ndiff --git a/tcg/tcg-op.h b/tcg/tcg-op.h\nindex 5d3278f243..6ad2c6d60e 100644\n--- a/tcg/tcg-op.h\n+++ b/tcg/tcg-op.h\n@@ -262,6 +262,7 @@ static inline void tcg_gen_br(TCGLabel *l)\n }\n \n void tcg_gen_mb(TCGBar);\n+void tcg_gen_req_mo(TCGBar type);\n \n /* Helper calls. */\n \n", "prefixes": [ "RFC", "3/3" ] }