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GET /api/patches/806341/?format=api
{ "id": 806341, "url": "http://patchwork.ozlabs.org/api/patches/806341/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170828015654.2530-11-Sergio.G.DelReal@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828015654.2530-11-Sergio.G.DelReal@gmail.com>", "list_archive_url": null, "date": "2017-08-28T01:56:50", "name": "[10/14] hvf: refactor cpuid code", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8481fd20731bdaa49c65e7bd3300eaf27eb3df82", "submitter": { "id": 70675, "url": "http://patchwork.ozlabs.org/api/people/70675/?format=api", "name": "Sergio Andres Gomez Del Real", "email": "sergio.g.delreal@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170828015654.2530-11-Sergio.G.DelReal@gmail.com/mbox/", "series": [ { "id": 56, "url": "http://patchwork.ozlabs.org/api/series/56/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=56", "date": "2017-08-28T01:56:40", "name": "add support for Hypervisor.framework in QEMU", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/56/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806341/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806341/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"VKHnlbNI\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xgZkL2FGJz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 12:01:14 +1000 (AEST)", "from localhost ([::1]:36511 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dm9MW-0007TI-3c\n\tfor incoming@patchwork.ozlabs.org; Sun, 27 Aug 2017 22:01:12 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:42106)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dm9JD-00054a-Vb\n\tfor qemu-devel@nongnu.org; Sun, 27 Aug 2017 21:57:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sergio.g.delreal@gmail.com>) id 1dm9JB-0001EZ-O4\n\tfor qemu-devel@nongnu.org; Sun, 27 Aug 2017 21:57:48 -0400", "from mail-ua0-x241.google.com ([2607:f8b0:400c:c08::241]:34979)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sergio.g.delreal@gmail.com>)\n\tid 1dm9JB-0001EF-Hc\n\tfor qemu-devel@nongnu.org; Sun, 27 Aug 2017 21:57:45 -0400", "by mail-ua0-x241.google.com with SMTP id j45so2016921uaf.2\n\tfor <qemu-devel@nongnu.org>; Sun, 27 Aug 2017 18:57:45 -0700 (PDT)", "from localhost.localdomain ([191.109.6.191])\n\tby smtp.gmail.com with ESMTPSA id\n\ty12sm2696824uad.22.2017.08.27.18.57.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 27 Aug 2017 18:57:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=fsRabrrOpRm5eKki328wcGEqUVd9MpvL3rHbTO5POG0=;\n\tb=VKHnlbNI8YYS+1v2kylCGDYhWL15k/UAa3Dli4qmXkb5utt00t0TYPXeDdOesMaLts\n\thR920Ahg5wZzSAkknxhgQiqxBov+kRzi43FZGYLkfCCDRnHfQbMciobG3qgQ24PVgewC\n\tzllo3JplbtBe5ydGsXlOTiOwp4Pe5+I2NLi7/ai8ZqKerdytubab4wUCzB/ebOd/0ant\n\tbhmIXILUWaXN+hMf3GM0Lrxbax3XKkE+M0Rk6ZqKz3hB3MvCUGLhjoOYHaMa8FctUqPE\n\t/O4kWRJCQ7ZxcnhXs1CQEzpOg2fkCZbtsyTUr/AK8qLDZyyb+navmyFQPSt72NLnVZtB\n\twFFw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=fsRabrrOpRm5eKki328wcGEqUVd9MpvL3rHbTO5POG0=;\n\tb=GvKvtu77q7rFZu8I5Q4cog3edpVa73gxw4+3bl188ZkVJ9tSnEL/7TAHgPFn5CMLI8\n\tXvdEnOfsRa2riol5uzL+/N2Q54WARMapDbz27tUFuHZZLqFXVNWfFio7b/E6bQn/Hu2e\n\tECcF8hO/unB6mEK/8MO+Dj7DutI6nRCHpPhCIGQlZVyOR1EW4caDnMRFXkc7RxC7V3Du\n\tf/wSODhNxFc52Q51Yq64zBsNxrlfX4bE/Gz8+DZ2PZ4kkpHXczKK8XsSk2jjMYUwF/4m\n\tltMbJqgbE8+ioSB9aAddrxYMG3e1AYrx020x8wTWYNT2atwAht+jdxPf3WQDN3vSfMiY\n\tsIMA==", "X-Gm-Message-State": "AHYfb5hD++TUYpNdDWZafUetCcH0MljqyuOCEBWe0o0WbOtiH1aObyAF\n\ty1pLoyXfLUkP1IyW", "X-Received": "by 10.176.89.133 with SMTP id g5mr4189223uad.39.1503885464622;\n\tSun, 27 Aug 2017 18:57:44 -0700 (PDT)", "From": "Sergio Andres Gomez Del Real <sergio.g.delreal@gmail.com>", "X-Google-Original-From": "Sergio Andres Gomez Del Real\n\t<Sergio.G.DelReal@gmail.com>", "To": "qemu-devel@nongnu.org", "Date": "Sun, 27 Aug 2017 20:56:50 -0500", "Message-Id": "<20170828015654.2530-11-Sergio.G.DelReal@gmail.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": "<20170828015654.2530-1-Sergio.G.DelReal@gmail.com>", "References": "<20170828015654.2530-1-Sergio.G.DelReal@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400c:c08::241", "Subject": "[Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "This commit adds code to request the cpuid features supported by the\nhost and hvf; it calls hvf_get_supported_cpuid if hvf is compiled with\nQEMU and enabled.\n\nSigned-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>\n---\n cpus.c | 2 +\n include/qom/cpu.h | 6 +--\n include/sysemu/hvf.h | 18 ++++++---\n target/i386/cpu-qom.h | 4 +-\n target/i386/cpu.c | 108 ++++++++++++++++++++++++++++++++++++++++----------\n target/i386/hvf-all.c | 20 +++++-----\n 6 files changed, 113 insertions(+), 45 deletions(-)", "diff": "diff --git a/cpus.c b/cpus.c\nindex 6754ce17cc..2411dfcd3f 100644\n--- a/cpus.c\n+++ b/cpus.c\n@@ -37,7 +37,9 @@\n #include \"sysemu/hw_accel.h\"\n #include \"sysemu/kvm.h\"\n #include \"sysemu/hax.h\"\n+#ifdef CONFIG_HVF\n #include \"sysemu/hvf.h\"\n+#endif\n #include \"qmp-commands.h\"\n #include \"exec/exec-all.h\"\n \ndiff --git a/include/qom/cpu.h b/include/qom/cpu.h\nindex c46eb61240..ef74c2ce3c 100644\n--- a/include/qom/cpu.h\n+++ b/include/qom/cpu.h\n@@ -408,13 +408,9 @@ struct CPUState {\n */\n uint16_t pending_tlb_flush;\n \n- // HVF\n bool hvf_vcpu_dirty;\n uint64_t hvf_fd; // fd of vcpu created by HVF\n- // Supporting data structures for VMCS capabilities\n- // and x86 emulation state\n- struct hvf_vcpu_caps* hvf_caps;\n- struct hvf_x86_state* hvf_x86;\n+ struct hvf_x86_state *hvf_x86;\n };\n \n QTAILQ_HEAD(CPUTailQ, CPUState);\ndiff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h\nindex f9a5a9c5d3..5b92769b16 100644\n--- a/include/sysemu/hvf.h\n+++ b/include/sysemu/hvf.h\n@@ -34,12 +34,6 @@ typedef struct hvf_slot {\n int slot_id;\n } hvf_slot;\n \n-typedef struct HVFState {\n- AccelState parent;\n- hvf_slot slots[32];\n- int num_slots;\n-} HVFState;\n-\n struct hvf_vcpu_caps {\n uint64_t vmx_cap_pinbased;\n uint64_t vmx_cap_procbased;\n@@ -49,6 +43,15 @@ struct hvf_vcpu_caps {\n uint64_t vmx_cap_preemption_timer;\n };\n \n+typedef struct HVFState {\n+ AccelState parent;\n+ hvf_slot slots[32];\n+ int num_slots;\n+\n+ struct hvf_vcpu_caps *hvf_caps;\n+} HVFState;\n+extern HVFState *hvf_state;\n+\n void hvf_set_phys_mem(MemoryRegionSection *, bool);\n void hvf_handle_io(CPUArchState *, uint16_t, void *,\n int, int, int);\n@@ -87,6 +90,9 @@ void update_apic_tpr(CPUState *);\n int hvf_put_registers(CPUState *);\n void vmx_clear_int_window_exiting(CPUState *cpu);\n \n+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,\n+ int reg);\n+\n #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME(\"hvf\")\n \n #define HVF_STATE(obj) \\\ndiff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h\nindex c2205e6077..22f95eb3a4 100644\n--- a/target/i386/cpu-qom.h\n+++ b/target/i386/cpu-qom.h\n@@ -47,7 +47,7 @@ typedef struct X86CPUDefinition X86CPUDefinition;\n /**\n * X86CPUClass:\n * @cpu_def: CPU model definition\n- * @kvm_required: Whether CPU model requires KVM to be enabled.\n+ * @host_cpuid_required: Whether CPU model requires cpuid from host.\n * @ordering: Ordering on the \"-cpu help\" CPU model list.\n * @migration_safe: See CpuDefinitionInfo::migration_safe\n * @static_model: See CpuDefinitionInfo::static\n@@ -66,7 +66,7 @@ typedef struct X86CPUClass {\n */\n X86CPUDefinition *cpu_def;\n \n- bool kvm_required;\n+ bool host_cpuid_required;\n int ordering;\n bool migration_safe;\n bool static_model;\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex ddc45abd70..8c531a0ffa 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -22,6 +22,9 @@\n #include \"cpu.h\"\n #include \"exec/exec-all.h\"\n #include \"sysemu/kvm.h\"\n+#ifdef CONFIG_HVF\n+#include \"sysemu/hvf.h\"\n+#endif\n #include \"sysemu/cpus.h\"\n #include \"kvm_i386.h\"\n \n@@ -613,6 +616,23 @@ static uint32_t xsave_area_size(uint64_t mask)\n return ret;\n }\n \n+static inline bool accel_uses_host_cpuid(void)\n+{\n+ bool enabled;\n+#if defined(CONFIG_KVM)\n+ enabled = kvm_enabled();\n+#elif defined(CONFIG_HVF)\n+ enabled = hvf_enabled();\n+#else\n+ enabled = 0;\n+#endif\n+ if (enabled) {\n+ return true;\n+ } else {\n+ return false;\n+ }\n+}\n+\n static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)\n {\n return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |\n@@ -1643,10 +1663,15 @@ static void max_x86_cpu_initfn(Object *obj)\n */\n cpu->max_features = true;\n \n- if (kvm_enabled()) {\n+ if (accel_uses_host_cpuid()) {\n char vendor[CPUID_VENDOR_SZ + 1] = { 0 };\n char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };\n int family, model, stepping;\n+ X86CPUDefinition host_cpudef = { };\n+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;\n+\n+ host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);\n+ x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);\n \n host_vendor_fms(vendor, &family, &model, &stepping);\n \n@@ -1660,12 +1685,23 @@ static void max_x86_cpu_initfn(Object *obj)\n object_property_set_str(OBJECT(cpu), model_id, \"model-id\",\n &error_abort);\n \n- env->cpuid_min_level =\n- kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);\n- env->cpuid_min_xlevel =\n- kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);\n- env->cpuid_min_xlevel2 =\n- kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);\n+ if (kvm_enabled()) {\n+ env->cpuid_min_level =\n+ kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);\n+ env->cpuid_min_xlevel =\n+ kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);\n+ env->cpuid_min_xlevel2 =\n+ kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);\n+ } else {\n+#if defined(CONFIG_HVF)\n+ env->cpuid_min_level =\n+ hvf_get_supported_cpuid(0x0, 0, R_EAX);\n+ env->cpuid_min_xlevel =\n+ hvf_get_supported_cpuid(0x80000000, 0, R_EAX);\n+ env->cpuid_min_xlevel2 =\n+ hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);\n+#endif\n+ }\n \n if (lmce_supported()) {\n object_property_set_bool(OBJECT(cpu), true, \"lmce\", &error_abort);\n@@ -1691,18 +1727,25 @@ static const TypeInfo max_x86_cpu_type_info = {\n .class_init = max_x86_cpu_class_init,\n };\n \n-#ifdef CONFIG_KVM\n-\n+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)\n static void host_x86_cpu_class_init(ObjectClass *oc, void *data)\n {\n X86CPUClass *xcc = X86_CPU_CLASS(oc);\n \n- xcc->kvm_required = true;\n+ xcc->host_cpuid_required = true;\n xcc->ordering = 8;\n \n- xcc->model_description =\n- \"KVM processor with all supported host features \"\n- \"(only available in KVM mode)\";\n+#if defined(CONFIG_KVM)\n+ if (kvm_enabled()) {\n+ xcc->model_description =\n+ \"KVM processor with all supported host features \";\n+ } \n+#elif defined(CONFIG_HVF)\n+ if (hvf_enabled()) {\n+ xcc->model_description =\n+ \"HVF processor with all supported host features \";\n+ }\n+#endif\n }\n \n static const TypeInfo host_x86_cpu_type_info = {\n@@ -1724,7 +1767,7 @@ static void report_unavailable_features(FeatureWord w, uint32_t mask)\n assert(reg);\n fprintf(stderr, \"warning: %s doesn't support requested feature: \"\n \"CPUID.%02XH:%s%s%s [bit %d]\\n\",\n- kvm_enabled() ? \"host\" : \"TCG\",\n+ accel_uses_host_cpuid() ? \"host\" : \"TCG\",\n f->cpuid_eax, reg,\n f->feat_names[i] ? \".\" : \"\",\n f->feat_names[i] ? f->feat_names[i] : \"\", i);\n@@ -2175,7 +2218,7 @@ static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,\n Error *err = NULL;\n strList **next = missing_feats;\n \n- if (xcc->kvm_required && !kvm_enabled()) {\n+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {\n strList *new = g_new0(strList, 1);\n new->value = g_strdup(\"kvm\");;\n *missing_feats = new;\n@@ -2337,7 +2380,15 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,\n r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,\n wi->cpuid_ecx,\n wi->cpuid_reg);\n- } else if (tcg_enabled()) {\n+ }\n+#if defined(CONFIG_HVF)\n+ else if (hvf_enabled()) {\n+ r = hvf_get_supported_cpuid(wi->cpuid_eax,\n+ wi->cpuid_ecx,\n+ wi->cpuid_reg);\n+ }\n+#endif\n+ else if (tcg_enabled()) {\n r = wi->tcg_features;\n } else {\n return ~0;\n@@ -2396,6 +2447,7 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)\n }\n \n /* Special cases not set in the X86CPUDefinition structs: */\n+ /* TODO: implement for hvf */\n if (kvm_enabled()) {\n if (!kvm_irqchip_in_kernel()) {\n x86_cpu_change_kvm_default(\"x2apic\", \"off\");\n@@ -2416,7 +2468,7 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)\n * when doing cross vendor migration\n */\n vendor = def->vendor;\n- if (kvm_enabled()) {\n+ if (accel_uses_host_cpuid()) {\n uint32_t ebx = 0, ecx = 0, edx = 0;\n host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);\n x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);\n@@ -2872,7 +2924,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,\n *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);\n *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);\n *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);\n- } else {\n+ }\n+#if defined(CONFIG_HVF)\n+ else if (hvf_enabled() && cpu->enable_pmu) {\n+ *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);\n+ *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);\n+ *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);\n+ *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);\n+ }\n+#endif\n+ else {\n *eax = 0;\n *ebx = 0;\n *ecx = 0;\n@@ -3220,6 +3281,7 @@ static void x86_cpu_reset(CPUState *s)\n \n s->halted = !cpu_is_bsp(cpu);\n \n+ /* TODO: implement for hvf */\n if (kvm_enabled()) {\n kvm_arch_reset_vcpu(cpu);\n }\n@@ -3262,6 +3324,7 @@ APICCommonClass *apic_get_class(void)\n {\n const char *apic_type = \"apic\";\n \n+ /* TODO: implement for hvf */\n if (kvm_apic_in_kernel()) {\n apic_type = \"kvm-apic\";\n } else if (xen_enabled()) {\n@@ -3492,6 +3555,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)\n }\n }\n \n+ /* TODO: implement for hvf */\n if (!kvm_enabled() || !cpu->expose_kvm) {\n env->features[FEAT_KVM] = 0;\n }\n@@ -3575,7 +3639,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)\n Error *local_err = NULL;\n static bool ht_warned;\n \n- if (xcc->kvm_required && !kvm_enabled()) {\n+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {\n char *name = x86_cpu_class_get_model_name(xcc);\n error_setg(&local_err, \"CPU model '%s' requires KVM\", name);\n g_free(name);\n@@ -3597,7 +3661,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)\n x86_cpu_report_filtered_features(cpu);\n if (cpu->enforce_cpuid) {\n error_setg(&local_err,\n- kvm_enabled() ?\n+ accel_uses_host_cpuid() ?\n \"Host doesn't support requested features\" :\n \"TCG doesn't support requested features\");\n goto out;\n@@ -3620,7 +3684,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)\n * consumer AMD devices but nothing else.\n */\n if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {\n- if (kvm_enabled()) {\n+ if (accel_uses_host_cpuid()) {\n uint32_t host_phys_bits = x86_host_phys_bits();\n static bool warned;\n \n@@ -4207,7 +4271,7 @@ static void x86_cpu_register_types(void)\n }\n type_register_static(&max_x86_cpu_type_info);\n type_register_static(&x86_base_cpu_type_info);\n-#ifdef CONFIG_KVM\n+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)\n type_register_static(&host_x86_cpu_type_info);\n #endif\n }\ndiff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c\nindex 88b5281975..11d20671f7 100644\n--- a/target/i386/hvf-all.c\n+++ b/target/i386/hvf-all.c\n@@ -604,7 +604,7 @@ int hvf_init_vcpu(CPUState *cpu)\n init_decoder(cpu);\n init_cpuid(cpu);\n \n- cpu->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));\n+ hvf_state->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));\n cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));\n \n r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);\n@@ -612,37 +612,37 @@ int hvf_init_vcpu(CPUState *cpu)\n assert_hvf_ok(r);\n \n if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,\n- &cpu->hvf_caps->vmx_cap_pinbased)) {\n+ &hvf_state->hvf_caps->vmx_cap_pinbased)) {\n abort();\n }\n if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED,\n- &cpu->hvf_caps->vmx_cap_procbased)) {\n+ &hvf_state->hvf_caps->vmx_cap_procbased)) {\n abort();\n }\n if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2,\n- &cpu->hvf_caps->vmx_cap_procbased2)) {\n+ &hvf_state->hvf_caps->vmx_cap_procbased2)) {\n abort();\n }\n if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY,\n- &cpu->hvf_caps->vmx_cap_entry)) {\n+ &hvf_state->hvf_caps->vmx_cap_entry)) {\n abort();\n }\n \n /* set VMCS control fields */\n wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS,\n- cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));\n+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 0));\n wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS,\n- cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,\n+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,\n VMCS_PRI_PROC_BASED_CTLS_HLT |\n VMCS_PRI_PROC_BASED_CTLS_MWAIT |\n VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |\n VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |\n VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);\n wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,\n- cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,\n+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,\n VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));\n \n- wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry,\n+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,\n 0));\n wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */\n \n@@ -829,7 +829,7 @@ int hvf_vcpu_exec(CPUState *cpu)\n uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);\n uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);\n \n- cpu_x86_cpuid(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);\n+ cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);\n \n wreg(cpu->hvf_fd, HV_X86_RAX, rax);\n wreg(cpu->hvf_fd, HV_X86_RBX, rbx);\n", "prefixes": [ "10/14" ] }