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GET /api/patches/806337/?format=api
HTTP 200 OK
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{
    "id": 806337,
    "url": "http://patchwork.ozlabs.org/api/patches/806337/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1503885509-25335-1-git-send-email-andy.yan@rock-chips.com/",
    "project": {
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        "name": "Linux MTD development",
        "link_name": "linux-mtd",
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        "list_email": "linux-mtd@lists.infradead.org",
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        "list_archive_url_format": "",
        "commit_url_format": ""
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    "msgid": "<1503885509-25335-1-git-send-email-andy.yan@rock-chips.com>",
    "list_archive_url": null,
    "date": "2017-08-28T01:58:29",
    "name": "[v7,1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "b4d70692785043472a4baf3b4efff393e2dd3efe",
    "submitter": {
        "id": 65124,
        "url": "http://patchwork.ozlabs.org/api/people/65124/?format=api",
        "name": "Andy Yan",
        "email": "andy.yan@rock-chips.com"
    },
    "delegate": {
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        "url": "http://patchwork.ozlabs.org/api/users/63396/?format=api",
        "username": "cpitchen",
        "first_name": "Cyrille",
        "last_name": "Pitchen",
        "email": "cyrille.pitchen@atmel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/1503885509-25335-1-git-send-email-andy.yan@rock-chips.com/mbox/",
    "series": [
        {
            "id": 57,
            "url": "http://patchwork.ozlabs.org/api/series/57/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=57",
            "date": "2017-08-28T01:58:29",
            "name": "[v7,1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info",
            "version": 7,
            "mbox": "http://patchwork.ozlabs.org/series/57/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/806337/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/806337/checks/",
    "tags": {},
    "related": [],
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        ],
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        "X-RL-SENDER": "andy.yan@rock-chips.com",
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        "From": "Andy Yan <andy.yan@rock-chips.com>",
        "To": "cyrille.pitchen@wedev4u.fr",
        "Subject": "[PATCH v7 1/2] mtd: spi-nor: add a quad_enable callback in struct\n\tflash_info",
        "Date": "Mon, 28 Aug 2017 09:58:29 +0800",
        "Message-Id": "<1503885509-25335-1-git-send-email-andy.yan@rock-chips.com>",
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        "X-Spam-Score": "-1.4 (-)",
        "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.4 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [211.150.99.135 listed in list.dnswl.org]\n\t-2.8 RCVD_IN_MSPIKE_H2      RBL: Average reputation (+2)\n\t[211.150.99.135 listed in wl.mailspike.net]\n\t3.3 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS\n\t[58.22.7.114 listed in zen.spamhaus.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]",
        "X-BeenThere": "linux-mtd@lists.infradead.org",
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        "Cc": "boris.brezillon@free-electrons.com, richard@nod.at,\n\tlinux-kernel@vger.kernel.org, marek.vasut@gmail.com,\n\tlinux-mtd@lists.infradead.org, Andy Yan <andy.yan@rock-chips.com>,\n\tcomputersforpeace@gmail.com, dwmw2@infradead.org",
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        "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>",
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    },
    "content": "Some manufacturers may use different bit to set QE on different\nmemories.\n\nThe GD25Q256 from GigaDevice is an example, which uses S6(bit 6\nof the Status Register-1) to set QE, which is different with\nother supported memories from GigaDevice that use S9(bit 1 of\nthe Status Register-2). This makes it is impossible to select\nthe quad enable method by distinguishing the MFR. This patch\nintroduce a quad_enable function which can be set per memory\nin the flash_info list table.\n\nSigned-off-by: Andy Yan <andy.yan@rock-chips.com>\n\n---\n\nChanges in v7:\n- fix some typos.\n\nChanges in v6:\n- split the quad_enable callback to a single patch\n- adjust the columns per line of the commit message.\n\nChanges in v5:\n- set quad_enable in flash_info list, thanks the guidance by Cyrille.\n\nChanges in v4:\n- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB\n\nChanges in v3:\n- rebase on top of spi-nor tree\n- add SPI_NOR_4B_OPCODES flag\n\nChanges in v2:\n- drop one line unnecessary modification\n\n drivers/mtd/spi-nor/spi-nor.c | 11 +++++++++++\n 1 file changed, 11 insertions(+)",
    "diff": "diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c\nindex cf1d4a1..3b94308 100644\n--- a/drivers/mtd/spi-nor/spi-nor.c\n+++ b/drivers/mtd/spi-nor/spi-nor.c\n@@ -89,6 +89,8 @@ struct flash_info {\n #define NO_CHIP_ERASE\t\tBIT(12) /* Chip does not support chip erase */\n #define SPI_NOR_SKIP_SFDP\tBIT(13)\t/* Skip parsing of SFDP tables */\n #define USE_CLSR\t\tBIT(14)\t/* use CLSR command */\n+\n+\tint\t(*quad_enable)(struct spi_nor *nor);\n };\n \n #define JEDEC_MFR(info)\t((info)->id[0])\n@@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,\n \t\t\tparams->quad_enable = spansion_quad_enable;\n \t\t\tbreak;\n \t\t}\n+\n+\t\t/*\n+\t\t * Some manufacturer like GigaDevice may use different\n+\t\t * bit to set QE on different memories, so the MFR can't\n+\t\t * indicate the quad_enable method for this case, we need\n+\t\t * set it in flash info list.\n+\t\t */\n+\t\tif (info->quad_enable)\n+\t\t\tparams->quad_enable = info->quad_enable;\n \t}\n \n \t/* Override the parameters with data read from SFDP tables. */\n",
    "prefixes": [
        "v7",
        "1/2"
    ]
}