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GET /api/patches/806291/?format=api
{ "id": 806291, "url": "http://patchwork.ozlabs.org/api/patches/806291/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503855651-17409-3-git-send-email-okaya@codeaurora.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503855651-17409-3-git-send-email-okaya@codeaurora.org>", "list_archive_url": null, "date": "2017-08-27T17:40:50", "name": "[V13,3/4] PCI: Handle CRS ('device not ready') returned by device after FLR", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "578a484d7ebc42f7082d5561b982caca6d88da5d", "submitter": { "id": 67496, "url": "http://patchwork.ozlabs.org/api/people/67496/?format=api", "name": "Sinan Kaya", "email": "okaya@codeaurora.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503855651-17409-3-git-send-email-okaya@codeaurora.org/mbox/", "series": [ { "id": 36, "url": "http://patchwork.ozlabs.org/api/series/36/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=36", "date": "2017-08-27T17:40:51", "name": "[V13,1/4] PCI: Don't ignore valid response before CRS timeout", "version": 13, "mbox": "http://patchwork.ozlabs.org/series/36/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/806291/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/806291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ET1UDThD\"; \n\tdkim=pass (1024-bit key) header.d=codeaurora.org\n\theader.i=@codeaurora.org header.b=\"m2v9fpKs\"; \n\tdkim-atps=neutral", "pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org", "pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=okaya@codeaurora.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgMdm6vJhz9sNn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 28 Aug 2017 03:41:32 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751336AbdH0RlH (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tSun, 27 Aug 2017 13:41:07 -0400", "from smtp.codeaurora.org ([198.145.29.96]:42690 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751146AbdH0RlE (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Sun, 27 Aug 2017 13:41:04 -0400", "by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 181D560731; Sun, 27 Aug 2017 17:41:04 +0000 (UTC)", "from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com\n\t[129.46.232.65])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: okaya@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 7AF7F6072D;\n\tSun, 27 Aug 2017 17:41:02 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503855664;\n\tbh=hrKWq7cNzJjcUOpB6WWD58XupwSseUI5Er5ARz5p6LE=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=ET1UDThDKzMWDm24cCDWrchfuo2S+I41ulG0J/m22O1pyUhfnmeZEb4cZ7uLi/yG6\n\tR5r1k7z5dS5OPi1jmMO2s3ahARaXKUO5qpisrgHlNFjenMPvvYyFzFyUoJ/RV2ta4s\n\teIUgSL2TqNowuDJPJGZef0VD6lirJNDWZYY7CSFs=", "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503855663;\n\tbh=hrKWq7cNzJjcUOpB6WWD58XupwSseUI5Er5ARz5p6LE=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=m2v9fpKsB2b6L34t2TEg7dBDhCNwyjMgSojRuSBHDBITk7usMlfpnpCg/xHMKgAW6\n\tGLEbzhtjGibZAq5tK5RehGZXVljIofX1T47J96CN5ak8VUPQv8I8dZhR6Q/F1dnJpz\n\tvVXga1TiJAVYCq6oaBIWVK2WmMZA7uDkBhNpBLpY=" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0", "DMARC-Filter": "OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7AF7F6072D", "From": "Sinan Kaya <okaya@codeaurora.org>", "To": "linux-pci@vger.kernel.org, timur@codeaurora.org,\n\talex.williamson@redhat.com", "Cc": "linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tSinan Kaya <okaya@codeaurora.org>, Bjorn Helgaas <bhelgaas@google.com>,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH V13 3/4] PCI: Handle CRS ('device not ready') returned by\n\tdevice after FLR", "Date": "Sun, 27 Aug 2017 13:40:50 -0400", "Message-Id": "<1503855651-17409-3-git-send-email-okaya@codeaurora.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1503855651-17409-1-git-send-email-okaya@codeaurora.org>", "References": "<1503855651-17409-1-git-send-email-okaya@codeaurora.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Sporadic reset issues have been observed with Intel 750 NVMe drive while\nassigning the physical function to the guest machine. The sequence of\nevents observed is as follows:\n\n- perform a Function Level Reset (FLR)\n- sleep up to 1000ms total\n- read ~0 from PCI_COMMAND\n- warn that the device didn't return from FLR\n- touch the device before it's ready\n- device drops config writes when we restore register settings\n- incomplete register restore leaves device in inconsistent state\n- device probe fails because device is in inconsistent state\n\nAfter reset, an endpoint may respond to config requests with Configuration\nRequest Retry Status (CRS) to indicate that it is not ready to accept new\nrequests. See PCIe r3.1, sec 2.3.1 and 6.6.2.\n\nIncrease the timeout value from 1 second to 60 seconds to cover the period\nwhere device responds with CRS and also report polling progress.\n\nSigned-off-by: Sinan Kaya <okaya@codeaurora.org>\n---\n drivers/pci/pci.c | 52 +++++++++++++++++++++++++++++++++++++---------------\n 1 file changed, 37 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex af0cc34..abab64b 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -3811,27 +3811,49 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)\n }\n EXPORT_SYMBOL(pci_wait_for_pending_transaction);\n \n-/*\n- * We should only need to wait 100ms after FLR, but some devices take longer.\n- * Wait for up to 1000ms for config space to return something other than -1.\n- * Intel IGD requires this when an LCD panel is attached. We read the 2nd\n- * dword because VFs don't implement the 1st dword.\n- */\n static void pci_flr_wait(struct pci_dev *dev)\n {\n-\tint i = 0;\n+\tint delay = 1, timeout = 60000;\n \tu32 id;\n \n-\tdo {\n-\t\tmsleep(100);\n+\t/*\n+\t * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within\n+\t * 100ms, but may silently discard requests while the FLR is in\n+\t * progress. Wait 100ms before trying to access the device.\n+\t */\n+\tmsleep(100);\n+\n+\t/*\n+\t * After 100ms, the device should not silently discard config\n+\t * requests, but it may still indicate that it needs more time by\n+\t * responding to them with CRS completions. The Root Port will\n+\t * generally synthesize ~0 data to complete the read (except when\n+\t * CRS SV is enabled and the read was for the Vendor ID; in that\n+\t * case it synthesizes 0x0001 data).\n+\t *\n+\t * Wait for the device to return a non-CRS completion. Read the\n+\t * Command register instead of Vendor ID so we don't have to\n+\t * contend with the CRS SV value.\n+\t */\n+\tpci_read_config_dword(dev, PCI_COMMAND, &id);\n+\twhile (id == ~0) {\n+\t\tif (delay > timeout) {\n+\t\t\tdev_warn(&dev->dev, \"not ready %dms after FLR; giving up\\n\",\n+\t\t\t\t delay - 1);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tif (delay > 1000)\n+\t\t\tdev_info(&dev->dev, \"not ready %dms after FLR; waiting\\n\",\n+\t\t\t\t delay - 1);\n+\n+\t\tmsleep(delay);\n+\t\tdelay *= 2;\n \t\tpci_read_config_dword(dev, PCI_COMMAND, &id);\n-\t} while (i++ < 10 && id == ~0);\n+\t}\n \n-\tif (id == ~0)\n-\t\tdev_warn(&dev->dev, \"Failed to return from FLR\\n\");\n-\telse if (i > 1)\n-\t\tdev_info(&dev->dev, \"Required additional %dms to return from FLR\\n\",\n-\t\t\t (i - 1) * 100);\n+\tif (delay > 1000)\n+\t\tdev_info(&dev->dev, \"ready %dms after FLR\\n\", delay - 1);\n }\n \n /**\n", "prefixes": [ "V13", "3/4" ] }