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{
    "id": 804987,
    "url": "http://patchwork.ozlabs.org/api/patches/804987/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20170823134612.26117-1-jarkko.nikula@linux.intel.com/",
    "project": {
        "id": 35,
        "url": "http://patchwork.ozlabs.org/api/projects/35/?format=api",
        "name": "Linux I2C development",
        "link_name": "linux-i2c",
        "list_id": "linux-i2c.vger.kernel.org",
        "list_email": "linux-i2c@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170823134612.26117-1-jarkko.nikula@linux.intel.com>",
    "list_archive_url": null,
    "date": "2017-08-23T13:46:12",
    "name": "i2c: designware: Don't set SCL timings and speed mode when in slave mode",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "e0a2de054de7cb9956dc94e5591dbc3606fcee81",
    "submitter": {
        "id": 43309,
        "url": "http://patchwork.ozlabs.org/api/people/43309/?format=api",
        "name": "Jarkko Nikula",
        "email": "jarkko.nikula@linux.intel.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20170823134612.26117-1-jarkko.nikula@linux.intel.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/804987/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/804987/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-i2c-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-i2c-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcpcd1NSmz9rvt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 23:46:41 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754051AbdHWNqh (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 23 Aug 2017 09:46:37 -0400",
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        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.41,417,1498546800\"; d=\"scan'208\";a=\"893353238\"",
        "From": "Jarkko Nikula <jarkko.nikula@linux.intel.com>",
        "To": "linux-i2c@vger.kernel.org",
        "Cc": "Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n\tMika Westerberg <mika.westerberg@linux.intel.com>,\n\tWolfram Sang <wsa@the-dreams.de>,\n\tLuis Oliveira <Luis.Oliveira@synopsys.com>,\n\tJarkko Nikula <jarkko.nikula@linux.intel.com>",
        "Subject": "[PATCH] i2c: designware: Don't set SCL timings and speed mode when\n\tin slave mode",
        "Date": "Wed, 23 Aug 2017 16:46:12 +0300",
        "Message-Id": "<20170823134612.26117-1-jarkko.nikula@linux.intel.com>",
        "X-Mailer": "git-send-email 2.14.1",
        "Sender": "linux-i2c-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-i2c.vger.kernel.org>",
        "X-Mailing-List": "linux-i2c@vger.kernel.org"
    },
    "content": "According to data sheet SCL timing parameters and DW_IC_CON SPEED mode\nbits are not used when operating in slave mode.\n\nSigned-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>\n---\nI've done quick testing with i2c-slave-eeprom and i2cdump over together\nhooked busses without issues. Would like to hear tested by or comment\nfrom Luis though. Patch is not urgent so can wait after vacation etc.\n---\n drivers/i2c/busses/i2c-designware-platdrv.c | 11 -----\n drivers/i2c/busses/i2c-designware-slave.c   | 64 -----------------------------\n 2 files changed, 75 deletions(-)",
    "diff": "diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c\nindex 56a17fdc2270..962c7ab25b93 100644\n--- a/drivers/i2c/busses/i2c-designware-platdrv.c\n+++ b/drivers/i2c/busses/i2c-designware-platdrv.c\n@@ -201,17 +201,6 @@ static void i2c_dw_configure_slave(struct dw_i2c_dev *dev)\n \t\t\t DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED;\n \n \tdev->mode = DW_IC_SLAVE;\n-\n-\tswitch (dev->clk_freq) {\n-\tcase 100000:\n-\t\tdev->slave_cfg |= DW_IC_CON_SPEED_STD;\n-\t\tbreak;\n-\tcase 3400000:\n-\t\tdev->slave_cfg |= DW_IC_CON_SPEED_HIGH;\n-\t\tbreak;\n-\tdefault:\n-\t\tdev->slave_cfg |= DW_IC_CON_SPEED_FAST;\n-\t}\n }\n \n static int i2c_dw_plat_prepare_clk(struct dw_i2c_dev *i_dev, bool prepare)\ndiff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c\nindex ea9578ab19a1..d42558d1b002 100644\n--- a/drivers/i2c/busses/i2c-designware-slave.c\n+++ b/drivers/i2c/busses/i2c-designware-slave.c\n@@ -51,9 +51,7 @@ static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)\n  */\n static int i2c_dw_init_slave(struct dw_i2c_dev *dev)\n {\n-\tu32 sda_falling_time, scl_falling_time;\n \tu32 reg, comp_param1;\n-\tu32 hcnt, lcnt;\n \tint ret;\n \n \tret = i2c_dw_acquire_lock(dev);\n@@ -79,68 +77,6 @@ static int i2c_dw_init_slave(struct dw_i2c_dev *dev)\n \t/* Disable the adapter. */\n \t__i2c_dw_enable_and_wait(dev, false);\n \n-\t/* Set standard and fast speed deviders for high/low periods. */\n-\tsda_falling_time = dev->sda_falling_time ?: 300; /* ns */\n-\tscl_falling_time = dev->scl_falling_time ?: 300; /* ns */\n-\n-\t/* Set SCL timing parameters for standard-mode. */\n-\tif (dev->ss_hcnt && dev->ss_lcnt) {\n-\t\thcnt = dev->ss_hcnt;\n-\t\tlcnt = dev->ss_lcnt;\n-\t} else {\n-\t\thcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),\n-\t\t\t\t       4000,\t/* tHD;STA = tHIGH = 4.0 us */\n-\t\t\t\t       sda_falling_time,\n-\t\t\t\t       0,\t/* 0: DW default, 1: Ideal */\n-\t\t\t\t       0);\t/* No offset */\n-\t\tlcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),\n-\t\t\t\t       4700,\t/* tLOW = 4.7 us */\n-\t\t\t\t       scl_falling_time,\n-\t\t\t\t       0);\t/* No offset */\n-\t}\n-\tdw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);\n-\tdw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);\n-\tdev_dbg(dev->dev, \"Standard-mode HCNT:LCNT = %d:%d\\n\", hcnt, lcnt);\n-\n-\t/* Set SCL timing parameters for fast-mode or fast-mode plus. */\n-\tif ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {\n-\t\thcnt = dev->fp_hcnt;\n-\t\tlcnt = dev->fp_lcnt;\n-\t} else if (dev->fs_hcnt && dev->fs_lcnt) {\n-\t\thcnt = dev->fs_hcnt;\n-\t\tlcnt = dev->fs_lcnt;\n-\t} else {\n-\t\thcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),\n-\t\t\t\t       600,\t/* tHD;STA = tHIGH = 0.6 us */\n-\t\t\t\t       sda_falling_time,\n-\t\t\t\t       0,\t/* 0: DW default, 1: Ideal */\n-\t\t\t\t       0);\t/* No offset */\n-\t\tlcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),\n-\t\t\t\t       1300,\t/* tLOW = 1.3 us */\n-\t\t\t\t       scl_falling_time,\n-\t\t\t\t       0);\t/* No offset */\n-\t}\n-\tdw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);\n-\tdw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);\n-\tdev_dbg(dev->dev, \"Fast-mode HCNT:LCNT = %d:%d\\n\", hcnt, lcnt);\n-\n-\tif ((dev->slave_cfg & DW_IC_CON_SPEED_MASK) ==\n-\t\tDW_IC_CON_SPEED_HIGH) {\n-\t\tif ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)\n-\t\t\t!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {\n-\t\t\tdev_err(dev->dev, \"High Speed not supported!\\n\");\n-\t\t\tdev->slave_cfg &= ~DW_IC_CON_SPEED_MASK;\n-\t\t\tdev->slave_cfg |= DW_IC_CON_SPEED_FAST;\n-\t\t} else if (dev->hs_hcnt && dev->hs_lcnt) {\n-\t\t\thcnt = dev->hs_hcnt;\n-\t\t\tlcnt = dev->hs_lcnt;\n-\t\t\tdw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);\n-\t\t\tdw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);\n-\t\t\tdev_dbg(dev->dev, \"HighSpeed-mode HCNT:LCNT = %d:%d\\n\",\n-\t\t\t\thcnt, lcnt);\n-\t\t}\n-\t}\n-\n \t/* Configure SDA Hold Time if required. */\n \treg = dw_readl(dev, DW_IC_COMP_VERSION);\n \tif (reg >= DW_IC_SDA_HOLD_MIN_VERS) {\n",
    "prefixes": []
}