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GET /api/patches/804967/?format=api
{ "id": 804967, "url": "http://patchwork.ozlabs.org/api/patches/804967/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170823125744.424675523@cogentembedded.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170823125744.424675523@cogentembedded.com>", "list_archive_url": null, "date": "2017-08-23T12:52:29", "name": "[2/2] clk: renesas: cpg-mssr: add R8A7797 support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9573beaca5f65dd2daf0e41a8a36392168b39565", "submitter": { "id": 22564, "url": "http://patchwork.ozlabs.org/api/people/22564/?format=api", "name": "Sergei Shtylyov", "email": "sergei.shtylyov@cogentembedded.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170823125744.424675523@cogentembedded.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804967/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804967/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=cogentembedded-com.20150623.gappssmtp.com\n\theader.i=@cogentembedded-com.20150623.gappssmtp.com\n\theader.b=\"M7VE3vUm\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcnXL2JKCz9s9Y\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 22:57:54 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754043AbdHWM5w (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 23 Aug 2017 08:57:52 -0400", "from mail-lf0-f48.google.com ([209.85.215.48]:35851 \"EHLO\n\tmail-lf0-f48.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754041AbdHWM5t (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 23 Aug 2017 08:57:49 -0400", "by mail-lf0-f48.google.com with SMTP id l137so54551lfg.3\n\tfor <devicetree@vger.kernel.org>;\n\tWed, 23 Aug 2017 05:57:48 -0700 (PDT)", "from wasted.cogentembedded.com ([31.173.84.44])\n\tby smtp.gmail.com with ESMTPSA id\n\to7sm238790lff.86.2017.08.23.05.57.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 23 Aug 2017 05:57:47 -0700 (PDT)", "by wasted.cogentembedded.com (sSMTP sendmail emulation);\n\tWed, 23 Aug 2017 15:57:44 +0300" ], "DKIM-Signature": "v=1; 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\n\tWed, 23 Aug 2017 05:57:48 -0700 (PDT)", "From": "Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>", "X-Google-Original-From": "\"Sergei Shtylyov\"\n\t<headless@wasted.cogentembedded.com>", "Message-Id": "<20170823125744.424675523@cogentembedded.com>", "User-Agent": "quilt/0.64", "Date": "Wed, 23 Aug 2017 15:52:29 +0300", "To": "Michael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh+dt@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>,\n\tGeert Uytterhoeven <geert+renesas@glider.be>,\n\tlinux-clk@vger.kernel.org, devicetree@vger.kernel.org", "Cc": [ "linux-renesas-soc@vger.kernel.org,\n\tVladimir Barinov <vladimir.barinov@cogentembedded.com>,\n\tSergei Shtylyov <sergei.shtylyov@cogentembedded.com>", "Simon Horman <horms+renesas@verge.net.au>" ], "Subject": "[PATCH 2/2] clk: renesas: cpg-mssr: add R8A7797 support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=ISO-8859-15", "Content-Disposition": "inline;\n\tfilename=clk-renesas-cpg-mssr-add-R8A7797-support.patch", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add R-Car V3M (R8A7797) Clock Pulse Generator / Module Standby and\nSoftware Reset support, using the CPG/MSSR driver core and the common\nR-Car Gen3 code.\n\nBased on the original (and large) patch by Daisuke Matsushita\n<daisuke.matsushita.ns@hitachi.com>.\n\nSigned-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>\nSigned-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\n\n---\n Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 5 \n drivers/clk/renesas/Kconfig | 5 \n drivers/clk/renesas/Makefile | 1 \n drivers/clk/renesas/r8a7797-cpg-mssr.c | 207 +++++++++++\n drivers/clk/renesas/renesas-cpg-mssr.c | 6 \n drivers/clk/renesas/renesas-cpg-mssr.h | 1 \n 6 files changed, 223 insertions(+), 2 deletions(-)\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html", "diff": "Index: linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n===================================================================\n--- linux.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n+++ linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n@@ -22,6 +22,7 @@ Required Properties:\n - \"renesas,r8a7794-cpg-mssr\" for the r8a7794 SoC (R-Car E2)\n - \"renesas,r8a7795-cpg-mssr\" for the r8a7795 SoC (R-Car H3)\n - \"renesas,r8a7796-cpg-mssr\" for the r8a7796 SoC (R-Car M3-W)\n+ - \"renesas,r8a7797-cpg-mssr\" for the r8a7797 SoC (R-Car V3M)\n \n - reg: Base address and length of the memory resource used by the CPG/MSSR\n block\n@@ -30,8 +31,8 @@ Required Properties:\n clock-names\n - clock-names: List of external parent clock names. Valid names are:\n - \"extal\" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,\n-\t\t r8a7795, r8a7796)\n- - \"extalr\" (r8a7795, r8a7796)\n+\t\t r8a7795, r8a7796, r8a7797)\n+ - \"extalr\" (r8a7795, r8a7796, r8a7797)\n - \"usb_extal\" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)\n \n - #clock-cells: Must be 2\nIndex: linux/drivers/clk/renesas/Kconfig\n===================================================================\n--- linux.orig/drivers/clk/renesas/Kconfig\n+++ linux/drivers/clk/renesas/Kconfig\n@@ -15,6 +15,7 @@ config CLK_RENESAS\n \tselect CLK_R8A7794 if ARCH_R8A7794\n \tselect CLK_R8A7795 if ARCH_R8A7795\n \tselect CLK_R8A7796 if ARCH_R8A7796\n+\tselect CLK_R8A7797 if ARCH_R8A7797\n \tselect CLK_SH73A0 if ARCH_SH73A0\n \n if CLK_RENESAS\n@@ -94,6 +95,10 @@ config CLK_R8A7796\n \tbool\n \tselect CLK_RCAR_GEN3_CPG\n \n+config CLK_R8A7797\n+\tbool\n+\tselect CLK_RCAR_GEN3_CPG\n+\n config CLK_SH73A0\n \tbool\n \tselect CLK_RENESAS_CPG_MSTP\nIndex: linux/drivers/clk/renesas/Makefile\n===================================================================\n--- linux.orig/drivers/clk/renesas/Makefile\n+++ linux/drivers/clk/renesas/Makefile\n@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_R8A7792)\t\t+= r8a7792-cp\n obj-$(CONFIG_CLK_R8A7794)\t\t+= r8a7794-cpg-mssr.o\n obj-$(CONFIG_CLK_R8A7795)\t\t+= r8a7795-cpg-mssr.o\n obj-$(CONFIG_CLK_R8A7796)\t\t+= r8a7796-cpg-mssr.o\n+obj-$(CONFIG_CLK_R8A7797)\t\t+= r8a7797-cpg-mssr.o\n obj-$(CONFIG_CLK_SH73A0)\t\t+= clk-sh73a0.o\n \n # Family\nIndex: linux/drivers/clk/renesas/r8a7797-cpg-mssr.c\n===================================================================\n--- /dev/null\n+++ linux/drivers/clk/renesas/r8a7797-cpg-mssr.c\n@@ -0,0 +1,207 @@\n+/*\n+ * r8a7797 Clock Pulse Generator / Module Standby and Software Reset\n+ *\n+ * Copyright (C) 2017 Cogent Embedded Inc.\n+ *\n+ * Based on r8a7795-cpg-mssr.c\n+ *\n+ * Copyright (C) 2015 Glider bvba\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; version 2 of the License.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/soc/renesas/rcar-rst.h>\n+\n+#include <dt-bindings/clock/r8a7797-cpg-mssr.h>\n+\n+#include \"renesas-cpg-mssr.h\"\n+#include \"rcar-gen3-cpg.h\"\n+\n+enum clk_ids {\n+\t/* Core Clock Outputs exported to DT */\n+\tLAST_DT_CORE_CLK = R8A7797_CLK_OSC,\n+\n+\t/* External Input Clocks */\n+\tCLK_EXTAL,\n+\tCLK_EXTALR,\n+\n+\t/* Internal Core Clocks */\n+\tCLK_MAIN,\n+\tCLK_PLL0,\n+\tCLK_PLL1,\n+\tCLK_PLL3,\n+\tCLK_PLL1_DIV2,\n+\tCLK_PLL1_DIV4,\n+\tCLK_S1,\n+\tCLK_S2,\n+\n+\t/* Module Clocks */\n+\tMOD_CLK_BASE\n+};\n+\n+static const struct cpg_core_clk r8a7797_core_clks[] __initconst = {\n+\t/* External Clock Inputs */\n+\tDEF_INPUT(\"extal\",\tCLK_EXTAL),\n+\tDEF_INPUT(\"extalr\",\tCLK_EXTALR),\n+\n+\t/* Internal Core Clocks */\n+\tDEF_BASE(\".main\",\tCLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),\n+\tDEF_BASE(\".pll0\",\tCLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),\n+\tDEF_BASE(\".pll1\",\tCLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),\n+\tDEF_BASE(\".pll3\",\tCLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),\n+\n+\tDEF_FIXED(\".pll1_div2\",\tCLK_PLL1_DIV2,\tCLK_PLL1,\t2, 1),\n+\tDEF_FIXED(\".pll1_div4\",\tCLK_PLL1_DIV4,\tCLK_PLL1_DIV2,\t2, 1),\n+\tDEF_FIXED(\".s1\",\tCLK_S1,\t\tCLK_PLL1_DIV2,\t4, 1),\n+\tDEF_FIXED(\".s2\",\tCLK_S2,\t\tCLK_PLL1_DIV2,\t6, 1),\n+\n+\t/* Core Clock Outputs */\n+\tDEF_FIXED(\"ztr\",\tR8A7797_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),\n+\tDEF_FIXED(\"ztrd2\",\tR8A7797_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),\n+\tDEF_FIXED(\"zt\",\t\tR8A7797_CLK_ZT, CLK_PLL1_DIV2, 4, 1),\n+\tDEF_FIXED(\"zx\",\t\tR8A7797_CLK_ZX, CLK_PLL1_DIV2, 3, 1),\n+\tDEF_FIXED(\"s1d1\",\tR8A7797_CLK_S1D1, CLK_S1,\t 1, 1),\n+\tDEF_FIXED(\"s1d2\",\tR8A7797_CLK_S1D2, CLK_S1,\t 2, 1),\n+\tDEF_FIXED(\"s1d4\",\tR8A7797_CLK_S1D4, CLK_S1,\t 4, 1),\n+\tDEF_FIXED(\"s2d1\",\tR8A7797_CLK_S2D1, CLK_S2,\t 1, 1),\n+\tDEF_FIXED(\"s2d2\",\tR8A7797_CLK_S2D2, CLK_S2,\t 2, 1),\n+\tDEF_FIXED(\"s2d4\",\tR8A7797_CLK_S2D4, CLK_S2,\t 4, 1),\n+\n+\tDEF_FIXED(\"cl\",\t\tR8A7797_CLK_CL, CLK_PLL1_DIV2, 48, 1),\n+\tDEF_FIXED(\"cp\",\t\tR8A7797_CLK_CP, CLK_EXTAL,\t 2, 1),\n+\n+\tDEF_DIV6P1(\"canfd\",\tR8A7797_CLK_CANFD, CLK_PLL1_DIV4, 0x244),\n+\tDEF_DIV6P1(\"mso\",\tR8A7797_CLK_MSO, CLK_PLL1_DIV4, 0x014),\n+\tDEF_DIV6P1(\"csi0\",\tR8A7797_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),\n+\n+\tDEF_FIXED(\"osc\",\tR8A7797_CLK_OSC, CLK_PLL1_DIV2, (12*1024), 1),\n+\tDEF_FIXED(\"r\",\t\tR8A7797_CLK_R,\t CLK_EXTALR,\t 1, 1),\n+};\n+\n+static const struct mssr_mod_clk r8a7797_mod_clks[] __initconst = {\n+\tDEF_MOD(\"ivcp1e\",\t\t 127,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"scif4\",\t\t 203,\tR8A7797_CLK_S2D4),\n+\tDEF_MOD(\"scif3\",\t\t 204,\tR8A7797_CLK_S2D4),\n+\tDEF_MOD(\"scif1\",\t\t 206,\tR8A7797_CLK_S2D4),\n+\tDEF_MOD(\"scif0\",\t\t 207,\tR8A7797_CLK_S2D4),\n+\tDEF_MOD(\"msiof3\",\t\t 208,\tR8A7797_CLK_MSO),\n+\tDEF_MOD(\"msiof2\",\t\t 209,\tR8A7797_CLK_MSO),\n+\tDEF_MOD(\"msiof1\",\t\t 210,\tR8A7797_CLK_MSO),\n+\tDEF_MOD(\"msiof0\",\t\t 211,\tR8A7797_CLK_MSO),\n+\tDEF_MOD(\"mfis\",\t\t\t 213,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"sys-dmac2\",\t\t 217,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"sys-dmac1\",\t\t 218,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"rwdt\",\t\t\t 402,\tR8A7797_CLK_R),\n+\tDEF_MOD(\"intc-ex\",\t\t 407,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"intc-ap\",\t\t 408,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"hscif3\",\t\t 517,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"hscif2\",\t\t 518,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"hscif1\",\t\t 519,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"hscif0\",\t\t 520,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"thermal\",\t\t 522,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"pwm\",\t\t\t 523,\tR8A7797_CLK_S2D4),\n+\tDEF_MOD(\"fcpvd0\",\t\t 603,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"vspd0\",\t\t 623,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"csi40\",\t\t 716,\tR8A7797_CLK_CSI0),\n+\tDEF_MOD(\"du0\",\t\t\t 724,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"vin3\",\t\t\t 808,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"vin2\",\t\t\t 809,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"vin1\",\t\t\t 810,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"vin0\",\t\t\t 811,\tR8A7797_CLK_S2D1),\n+\tDEF_MOD(\"etheravb\",\t\t 812,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"gpio5\",\t\t 907,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"gpio4\",\t\t 908,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"gpio3\",\t\t 909,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"gpio2\",\t\t 910,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"gpio1\",\t\t 911,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"gpio0\",\t\t 912,\tR8A7797_CLK_CP),\n+\tDEF_MOD(\"can-fd\",\t\t 914,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"i2c4\",\t\t\t 927,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"i2c3\",\t\t\t 928,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"i2c2\",\t\t\t 929,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"i2c1\",\t\t\t 930,\tR8A7797_CLK_S2D2),\n+\tDEF_MOD(\"i2c0\",\t\t\t 931,\tR8A7797_CLK_S2D2),\n+};\n+\n+static const unsigned int r8a7797_crit_mod_clks[] __initconst = {\n+\tMOD_CLK_ID(408),\t/* INTC-AP (GIC) */\n+};\n+\n+\n+/*\n+ * CPG Clock Data\n+ */\n+\n+/*\n+ * MD\t\tEXTAL\t\tPLL0\tPLL1\tPLL3\n+ * 14 13 19\t(MHz)\n+ *-------------------------------------------------\n+ * 0 0 0\t16.66 x 1\tx192\tx192\tx96\n+ * 0 0 1\t16.66 x 1\tx192\tx192\tx80\n+ * 0 1 0\t20 x 1\tx160\tx160\tx80\n+ * 0 1 1\t20 x 1\tx160\tx160\tx66\n+ * 1 0 0\t27 / 2\tx236\tx236\tx118\n+ * 1 0 1\t27 / 2\tx236\tx236\tx98\n+ * 1 1 0\t33.33 / 2\tx192\tx192\tx96\n+ * 1 1 1\t33.33 / 2\tx192\tx192\tx80\n+ */\n+#define CPG_PLL_CONFIG_INDEX(md)\t((((md) & BIT(14)) >> 12) | \\\n+\t\t\t\t\t (((md) & BIT(13)) >> 12) | \\\n+\t\t\t\t\t (((md) & BIT(19)) >> 19))\n+\n+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {\n+\t/* EXTAL div\tPLL1 mult\tPLL3 mult */\n+\t{ 1,\t\t192,\t\t96,\t},\n+\t{ 1,\t\t192,\t\t80,\t},\n+\t{ 1,\t\t160,\t\t80,\t},\n+\t{ 1,\t\t160,\t\t66,\t},\n+\t{ 2,\t\t236,\t\t118,\t},\n+\t{ 2,\t\t236,\t\t98,\t},\n+\t{ 2,\t\t192,\t\t96,\t},\n+\t{ 2,\t\t192,\t\t80,\t},\n+};\n+\n+static int __init r8a7797_cpg_mssr_init(struct device *dev)\n+{\n+\tconst struct rcar_gen3_cpg_pll_config *cpg_pll_config;\n+\tu32 cpg_mode;\n+\tint error;\n+\n+\terror = rcar_rst_read_mode_pins(&cpg_mode);\n+\tif (error)\n+\t\treturn error;\n+\n+\tcpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];\n+\tif (!cpg_pll_config->extal_div) {\n+\t\tdev_err(dev, \"Prohibited setting (cpg_mode=0x%x)\\n\", cpg_mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);\n+}\n+\n+const struct cpg_mssr_info r8a7797_cpg_mssr_info __initconst = {\n+\t/* Core Clocks */\n+\t.core_clks = r8a7797_core_clks,\n+\t.num_core_clks = ARRAY_SIZE(r8a7797_core_clks),\n+\t.last_dt_core_clk = LAST_DT_CORE_CLK,\n+\t.num_total_core_clks = MOD_CLK_BASE,\n+\n+\t/* Module Clocks */\n+\t.mod_clks = r8a7797_mod_clks,\n+\t.num_mod_clks = ARRAY_SIZE(r8a7797_mod_clks),\n+\t.num_hw_mod_clks = 12 * 32,\n+\n+\t/* Critical Module Clocks */\n+\t.crit_mod_clks = r8a7797_crit_mod_clks,\n+\t.num_crit_mod_clks = ARRAY_SIZE(r8a7797_crit_mod_clks),\n+\n+\t/* Callbacks */\n+\t.init = r8a7797_cpg_mssr_init,\n+\t.cpg_clk_register = rcar_gen3_cpg_clk_register,\n+};\nIndex: linux/drivers/clk/renesas/renesas-cpg-mssr.c\n===================================================================\n--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.c\n+++ linux/drivers/clk/renesas/renesas-cpg-mssr.c\n@@ -680,6 +680,12 @@ static const struct of_device_id cpg_mss\n \t\t.data = &r8a7796_cpg_mssr_info,\n \t},\n #endif\n+#ifdef CONFIG_CLK_R8A7797\n+\t{\n+\t\t.compatible = \"renesas,r8a7797-cpg-mssr\",\n+\t\t.data = &r8a7797_cpg_mssr_info,\n+\t},\n+#endif\n \t{ /* sentinel */ }\n };\n \nIndex: linux/drivers/clk/renesas/renesas-cpg-mssr.h\n===================================================================\n--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.h\n+++ linux/drivers/clk/renesas/renesas-cpg-mssr.h\n@@ -138,6 +138,7 @@ extern const struct cpg_mssr_info r8a779\n extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;\n extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;\n extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;\n+extern const struct cpg_mssr_info r8a7797_cpg_mssr_info;\n \n \n /*\n", "prefixes": [ "2/2" ] }