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GET /api/patches/804916/?format=api
{ "id": 804916, "url": "http://patchwork.ozlabs.org/api/patches/804916/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170823100342.26148-1-maxime.ripard@free-electrons.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170823100342.26148-1-maxime.ripard@free-electrons.com>", "list_archive_url": null, "date": "2017-08-23T10:03:41", "name": "[U-Boot,v2,1/2] mmc: sunxi: Support new mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "57e4ccdf94bcde741afa4da0fdb03c5accdb455c", "submitter": { "id": 12916, "url": "http://patchwork.ozlabs.org/api/people/12916/?format=api", "name": "Maxime Ripard", "email": "maxime.ripard@free-electrons.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170823100342.26148-1-maxime.ripard@free-electrons.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804916/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804916/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcjgg1H6pz9s8V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 20:03:59 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid DA46BC21E7E; Wed, 23 Aug 2017 10:03:51 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 936C4C21DA4;\n\tWed, 23 Aug 2017 10:03:48 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 94AF6C21DA4; Wed, 23 Aug 2017 10:03:46 +0000 (UTC)", "from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54])\n\tby lists.denx.de (Postfix) with ESMTP id 2C5F1C21D78\n\tfor <u-boot@lists.denx.de>; Wed, 23 Aug 2017 10:03:46 +0000 (UTC)", "by mail.free-electrons.com (Postfix, from userid 110)\n\tid 103FD209F5; Wed, 23 Aug 2017 12:03:45 +0200 (CEST)", "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id BFC30209CE;\n\tWed, 23 Aug 2017 12:03:44 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Maxime Ripard <maxime.ripard@free-electrons.com>", "To": "Jagan Teki <jagan@openedev.com>, Jaehoon Chung <jh80.chung@samsung.com>", "Date": "Wed, 23 Aug 2017 12:03:41 +0200", "Message-Id": "<20170823100342.26148-1-maxime.ripard@free-electrons.com>", "X-Mailer": "git-send-email 2.13.5", "Cc": "u-boot@lists.denx.de, Maxime Ripard <maxime.ripard@free-electrons.com>", "Subject": "[U-Boot] [PATCH v2 1/2] mmc: sunxi: Support new mode", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Almost all of the newer Allwinner SoCs have a new operating mode for the\neMMC clocks that needs to be enabled in both the clock and the MMC\ncontroller.\n\nDetails about that mode are sparse, and the name itself (new mode vs old\nmode) doesn't give much details, but it seems that the it changes the\nsampling of the MMC clock. One side effect is also that it divides the\nparent clock rate by 2.\n\nAdd support for it through a Kconfig option.\n\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n\n---\nChanges from v1:\n - Switched to IS_ENABLED when possible\n - Added some defines\n - Tried to put more details in the commit log\n - Added a depends on in the Kconfig option\n---\n arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 1 +\n arch/arm/include/asm/arch-sunxi/mmc.h | 11 ++++++---\n drivers/mmc/Kconfig | 4 ++++\n drivers/mmc/sunxi_mmc.c | 27 +++++++++++++++++++---\n 4 files changed, 37 insertions(+), 6 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h\nindex 5e1346e5242a..5dfcbf3b017b 100644\n--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h\n+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h\n@@ -220,6 +220,7 @@ struct sunxi_ccm_reg {\n #define CCM_MMC_CTRL_SCLK_DLY(x)\t((x) << 20)\n #define CCM_MMC_CTRL_OSCM24\t\t(0x0 << 24)\n #define CCM_MMC_CTRL_PLL6\t\t(0x1 << 24)\n+#define CCM_MMC_CTRL_MODE_SEL_NEW\t(0x1 << 30)\n #define CCM_MMC_CTRL_ENABLE\t\t(0x1 << 31)\n \n #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)\ndiff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h\nindex cb52e648731c..69f737f3bffc 100644\n--- a/arch/arm/include/asm/arch-sunxi/mmc.h\n+++ b/arch/arm/include/asm/arch-sunxi/mmc.h\n@@ -35,16 +35,19 @@ struct sunxi_mmc {\n \tu32 cbcr;\t\t/* 0x48 CIU byte count */\n \tu32 bbcr;\t\t/* 0x4c BIU byte count */\n \tu32 dbgc;\t\t/* 0x50 debug enable */\n-\tu32 res0[11];\n+\tu32 res0;\t\t/* 0x54 reserved */\n+\tu32 a12a;\t\t/* 0x58 Auto command 12 argument */\n+\tu32 ntsr;\t\t/* 0x5c\tNew timing set register */\n+\tu32 res1[8];\n \tu32 dmac;\t\t/* 0x80 internal DMA control */\n \tu32 dlba;\t\t/* 0x84 internal DMA descr list base address */\n \tu32 idst;\t\t/* 0x88 internal DMA status */\n \tu32 idie;\t\t/* 0x8c internal DMA interrupt enable */\n \tu32 chda;\t\t/* 0x90 */\n \tu32 cbda;\t\t/* 0x94 */\n-\tu32 res1[26];\n+\tu32 res2[26];\n #ifdef CONFIG_SUNXI_GEN_SUN6I\n-\tu32 res2[64];\n+\tu32 res3[64];\n #endif\n \tu32 fifo;\t\t/* 0x100 / 0x200 FIFO access address */\n };\n@@ -116,6 +119,8 @@ struct sunxi_mmc {\n #define SUNXI_MMC_STATUS_CARD_DATA_BUSY\t\t(0x1 << 9)\n #define SUNXI_MMC_STATUS_DATA_FSM_BUSY\t\t(0x1 << 10)\n \n+#define SUNXI_MMC_NTSR_MODE_SEL_NEW\t\t(0x1 << 31)\n+\n #define SUNXI_MMC_IDMAC_RESET\t\t(0x1 << 0)\n #define SUNXI_MMC_IDMAC_FIXBURST\t(0x1 << 1)\n #define SUNXI_MMC_IDMAC_ENABLE\t\t(0x1 << 7)\ndiff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig\nindex 51a87cdd77dc..9075b346036b 100644\n--- a/drivers/mmc/Kconfig\n+++ b/drivers/mmc/Kconfig\n@@ -389,6 +389,10 @@ config MMC_SUNXI\n \t This selects support for the SD/MMC Host Controller on\n \t Allwinner sunxi SoCs.\n \n+config MMC_SUNXI_HAS_NEW_MODE\n+\tbool\n+\tdepends on MMC_SUNXI\n+\n config GENERIC_ATMEL_MCI\n \tbool \"Atmel Multimedia Card Interface support\"\n \tdepends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91\ndiff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c\nindex 588574fab6a9..bc638ae2e64a 100644\n--- a/drivers/mmc/sunxi_mmc.c\n+++ b/drivers/mmc/sunxi_mmc.c\n@@ -96,6 +96,18 @@ static int mmc_resource_init(int sdc_no)\n static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n {\n \tunsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;\n+\tbool new_mode = false;\n+\tu32 val = 0;\n+\n+\tif (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))\n+\t\tnew_mode = true;\n+\n+\t/*\n+\t * The MMC clock has an extra /2 post-divider when operating in the new\n+\t * mode.\n+\t */\n+\tif (new_mode)\n+\t\thz = hz * 2;\n \n \tif (hz <= 24000000) {\n \t\tpll = CCM_MMC_CTRL_OSCM24;\n@@ -152,9 +164,18 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n #endif\n \t}\n \n-\twritel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |\n-\t CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |\n-\t CCM_MMC_CTRL_M(div), priv->mclkreg);\n+\tif (new_mode) {\n+#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE\n+\t\tval = CCM_MMC_CTRL_MODE_SEL_NEW;\n+\t\twritel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr);\n+#endif\n+\t} else {\n+\t\tval = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |\n+\t\t\tCCM_MMC_CTRL_SCLK_DLY(sclk_dly);\n+\t}\n+\n+\twritel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |\n+\t CCM_MMC_CTRL_M(div) | val, priv->mclkreg);\n \n \tdebug(\"mmc %u set mod-clk req %u parent %u n %u m %u rate %u\\n\",\n \t priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);\n", "prefixes": [ "U-Boot", "v2", "1/2" ] }