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GET /api/patches/804738/?format=api
{ "id": 804738, "url": "http://patchwork.ozlabs.org/api/patches/804738/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503464171-6471-4-git-send-email-okaya@codeaurora.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1503464171-6471-4-git-send-email-okaya@codeaurora.org>", "list_archive_url": null, "date": "2017-08-23T04:56:10", "name": "[V12,4/5] PCI: Handle CRS (\"device not ready\") returned by device after FLR", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4bca96c253e54dd3d524cfb4752b9b08c99e4a02", "submitter": { "id": 67496, "url": "http://patchwork.ozlabs.org/api/people/67496/?format=api", "name": "Sinan Kaya", "email": "okaya@codeaurora.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1503464171-6471-4-git-send-email-okaya@codeaurora.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804738/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Bqw/VV8o\"; \n\tdkim=pass (1024-bit key) header.d=codeaurora.org\n\theader.i=@codeaurora.org header.b=\"Bqw/VV8o\"; \n\tdkim-atps=neutral", "pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org", "pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=okaya@codeaurora.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcZsd1cZ8z9s8V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 14:57:09 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753371AbdHWE4x (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 23 Aug 2017 00:56:53 -0400", "from smtp.codeaurora.org ([198.145.29.96]:53348 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753308AbdHWE4V (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Wed, 23 Aug 2017 00:56:21 -0400", "by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid B24F160721; Wed, 23 Aug 2017 04:56:20 +0000 (UTC)", "from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com\n\t[129.46.232.65])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: okaya@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 4C18F60719;\n\tWed, 23 Aug 2017 04:56:19 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503464180;\n\tbh=ZEIXopUjzQejHoXfFG8kVgovPgxiFGeFyHpsLZWMF9E=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Bqw/VV8o/s2U1VwSN5yMQ6pzMpVrox8a0ZX3+8GGk3KeGotEfQ8rhIPmAhlzCBLOu\n\thO/bvnUnh02ikgjl5W3OlPgOFcJvEwwsJupLCOG8z5WWhIDyngV/PHJbYpvY9vyrl6\n\tKkEMSlXXkoFPsdGA3rJVl+jj+hYinAdknKU60ME0=", "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503464180;\n\tbh=ZEIXopUjzQejHoXfFG8kVgovPgxiFGeFyHpsLZWMF9E=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Bqw/VV8o/s2U1VwSN5yMQ6pzMpVrox8a0ZX3+8GGk3KeGotEfQ8rhIPmAhlzCBLOu\n\thO/bvnUnh02ikgjl5W3OlPgOFcJvEwwsJupLCOG8z5WWhIDyngV/PHJbYpvY9vyrl6\n\tKkEMSlXXkoFPsdGA3rJVl+jj+hYinAdknKU60ME0=" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0", "DMARC-Filter": "OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4C18F60719", "From": "Sinan Kaya <okaya@codeaurora.org>", "To": "linux-pci@vger.kernel.org, timur@codeaurora.org,\n\talex.williamson@redhat.com", "Cc": "linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tSinan Kaya <okaya@codeaurora.org>, Bjorn Helgaas <bhelgaas@google.com>,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH V12 4/5] PCI: Handle CRS (\"device not ready\") returned by\n\tdevice after FLR", "Date": "Wed, 23 Aug 2017 00:56:10 -0400", "Message-Id": "<1503464171-6471-4-git-send-email-okaya@codeaurora.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1503464171-6471-1-git-send-email-okaya@codeaurora.org>", "References": "<1503464171-6471-1-git-send-email-okaya@codeaurora.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Sporadic reset issues have been observed with Intel 750 NVMe drive while\nassigning the physical function to the guest machine. The sequence of\nevents observed is as follows:\n\n - perform a Function Level Reset (FLR)\n - sleep up to 1000ms total\n - read ~0 from PCI_COMMAND\n - warn that the device didn't return from FLR\n - touch the device before it's ready\n - device drops config writes when we restore register settings\n - incomplete register restore leaves device in inconsistent state\n - device probe fails because device is in inconsistent state\n\nAfter reset, an endpoint may respond to config requests with Configuration\nRequest Retry Status (CRS) to indicate that it is not ready to accept new\nrequests. See PCIe r3.1, sec 2.3.1 and 6.6.2.\n\nAfter an FLR, read the Vendor ID and use pci_bus_wait_crs() to wait for a\nvalue that indicates the device is ready only if CRS visibility is\nsupported and device is responding with 0x0001.\n\nIf pci_bus_wait_crs() fails, i.e., the device has responded with CRS status\nfor at least the timeout interval, fall back to the old behavior of reading\nthe Command register until it is not ~0.\n\nAlso increase the timeout value from 1 second to 60 seconds to have\nconsistent behavior for root ports that do and do not support CRS\nvisibility.\n\nSigned-off-by: Sinan Kaya <okaya@codeaurora.org>\n---\n drivers/pci/pci.c | 20 ++++++++++++++++++--\n 1 file changed, 18 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex af0cc34..5980ab3 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -3819,19 +3819,35 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)\n */\n static void pci_flr_wait(struct pci_dev *dev)\n {\n+\tint timeout_ms = 60000;\n \tint i = 0;\n \tu32 id;\n \n+\t/*\n+\t * Per PCIe r3.1, sec 6.6.2, the device should finish FLR within\n+\t * 100ms, but even after that, it may respond to config requests\n+\t * with CRS status if it requires more time.\n+\t */\n+\tmsleep(100);\n+\n+\tif (pci_bus_read_config_dword(dev->bus, dev->devfn, PCI_VENDOR_ID, &id))\n+\t\treturn;\n+\n+\tif (pci_bus_crs_visibility_pending(id) &&\n+\t\tpci_bus_wait_crs(dev->bus, dev->devfn, id, timeout_ms))\n+\t\treturn;\n+\n+\ttimeout_ms -= 100;\n \tdo {\n \t\tmsleep(100);\n \t\tpci_read_config_dword(dev, PCI_COMMAND, &id);\n-\t} while (i++ < 10 && id == ~0);\n+\t} while (i++ < (timeout_ms / 100) && id == ~0);\n \n \tif (id == ~0)\n \t\tdev_warn(&dev->dev, \"Failed to return from FLR\\n\");\n \telse if (i > 1)\n \t\tdev_info(&dev->dev, \"Required additional %dms to return from FLR\\n\",\n-\t\t\t (i - 1) * 100);\n+\t\t\t i * 100);\n }\n \n /**\n", "prefixes": [ "V12", "4/5" ] }