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{
    "id": 803942,
    "url": "http://patchwork.ozlabs.org/api/patches/803942/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-12-lokeshvutla@ti.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170821072101.29375-12-lokeshvutla@ti.com>",
    "list_archive_url": null,
    "date": "2017-08-21T07:20:59",
    "name": "[U-Boot,v2,11/13] arm: dts: dra7: sync DT with latest Linux",
    "commit_ref": "4ddaa6ce28e6528e00d32bcdfc7905df2dbbbb06",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "003537ed1235c6dbeda94e4b54a0d37ece292d3e",
    "submitter": {
        "id": 14145,
        "url": "http://patchwork.ozlabs.org/api/people/14145/?format=api",
        "name": "Lokesh Vutla",
        "email": "lokeshvutla@ti.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-12-lokeshvutla@ti.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/803942/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/803942/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Lokesh Vutla <lokeshvutla@ti.com>",
        "To": "Tom Rini <trini@konsulko.com>, <u-boot@lists.denx.de>",
        "Date": "Mon, 21 Aug 2017 12:50:59 +0530",
        "Message-ID": "<20170821072101.29375-12-lokeshvutla@ti.com>",
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        "References": "<20170821072101.29375-1-lokeshvutla@ti.com>",
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        "X-Mailman-Approved-At": "Mon, 21 Aug 2017 10:51:40 +0000",
        "Cc": "Tero Kristo <t-kristo@ti.com>",
        "Subject": "[U-Boot] [PATCH v2 11/13] arm: dts: dra7: sync DT with latest Linux",
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        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>"
    },
    "content": "Sync all dra7* specific dts files with the upstream\nkernel including changes queued for 4.14\n\nhttps://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git/log/?h=omap-for-v4.14/dt-v3\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n---\n arch/arm/dts/am571x-idk.dts                |  56 ++-\n arch/arm/dts/am572x-idk.dts                |  64 ++-\n arch/arm/dts/am57xx-beagle-x15-common.dtsi |  61 ++-\n arch/arm/dts/am57xx-beagle-x15-revb1.dts   |  22 +-\n arch/arm/dts/am57xx-beagle-x15-revc.dts    |  39 ++\n arch/arm/dts/am57xx-beagle-x15.dts         |  16 +\n arch/arm/dts/am57xx-cl-som-am57x.dts       | 617 +++++++++++++++++++++++++++\n arch/arm/dts/am57xx-idk-common.dtsi        | 118 +++++-\n arch/arm/dts/am57xx-sbc-am57x.dts          | 179 ++++++++\n arch/arm/dts/dra7-evm-common.dtsi          | 258 ++++++++++++\n arch/arm/dts/dra7-evm.dts                  | 558 +++----------------------\n arch/arm/dts/dra7.dtsi                     | 101 ++++-\n arch/arm/dts/dra71-evm.dts                 |  45 +-\n arch/arm/dts/dra72-evm-common.dtsi         |  31 +-\n arch/arm/dts/dra72-evm-revc.dts            |  42 +-\n arch/arm/dts/dra72-evm-tps65917.dtsi       |  16 +\n arch/arm/dts/dra72-evm.dts                 |  32 ++\n arch/arm/dts/dra72x-mmc-iodelay.dtsi       | 350 ++++++++++++++++\n arch/arm/dts/dra72x.dtsi                   |  37 +-\n arch/arm/dts/dra74x-mmc-iodelay.dtsi       | 647 +++++++++++++++++++++++++++++\n arch/arm/dts/dra74x.dtsi                   |  92 ++--\n arch/arm/dts/dra76-evm.dts                 | 423 +++++++++++++++++++\n arch/arm/dts/dra76x.dtsi                   |  19 +\n arch/arm/dts/dra7xx-clocks.dtsi            |  20 +\n include/dt-bindings/pinctrl/dra.h          |   3 +\n 25 files changed, 3210 insertions(+), 636 deletions(-)\n create mode 100644 arch/arm/dts/am57xx-beagle-x15-revc.dts\n create mode 100644 arch/arm/dts/am57xx-cl-som-am57x.dts\n create mode 100644 arch/arm/dts/am57xx-sbc-am57x.dts\n create mode 100644 arch/arm/dts/dra7-evm-common.dtsi\n create mode 100644 arch/arm/dts/dra72x-mmc-iodelay.dtsi\n create mode 100644 arch/arm/dts/dra74x-mmc-iodelay.dtsi\n create mode 100644 arch/arm/dts/dra76-evm.dts\n create mode 100644 arch/arm/dts/dra76x.dtsi",
    "diff": "diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts\nindex ac69bb0616..debf946440 100644\n--- a/arch/arm/dts/am571x-idk.dts\n+++ b/arch/arm/dts/am571x-idk.dts\n@@ -11,6 +11,7 @@\n #include <dt-bindings/gpio/gpio.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n #include \"am57xx-idk-common.dtsi\"\n+#include \"dra72x-mmc-iodelay.dtsi\"\n \n / {\n \tmodel = \"TI AM5718 IDK\";\n@@ -62,20 +63,57 @@\n \t\t\tlinux,default-trigger = \"mmc0\";\n \t\t};\n \t};\n+};\n+\n+&omap_dwc3_2 {\n+\textcon = <&extcon_usb2>;\n+};\n \n-\textcon_usb2: extcon_usb2 {\n-\t     compatible = \"linux,extcon-usb-gpio\";\n-\t     id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;\n+&extcon_usb2 {\n+\tid-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;\n+\tvbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&mailbox5 {\n+\tstatus = \"okay\";\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tstatus = \"okay\";\n \t};\n };\n \n-&mmc1 {\n+&mailbox6 {\n \tstatus = \"okay\";\n-\tvmmc-supply = <&ldo1_reg>;\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n };\n \n-&omap_dwc3_2 {\n-\textcon = <&extcon_usb2>;\n+&pcie1_rc {\n+\tstatus = \"okay\";\n+\tgpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&pcie1_ep {\n+\tgpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;\n };\ndiff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts\nindex f9adc00a64..a578fe97ba 100644\n--- a/arch/arm/dts/am572x-idk.dts\n+++ b/arch/arm/dts/am572x-idk.dts\n@@ -12,6 +12,7 @@\n #include <dt-bindings/gpio/gpio.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n #include \"am57xx-idk-common.dtsi\"\n+#include \"dra74x-mmc-iodelay.dtsi\"\n \n / {\n \tmodel = \"TI AM5728 IDK\";\n@@ -23,11 +24,6 @@\n \t\treg = <0x0 0x80000000 0x0 0x80000000>;\n \t};\n \n-\textcon_usb2: extcon_usb2 {\n-\t\tcompatible = \"linux,extcon-usb-gpio\";\n-\t\tid-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;\n-\t};\n-\n \tstatus-leds {\n \t\tcompatible = \"gpio-leds\";\n \t\tcpu0-led {\n@@ -72,14 +68,62 @@\n \t};\n };\n \n+&mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev20>;\n+};\n+\n &omap_dwc3_2 {\n \textcon = <&extcon_usb2>;\n };\n \n-&mmc1 {\n+&extcon_usb2 {\n+\tid-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;\n+\tvbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&sn65hvs882 {\n+\tload-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;\n+};\n+\n+&pcie1_rc {\n \tstatus = \"okay\";\n-\tvmmc-supply = <&v3_3d>;\n-\tvmmc_aux-supply = <&ldo1_reg>;\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */\n+\tgpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&pcie1_ep {\n+\tgpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&mailbox5 {\n+\tstatus = \"okay\";\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&mailbox6 {\n+\tstatus = \"okay\";\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n };\ndiff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi\nindex 01a9e56bfd..49aeecd312 100644\n--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi\n+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi\n@@ -9,16 +9,13 @@\n \n #include \"dra74x.dtsi\"\n #include \"am57xx-commercial-grade.dtsi\"\n+#include \"dra74x-mmc-iodelay.dtsi\"\n #include <dt-bindings/gpio/gpio.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n \n / {\n \tcompatible = \"ti,am572x-beagle-x15\", \"ti,am5728\", \"ti,dra742\", \"ti,dra74\", \"ti,dra7\";\n \n-\tchosen {\n-\t\tstdout-path = &uart3;\n-\t};\n-\n \taliases {\n \t\trtc0 = &mcp_rtc;\n \t\trtc1 = &tps659038_rtc;\n@@ -26,6 +23,10 @@\n \t\tdisplay0 = &hdmi0;\n \t};\n \n+\tchosen {\n+\t\tstdout-path = &uart3;\n+\t};\n+\n \tmemory@0 {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x0 0x80000000 0x0 0x80000000>;\n@@ -166,34 +167,6 @@\n \t};\n };\n \n-&dra7_pmx_core {\n-\tmmc1_pins_default: mmc1_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)\t/* mmc1sdcd.gpio219 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n-\t\t>;\n-\t};\n-\n-\tmmc2_pins_default: mmc2_pins_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n-\t\t>;\n-\t};\n-};\n &i2c1 {\n \tstatus = \"okay\";\n \tclock-frequency = <400000>;\n@@ -208,6 +181,7 @@\n \t\tinterrupt-controller;\n \n \t\tti,system-power-controller;\n+\t\tti,palmas-override-powerhold;\n \n \t\ttps659038_pmic {\n \t\t\tcompatible = \"ti,tps659038-pmic\";\n@@ -387,7 +361,7 @@\n \t};\n \n \teeprom: eeprom@50 {\n-\t\tcompatible = \"at,24c32\";\n+\t\tcompatible = \"atmel,24c32\";\n \t\treg = <0x50>;\n \t};\n };\n@@ -424,19 +398,29 @@\n \t\t\t      <&dra7_pmx_core 0x3f8>;\n };\n \n+&davinci_mdio {\n+\tphy0: ethernet-phy@1 {\n+\t\treg = <1>;\n+\t};\n+\n+\tphy1: ethernet-phy@2 {\n+\t\treg = <2>;\n+\t};\n+};\n+\n &mac {\n \tstatus = \"okay\";\n \tdual_emac;\n };\n \n &cpsw_emac0 {\n-\tphy_id = <&davinci_mdio>, <1>;\n+\tphy-handle = <&phy0>;\n \tphy-mode = \"rgmii\";\n \tdual_emac_res_vlan = <1>;\n };\n \n &cpsw_emac1 {\n-\tphy_id = <&davinci_mdio>, <2>;\n+\tphy-handle = <&phy1>;\n \tphy-mode = \"rgmii\";\n \tdual_emac_res_vlan = <2>;\n };\n@@ -559,7 +543,12 @@\n \t};\n };\n \n-&pcie1 {\n+&pcie1_rc {\n+\tstatus = \"ok\";\n+\tgpios = <&gpio2 8 GPIO_ACTIVE_LOW>;\n+};\n+\n+&pcie1_ep {\n \tgpios = <&gpio2 8 GPIO_ACTIVE_LOW>;\n };\n \ndiff --git a/arch/arm/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/dts/am57xx-beagle-x15-revb1.dts\nindex ca85570629..5a77b33492 100644\n--- a/arch/arm/dts/am57xx-beagle-x15-revb1.dts\n+++ b/arch/arm/dts/am57xx-beagle-x15-revb1.dts\n@@ -19,6 +19,26 @@\n };\n \n &mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;\n \tvmmc-supply = <&vdd_3v3>;\n-\tvmmc-aux-supply = <&ldo1_reg>;\n+\tvqmmc-supply = <&ldo1_reg>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;\n+};\n+\n+/* errata i880 \"Ethernet RGMII2 Limited to 10/100 Mbps\" */\n+&phy1 {\n+\tmax-speed = <100>;\n };\ndiff --git a/arch/arm/dts/am57xx-beagle-x15-revc.dts b/arch/arm/dts/am57xx-beagle-x15-revc.dts\nnew file mode 100644\nindex 0000000000..17c41da3b5\n--- /dev/null\n+++ b/arch/arm/dts/am57xx-beagle-x15-revc.dts\n@@ -0,0 +1,39 @@\n+/*\n+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include \"am57xx-beagle-x15-common.dtsi\"\n+\n+/ {\n+\tmodel = \"TI AM5728 BeagleBoard-X15 rev C\";\n+};\n+\n+&tpd12s015 {\n+\tgpios = <&gpio7 10 GPIO_ACTIVE_HIGH>,\t/* gpio7_10, CT CP HPD */\n+\t\t<&gpio2 30 GPIO_ACTIVE_HIGH>,\t/* gpio2_30, LS OE */\n+\t\t<&gpio7 12 GPIO_ACTIVE_HIGH>;\t/* gpio7_12/sp1_cs2, HPD */\n+};\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n+\tvmmc-supply = <&vdd_3v3>;\n+\tvqmmc-supply = <&ldo1_reg>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev20>;\n+};\ndiff --git a/arch/arm/dts/am57xx-beagle-x15.dts b/arch/arm/dts/am57xx-beagle-x15.dts\nindex 8c66f2efd2..d6689106d2 100644\n--- a/arch/arm/dts/am57xx-beagle-x15.dts\n+++ b/arch/arm/dts/am57xx-beagle-x15.dts\n@@ -20,5 +20,21 @@\n };\n \n &mmc1 {\n+\tpinctrl-names = \"default\", \"hs\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\n \tvmmc-supply = <&ldo1_reg>;\n };\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;\n+};\n+\n+/* errata i880 \"Ethernet RGMII2 Limited to 10/100 Mbps\" */\n+&phy1 {\n+\tmax-speed = <100>;\n+};\ndiff --git a/arch/arm/dts/am57xx-cl-som-am57x.dts b/arch/arm/dts/am57xx-cl-som-am57x.dts\nnew file mode 100644\nindex 0000000000..203266f884\n--- /dev/null\n+++ b/arch/arm/dts/am57xx-cl-som-am57x.dts\n@@ -0,0 +1,617 @@\n+/*\n+ * Support for CompuLab CL-SOM-AM57x System-on-Module\n+ *\n+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/\n+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published by\n+ * the Free Software Foundation.\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include \"dra74x.dtsi\"\n+\n+/ {\n+\tmodel = \"CompuLab CL-SOM-AM57x\";\n+\tcompatible = \"compulab,cl-som-am57x\", \"ti,am5728\", \"ti,dra742\", \"ti,dra74\", \"ti,dra7\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&leds_pins_default>;\n+\n+\t\tled0 {\n+\t\t\tlabel = \"cl-som-am57x:green\";\n+\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n+\tvdd_3v3: fixedregulator-vdd_3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vdd_3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t};\n+\n+\tads7846reg: fixedregulator-ads7846-reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"ads7846-reg\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t};\n+\n+\tsound0: sound0 {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,name = \"CL-SOM-AM57x-Sound-Card\";\n+\t\tsimple-audio-card,format = \"i2s\";\n+\t\tsimple-audio-card,bitclock-master = <&dailink0_master>;\n+\t\tsimple-audio-card,frame-master = <&dailink0_master>;\n+\t\tsimple-audio-card,widgets =\n+\t\t\t\t\t\"Headphone\", \"Headphone Jack\",\n+\t\t\t\t\t\"Microphone\", \"Microphone Jack\",\n+\t\t\t\t\t\"Line\", \"Line Jack\";\n+\t\tsimple-audio-card,routing =\n+\t\t\t\t\t\"Headphone Jack\", \"RHPOUT\",\n+\t\t\t\t\t\"Headphone Jack\", \"LHPOUT\",\n+\t\t\t\t\t\"LLINEIN\", \"Line Jack\",\n+\t\t\t\t\t\"MICIN\", \"Mic Bias\",\n+\t\t\t\t\t\"Mic Bias\", \"Microphone Jack\";\n+\n+\t\tdailink0_master: simple-audio-card,cpu {\n+\t\t\tsound-dai = <&mcasp3>;\n+\t\t};\n+\n+\t\tsimple-audio-card,codec {\n+\t\t\tsound-dai = <&wm8731>;\n+\t\t\tsystem-clock-frequency = <12000000>;\n+\t\t};\n+\t};\n+};\n+\n+&dra7_pmx_core {\n+\tleds_pins_default: leds_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14)\t/* gpmc_a15.gpio2_5 */\n+\t\t>;\n+\t};\n+\n+\ti2c1_pins_default: i2c1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c1_sda.sda */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c1_scl.scl */\n+\t\t>;\n+\t};\n+\n+\ti2c3_pins_default: i2c3_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10)\t/* mcasp1_aclkx.i2c3_sda */\n+\t\t\tDRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10)\t/* mcasp1_fsx.i2c3_scl */\n+\t\t>;\n+\t};\n+\n+\ti2c4_pins_default: i2c4_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10)\t/* mcasp1_acl.i2c4_sda */\n+\t\t\tDRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10)\t/* mcasp1_fsr.i2c4_scl */\n+\t\t>;\n+\t};\n+\n+\ttps659038_pins_default: tps659038_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_default: mmc2_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tqspi1_pins: pinmux_qspi1_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)\t/* gpmc_a13.qspi1_rtclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)\t/* gpmc_a16.qspi1_d0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)\t/* gpmc_a17.qspi1_d1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)\t/* qpmc_a18.qspi1_sclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_cs2.qspi1_cs0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_cs3.qspi1_cs1 */\n+\t\t>;\n+\t};\n+\n+\tcpsw_pins_default: cpsw_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\t/* Slave at addr 0x0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_tclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_tctl */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_td3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_td2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_td1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_td0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */\n+\n+\t\t\t/* Slave at addr 0x1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d12.rgmii1_tclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d13.rgmii1_tctl */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d14.rgmii1_td3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d15.rgmii1_td2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d16.rgmii1_td1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d17.rgmii1_td0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */\n+\t\t>;\n+\t};\n+\n+\tcpsw_pins_sleep: cpsw_pins_sleep {\n+\t\tpinctrl-single,pins = <\n+\t\t\t/* Slave 1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)\n+\n+\t\t\t/* Slave 2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)\n+\t\t>;\n+\t};\n+\n+\tdavinci_mdio_pins_default: davinci_mdio_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\t/* MDIO */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3)\t/* vin2a_d11.mdio_d */\n+\t\t>;\n+\t};\n+\n+\tdavinci_mdio_pins_sleep: davinci_mdio_pins_sleep {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)\n+\t\t>;\n+\t};\n+\n+\tads7846_pins: pinmux_ads7846_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */\n+\t\t>;\n+\t};\n+\n+\tmcasp3_pins_default: mcasp3_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */\n+\t\t\tDRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */\n+\t\t>;\n+\t};\n+\n+\tmcasp3_pins_sleep: mcasp3_pins_sleep {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)\n+\t\t>;\n+\t};\n+};\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins_default>;\n+\tclock-frequency = <400000>;\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c3_pins_default>;\n+\tclock-frequency = <400000>;\n+};\n+\n+&i2c4 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c4_pins_default>;\n+\tclock-frequency = <400000>;\n+\n+\ttps659038: tps659038@58 {\n+\t\tcompatible = \"ti,tps659038\";\n+\t\treg = <0x58>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <0 IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&tps659038_pins_default>;\n+\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-controller;\n+\n+\t\tti,system-power-controller;\n+\n+\t\ttps659038_pmic {\n+\t\t\tcompatible = \"ti,tps659038-pmic\";\n+\n+\t\t\tregulators {\n+\t\t\t\tsmps12_reg: smps12 {\n+\t\t\t\t\t/* VDD_MPU */\n+\t\t\t\t\tregulator-name = \"smps12\";\n+\t\t\t\t\tregulator-min-microvolt = < 850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps3_reg: smps3 {\n+\t\t\t\t\t/* VDD_DDR */\n+\t\t\t\t\tregulator-name = \"smps3\";\n+\t\t\t\t\tregulator-min-microvolt = <1500000>;\n+\t\t\t\t\tregulator-max-microvolt = <1500000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps45_reg: smps45 {\n+\t\t\t\t\t/* VDD_DSPEVE */\n+\t\t\t\t\tregulator-name = \"smps45\";\n+\t\t\t\t\tregulator-min-microvolt = < 850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps6_reg: smps6 {\n+\t\t\t\t\t/* VDD_GPU */\n+\t\t\t\t\tregulator-name = \"smps6\";\n+\t\t\t\t\tregulator-min-microvolt = < 850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps7_reg: smps7 {\n+\t\t\t\t\t/* VDD_CORE */\n+\t\t\t\t\tregulator-name = \"smps7\";\n+\t\t\t\t\tregulator-min-microvolt = < 850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1160000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps8_reg: smps8 {\n+\t\t\t\t\t/* VDD_IVA */\n+\t\t\t\t\tregulator-name = \"smps8\";\n+\t\t\t\t\tregulator-min-microvolt = < 850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps9_reg: smps9 {\n+\t\t\t\t\t/* PMIC_3V3 */\n+\t\t\t\t\tregulator-name = \"smps9\";\n+\t\t\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\n+\t\t\t\tldo1_reg: ldo1 {\n+\t\t\t\t\t/* VDD_SD / VDDSHV8  */\n+\t\t\t\t\tregulator-name = \"ldo1\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo2_reg: ldo2 {\n+\t\t\t\t\t/* VDD_1V8 */\n+\t\t\t\t\tregulator-name = \"ldo2\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo3_reg: ldo3 {\n+\t\t\t\t\t/* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */\n+\t\t\t\t\tregulator-name = \"ldo3\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo4_reg: ldo4 {\n+\t\t\t\t\t/* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */\n+\t\t\t\t\tregulator-name = \"ldo4\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo9_reg: ldo9 {\n+\t\t\t\t\t/* VDD_RTC */\n+\t\t\t\t\tregulator-name = \"ldo9\";\n+\t\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\t\tregulator-max-microvolt = <1050000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldoln_reg: ldoln {\n+\t\t\t\t\t/* VDDA_1V8_PLL */\n+\t\t\t\t\tregulator-name = \"ldoln\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldousb_reg: ldousb {\n+\t\t\t\t\t/* VDDA_3V_USB: VDDA_USBHS33 */\n+\t\t\t\t\tregulator-name = \"ldousb\";\n+\t\t\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\t/* regen1 not used */\n+\t\t\t};\n+\t\t};\n+\n+\t\ttps659038_pwr_button: tps659038_pwr_button {\n+\t\t\tcompatible = \"ti,palmas-pwrbutton\";\n+\t\t\tinterrupt-parent = <&tps659038>;\n+\t\t\tinterrupts = <1 IRQ_TYPE_EDGE_FALLING>;\n+\t\t\twakeup-source;\n+\t\t\tti,palmas-long-press-seconds = <12>;\n+\t\t};\n+\n+\t\ttps659038_gpio: tps659038_gpio {\n+\t\t\tcompatible = \"ti,palmas-gpio\";\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t};\n+\t};\n+\n+\trtc0: rtc@56 {\n+\t\tcompatible = \"emmicro,em3027\";\n+\t\treg = <0x56>;\n+\t};\n+\n+\teeprom_module: atmel@50 {\n+\t\tcompatible = \"atmel,24c08\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <16>;\n+\t};\n+\n+\twm8731: wm8731@1a {\n+\t\t#sound-dai-cells = <0>;\n+\t\tcompatible = \"wlf,wm8731\";\n+\t\treg = <0x1a>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu0-supply = <&smps12_reg>;\n+\tvoltage-tolerance = <1>;\n+};\n+\n+&sata {\n+\tstatus = \"okay\";\n+};\n+\n+&mailbox5 {\n+\tstatus = \"okay\";\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&mailbox6 {\n+\tstatus = \"okay\";\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&mmc2 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\n+\tvmmc-supply = <&vdd_3v3>;\n+\tbus-width = <8>;\n+\tti,non-removable;\n+\tcap-mmc-dual-data-rate;\n+};\n+\n+&qspi {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&qspi1_pins>;\n+\n+\tspi-max-frequency = <48000000>;\n+\n+\tspi_flash: spi_flash@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spansion,m25p80\", \"jedec,spi-nor\";\n+\t\treg = <0>;\t\t\t\t/* CS0 */\n+\t\tspi-max-frequency = <48000000>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0x0 0xc0000>;\n+\t\t};\n+\n+\t\tpartition@c0000 {\n+\t\t\tlabel = \"uboot environment\";\n+\t\t\treg = <0xc0000 0x40000>;\n+\t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tlabel = \"reserved\";\n+\t\t\treg = <0x100000 0x0>;\n+\t\t};\n+\t};\n+\n+\t/* touch controller */\n+\tads7846@0 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&ads7846_pins>;\n+\n+\t\tcompatible = \"ti,ads7846\";\n+\t\tvcc-supply = <&ads7846reg>;\n+\n+\t\treg = <1>;                              /* CS1 */\n+\t\tspi-max-frequency = <1500000>;\n+\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <31 0>;\n+\t\tpendown-gpio = <&gpio1 31 0>;\n+\n+\n+\t\tti,x-min = /bits/ 16 <0x0>;\n+\t\tti,x-max = /bits/ 16 <0x0fff>;\n+\t\tti,y-min = /bits/ 16 <0x0>;\n+\t\tti,y-max = /bits/ 16 <0x0fff>;\n+\n+\t\tti,x-plate-ohms = /bits/ 16 <180>;\n+\t\tti,pressure-max = /bits/ 16 <255>;\n+\n+\t\tti,debounce-max = /bits/ 16 <30>;\n+\t\tti,debounce-tol = /bits/ 16 <10>;\n+\t\tti,debounce-rep = /bits/ 16 <1>;\n+\n+\t\twakeup-source;\n+\t};\n+};\n+\n+&mac {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\", \"sleep\";\n+\tpinctrl-0 = <&cpsw_pins_default>;\n+\tpinctrl-1 = <&cpsw_pins_sleep>;\n+\tdual_emac;\n+};\n+\n+&cpsw_emac0 {\n+\tphy_id = <&davinci_mdio>, <0>;\n+\tphy-mode = \"rgmii-txid\";\n+\tdual_emac_res_vlan = <0>;\n+};\n+\n+&cpsw_emac1 {\n+\tphy_id = <&davinci_mdio>, <1>;\n+\tphy-mode = \"rgmii-txid\";\n+\tdual_emac_res_vlan = <1>;\n+};\n+\n+&davinci_mdio {\n+\tpinctrl-names = \"default\", \"sleep\";\n+\tpinctrl-0 = <&davinci_mdio_pins_default>;\n+\tpinctrl-1 = <&davinci_mdio_pins_sleep>;\n+};\n+\n+&usb2_phy1 {\n+\tphy-supply = <&ldousb_reg>;\n+};\n+\n+&usb2_phy2 {\n+\tphy-supply = <&ldousb_reg>;\n+};\n+\n+&usb1 {\n+\tdr_mode = \"host\";\n+};\n+\n+&usb2 {\n+\tdr_mode = \"host\";\n+};\n+\n+&mcasp3 {\n+\t#sound-dai-cells = <0>;\n+\tpinctrl-names = \"default\", \"sleep\";\n+\tpinctrl-0 = <&mcasp3_pins_default>;\n+\tpinctrl-1 = <&mcasp3_pins_sleep>;\n+\tstatus = \"okay\";\n+\n+\top-mode = <0>;\t/* MCASP_IIS_MODE */\n+\ttdm-slots = <2>;\n+\t/* 4 serializers */\n+\tserial-dir = <\t/* 0: INACTIVE, 1: TX, 2: RX */\n+\t\t1 2 0 0\n+\t>;\n+};\n+\n+&gpio3 {\n+\tstatus = \"okay\";\n+\tti,no-reset-on-init;\n+};\n+\n+&gpio2 {\n+\tstatus = \"okay\";\n+\tti,no-reset-on-init;\n+};\ndiff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi\nindex 30118ed233..97aa8e6a56 100644\n--- a/arch/arm/dts/am57xx-idk-common.dtsi\n+++ b/arch/arm/dts/am57xx-idk-common.dtsi\n@@ -47,6 +47,74 @@\n \t\tregulator-always-on;\n \t\tregulator-boot-on;\n \t};\n+\n+\tleds-iio {\n+\t\tstatus = \"disabled\";\n+\t\tcompatible = \"gpio-leds\";\n+\t\tled-out0 {\n+\t\t\tlabel = \"out0\";\n+\t\t\tgpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out1 {\n+\t\t\tlabel = \"out1\";\n+\t\t\tgpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out2 {\n+\t\t\tlabel = \"out2\";\n+\t\t\tgpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out3 {\n+\t\t\tlabel = \"out3\";\n+\t\t\tgpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out4 {\n+\t\t\tlabel = \"out4\";\n+\t\t\tgpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out5 {\n+\t\t\tlabel = \"out5\";\n+\t\t\tgpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out6 {\n+\t\t\tlabel = \"out6\";\n+\t\t\tgpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-out7 {\n+\t\t\tlabel = \"out7\";\n+\t\t\tgpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+};\n+\n+&dra7_pmx_core {\n+\tdcan1_pins_default: dcan1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* dcan1_tx */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0)\t\t/* dcan1_rx */\n+\t\t>;\n+\t};\n+\n+\tdcan1_pins_sleep: dcan1_pins_sleep {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)\t/* dcan1_tx.off */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP)\t/* dcan1_rx.off */\n+\t\t>;\n+\t};\n };\n \n &i2c1 {\n@@ -61,6 +129,7 @@\n \t\t#interrupt-cells = <2>;\n \t\tinterrupt-controller;\n \t\tti,system-power-controller;\n+\t\tti,palmas-override-powerhold;\n \n \t\ttps659038_pmic {\n \t\t\tcompatible = \"ti,tps659038-pmic\";\n@@ -254,6 +323,35 @@\n \t\t\tgpio-controller;\n \t\t\t#gpio-cells = <2>;\n \t\t};\n+\n+\t\textcon_usb2: tps659038_usb {\n+\t\t\tcompatible = \"ti,palmas-usb-vid\";\n+\t\t\tti,enable-vbus-detection;\n+\t\t\tti,enable-id-detection;\n+\t\t\t/* ID & VBUS GPIOs provided in board dts */\n+\t\t};\n+\t};\n+\n+\ttpic2810: tpic2810@60 {\n+\t\tcompatible = \"ti,tpic2810\";\n+\t\treg = <0x60>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t};\n+};\n+\n+&mcspi3 {\n+\tstatus = \"okay\";\n+\tti,pindir-d0-out-d1-in;\n+\n+\tsn65hvs882: sn65hvs882@0 {\n+\t\tcompatible = \"pisosr-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <1000000>;\n+\t\tspi-cpol;\n \t};\n };\n \n@@ -298,7 +396,15 @@\n };\n \n &usb2 {\n-\tdr_mode = \"otg\";\n+\tdr_mode = \"peripheral\";\n+};\n+\n+&mmc1 {\n+\tstatus = \"okay\";\n+\tvmmc-supply = <&v3_3d>;\n+\tvqmmc-supply = <&ldo1_reg>;\n+\tbus-width = <4>;\n+\tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */\n };\n \n &mmc2 {\n@@ -309,12 +415,20 @@\n \tmax-frequency = <96000000>;\n };\n \n+&dcan1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\", \"sleep\", \"active\";\n+\tpinctrl-0 = <&dcan1_pins_sleep>;\n+\tpinctrl-1 = <&dcan1_pins_sleep>;\n+\tpinctrl-2 = <&dcan1_pins_default>;\n+};\n+\n &qspi {\n \tstatus = \"okay\";\n \n \tspi-max-frequency = <76800000>;\n \tm25p80@0 {\n-\t\tcompatible = \"s25fl256s1\", \"spi-flash\", \"jedec,spi-nor\";\n+\t\tcompatible = \"s25fl256s1\", \"jedec,spi-nor\";\n \t\tspi-max-frequency = <76800000>;\n \t\treg = <0>;\n \t\tspi-tx-bus-width = <1>;\ndiff --git a/arch/arm/dts/am57xx-sbc-am57x.dts b/arch/arm/dts/am57xx-sbc-am57x.dts\nnew file mode 100644\nindex 0000000000..31f9be6324\n--- /dev/null\n+++ b/arch/arm/dts/am57xx-sbc-am57x.dts\n@@ -0,0 +1,179 @@\n+/*\n+ * Support for CompuLab SBC-AM57x single board computer\n+ *\n+ * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/\n+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published by\n+ * the Free Software Foundation.\n+ */\n+\n+#include \"am57xx-cl-som-am57x.dts\"\n+#include \"compulab-sb-som.dtsi\"\n+\n+/ {\n+\tmodel = \"CompuLab CL-SOM-AM57x on SB-SOM-AM57x\";\n+\tcompatible = \"compulab,sbc-am57x\", \"compulab,cl-som-am57x\", \"ti,am5728\", \"ti,dra742\", \"ti,dra74\", \"ti,dra7\";\n+\n+\taliases {\n+\t\tdisplay0 = &lcd0;\n+\t\tdisplay1 = &hdmi;\n+\t};\n+};\n+\n+&dra7_pmx_core {\n+\tuart3_pins_default: uart3_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0)\t/* uart3_rxd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0)\t/* uart3_txd */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_default: mmc1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)\t/* mmc1_sdcd.gpio6_27 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14)\t/* mmc1_sdwp.gpio6_28 */\n+\t\t>;\n+\t};\n+\n+\tusb1_pins: pinmux_usb1_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */\n+\t\t>;\n+\t};\n+\n+\ti2c5_pins_default: i2c5_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10)\t/* mcasp1_axr0.i2c5_sda */\n+\t\t\tDRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10)\t/* mcasp1_axr1.i2c5_scl */\n+\t\t>;\n+\t};\n+\n+\tlcd_pins_default: lcd_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14)      /* vin2a_vsync0.gpio4_0 */\n+\t\t>;\n+\t};\n+\n+\thdmi_pins: pinmux_hdmi_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)\t/* i2c2_sda.hdmi1_ddc_scl */\n+\t\t\tDRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)\t/* i2c2_scl.hdmi1_ddc_sda */\n+\t\t>;\n+\t};\n+\n+\thdmi_conn_pins: pinmux_hdmi_conn_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14)\t/* spi1_cs2.gpio7_12 */\n+\t\t>;\n+\t};\n+};\n+\n+&uart3 {\n+\tstatus = \"okay\";\n+\tinterrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t      <&dra7_pmx_core 0x3f8>;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart3_pins_default>;\n+};\n+\n+&mmc1 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\n+\tvmmc-supply = <&ldo1_reg>;\n+\tbus-width = <4>;\n+\tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;\n+\twp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&usb1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&usb1_pins>;\n+};\n+\n+&i2c5 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c5_pins_default>;\n+\tclock-frequency = <400000>;\n+\n+\teeprom_base: atmel@54 {\n+\t\tcompatible = \"atmel,24c08\";\n+\t\treg = <0x54>;\n+\t\tpagesize = <16>;\n+\t};\n+\n+\tpca9555: pca9555@20 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x20>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t};\n+};\n+\n+&dss {\n+\tstatus = \"ok\";\n+\n+\tvdda_video-supply = <&ldoln_reg>;\n+\n+\tport {\n+\t\tdpi_lcd_out: endpoint {\n+\t\t\tremote-endpoint = <&lcd_in>;\n+\t\t\tdata-lines = <24>;\n+\t\t};\n+\t};\n+};\n+\n+&lcd0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&lcd_pins_default>;\n+\n+\tenable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH\n+\t\t\t&gpio4 0 GPIO_ACTIVE_HIGH>;\n+\n+\tport {\n+\t\tlcd_in: endpoint {\n+\t\t\tremote-endpoint = <&dpi_lcd_out>;\n+\t\t\tdata-lines = <24>;\n+\t\t};\n+\t};\n+};\n+\n+&hdmi {\n+\tstatus = \"ok\";\n+\tvdda-supply = <&ldo4_reg>;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&hdmi_pins>;\n+\n+\tport {\n+\t\thdmi_out: endpoint {\n+\t\t\tremote-endpoint = <&hdmi_connector_in>;\n+\t\t\tlanes = <1 0 3 2 5 4 7 6>;\n+\t\t};\n+\t};\n+};\n+\n+&hdmi_conn {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&hdmi_conn_pins>;\n+\n+\thpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;\n+\n+\tport {\n+\t\thdmi_connector_in: endpoint {\n+\t\t\tremote-endpoint = <&hdmi_out>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi\nnew file mode 100644\nindex 0000000000..343e95f9a0\n--- /dev/null\n+++ b/arch/arm/dts/dra7-evm-common.dtsi\n@@ -0,0 +1,258 @@\n+/*\n+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/clk/ti-dra7-atl.h>\n+#include <dt-bindings/input/input.h>\n+\n+/ {\n+\tchosen {\n+\t\tstdout-path = &uart1;\n+\t};\n+\n+\textcon_usb1: extcon_usb1 {\n+\t\tcompatible = \"linux,extcon-usb-gpio\";\n+\t\tid-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tsound0: sound0 {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,name = \"DRA7xx-EVM\";\n+\t\tsimple-audio-card,widgets =\n+\t\t\t\"Headphone\", \"Headphone Jack\",\n+\t\t\t\"Line\", \"Line Out\",\n+\t\t\t\"Microphone\", \"Mic Jack\",\n+\t\t\t\"Line\", \"Line In\";\n+\t\tsimple-audio-card,routing =\n+\t\t\t\"Headphone Jack\",\t\"HPLOUT\",\n+\t\t\t\"Headphone Jack\",\t\"HPROUT\",\n+\t\t\t\"Line Out\",\t\t\"LLOUT\",\n+\t\t\t\"Line Out\",\t\t\"RLOUT\",\n+\t\t\t\"MIC3L\",\t\t\"Mic Jack\",\n+\t\t\t\"MIC3R\",\t\t\"Mic Jack\",\n+\t\t\t\"Mic Jack\",\t\t\"Mic Bias\",\n+\t\t\t\"LINE1L\",\t\t\"Line In\",\n+\t\t\t\"LINE1R\",\t\t\"Line In\";\n+\t\tsimple-audio-card,format = \"dsp_b\";\n+\t\tsimple-audio-card,bitclock-master = <&sound0_master>;\n+\t\tsimple-audio-card,frame-master = <&sound0_master>;\n+\t\tsimple-audio-card,bitclock-inversion;\n+\n+\t\tsound0_master: simple-audio-card,cpu {\n+\t\t\tsound-dai = <&mcasp3>;\n+\t\t\tsystem-clock-frequency = <5644800>;\n+\t\t};\n+\n+\t\tsimple-audio-card,codec {\n+\t\t\tsound-dai = <&tlv320aic3106>;\n+\t\t\tclocks = <&atl_clkin2_ck>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tled0 {\n+\t\t\tlabel = \"dra7:usr1\";\n+\t\t\tgpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled1 {\n+\t\t\tlabel = \"dra7:usr2\";\n+\t\t\tgpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled2 {\n+\t\t\tlabel = \"dra7:usr3\";\n+\t\t\tgpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled3 {\n+\t\t\tlabel = \"dra7:usr4\";\n+\t\t\tgpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n+\tgpio_keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tautorepeat;\n+\n+\t\tUSER1 {\n+\t\t\tlabel = \"btnUser1\";\n+\t\t\tlinux,code = <BTN_0>;\n+\t\t\tgpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tUSER2 {\n+\t\t\tlabel = \"btnUser2\";\n+\t\t\tlinux,code = <BTN_1>;\n+\t\t\tgpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+};\n+\n+&mcspi1 {\n+\tstatus = \"okay\";\n+};\n+\n+&mcspi2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+\tinterrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t      <&dra7_pmx_core 0x3e0>;\n+};\n+\n+&uart2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart3 {\n+\tstatus = \"okay\";\n+};\n+\n+&qspi {\n+\tstatus = \"okay\";\n+\n+\tspi-max-frequency = <76800000>;\n+\tm25p80@0 {\n+\t\tcompatible = \"s25fl256s1\";\n+\t\tspi-max-frequency = <76800000>;\n+\t\treg = <0>;\n+\t\tspi-tx-bus-width = <1>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\t/* MTD partition table.\n+\t\t * The ROM checks the first four physical blocks\n+\t\t * for a valid file to boot and the flash here is\n+\t\t * 64KiB block size.\n+\t\t */\n+\t\tpartition@0 {\n+\t\t\tlabel = \"QSPI.SPL\";\n+\t\t\treg = <0x00000000 0x000010000>;\n+\t\t};\n+\t\tpartition@1 {\n+\t\t\tlabel = \"QSPI.SPL.backup1\";\n+\t\t\treg = <0x00010000 0x00010000>;\n+\t\t};\n+\t\tpartition@2 {\n+\t\t\tlabel = \"QSPI.SPL.backup2\";\n+\t\t\treg = <0x00020000 0x00010000>;\n+\t\t};\n+\t\tpartition@3 {\n+\t\t\tlabel = \"QSPI.SPL.backup3\";\n+\t\t\treg = <0x00030000 0x00010000>;\n+\t\t};\n+\t\tpartition@4 {\n+\t\t\tlabel = \"QSPI.u-boot\";\n+\t\t\treg = <0x00040000 0x00100000>;\n+\t\t};\n+\t\tpartition@5 {\n+\t\t\tlabel = \"QSPI.u-boot-spl-os\";\n+\t\t\treg = <0x00140000 0x00080000>;\n+\t\t};\n+\t\tpartition@6 {\n+\t\t\tlabel = \"QSPI.u-boot-env\";\n+\t\t\treg = <0x001c0000 0x00010000>;\n+\t\t};\n+\t\tpartition@7 {\n+\t\t\tlabel = \"QSPI.u-boot-env.backup1\";\n+\t\t\treg = <0x001d0000 0x0010000>;\n+\t\t};\n+\t\tpartition@8 {\n+\t\t\tlabel = \"QSPI.kernel\";\n+\t\t\treg = <0x001e0000 0x0800000>;\n+\t\t};\n+\t\tpartition@9 {\n+\t\t\tlabel = \"QSPI.file-system\";\n+\t\t\treg = <0x009e0000 0x01620000>;\n+\t\t};\n+\t};\n+};\n+\n+&omap_dwc3_1 {\n+\textcon = <&extcon_usb1>;\n+};\n+\n+&usb1 {\n+\tdr_mode = \"otg\";\n+\textcon = <&extcon_usb1>;\n+};\n+\n+&usb2 {\n+\tdr_mode = \"host\";\n+};\n+\n+&atl {\n+\tassigned-clocks = <&abe_dpll_sys_clk_mux>,\n+\t\t\t  <&atl_gfclk_mux>,\n+\t\t\t  <&dpll_abe_ck>,\n+\t\t\t  <&dpll_abe_m2x2_ck>,\n+\t\t\t  <&atl_clkin2_ck>;\n+\tassigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;\n+\tassigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;\n+\n+\tstatus = \"okay\";\n+\n+\tatl2 {\n+\t\tbws = <DRA7_ATL_WS_MCASP2_FSX>;\n+\t\taws = <DRA7_ATL_WS_MCASP3_FSX>;\n+\t};\n+};\n+\n+&mcasp3 {\n+\t#sound-dai-cells = <0>;\n+\n+\tassigned-clocks = <&mcasp3_ahclkx_mux>;\n+\tassigned-clock-parents = <&atl_clkin2_ck>;\n+\n+\tstatus = \"okay\";\n+\n+\top-mode = <0>;          /* MCASP_IIS_MODE */\n+\ttdm-slots = <2>;\n+\t/* 4 serializer */\n+\tserial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */\n+\t\t1 2 0 0\n+\t>;\n+\ttx-num-evt = <32>;\n+\trx-num-evt = <32>;\n+};\n+\n+&mailbox5 {\n+\tstatus = \"okay\";\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&mailbox6 {\n+\tstatus = \"okay\";\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\t\tstatus = \"okay\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts\nindex 4d882ab338..aa426dabb6 100644\n--- a/arch/arm/dts/dra7-evm.dts\n+++ b/arch/arm/dts/dra7-evm.dts\n@@ -8,24 +8,26 @@\n /dts-v1/;\n \n #include \"dra74x.dtsi\"\n-#include <dt-bindings/gpio/gpio.h>\n-#include <dt-bindings/clk/ti-dra7-atl.h>\n-#include <dt-bindings/input/input.h>\n+#include \"dra7-evm-common.dtsi\"\n+#include \"dra74x-mmc-iodelay.dtsi\"\n \n / {\n \tmodel = \"TI DRA742\";\n \tcompatible = \"ti,dra7-evm\", \"ti,dra742\", \"ti,dra74\", \"ti,dra7\";\n \n-\tchosen {\n-\t\tstdout-path = &uart1;\n-\t\ttick-timer = &timer2;\n-\t};\n-\n \tmemory@0 {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */\n \t};\n \n+\tevm_1v8_sw: fixedregulator-evm_1v8 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"evm_1v8\";\n+\t\tvin-supply = <&smps9_reg>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t};\n+\n \tevm_3v3_sd: fixedregulator-sd {\n \t\tcompatible = \"regulator-fixed\";\n \t\tregulator-name = \"evm_3v3_sd\";\n@@ -52,11 +54,6 @@\n \t\tregulator-max-microvolt = <1800000>;\n \t};\n \n-\textcon_usb1: extcon_usb1 {\n-\t\tcompatible = \"linux,extcon-usb-gpio\";\n-\t\tid-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;\n-\t};\n-\n \textcon_usb2: extcon_usb2 {\n \t\tcompatible = \"linux,extcon-usb-gpio\";\n \t\tid-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;\n@@ -74,286 +71,9 @@\n \t\tgpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;\n \t};\n \n-\tsound0: sound0 {\n-\t\tcompatible = \"simple-audio-card\";\n-\t\tsimple-audio-card,name = \"DRA7xx-EVM\";\n-\t\tsimple-audio-card,widgets =\n-\t\t\t\"Headphone\", \"Headphone Jack\",\n-\t\t\t\"Line\", \"Line Out\",\n-\t\t\t\"Microphone\", \"Mic Jack\",\n-\t\t\t\"Line\", \"Line In\";\n-\t\tsimple-audio-card,routing =\n-\t\t\t\"Headphone Jack\",\t\"HPLOUT\",\n-\t\t\t\"Headphone Jack\",\t\"HPROUT\",\n-\t\t\t\"Line Out\",\t\t\"LLOUT\",\n-\t\t\t\"Line Out\",\t\t\"RLOUT\",\n-\t\t\t\"MIC3L\",\t\t\"Mic Jack\",\n-\t\t\t\"MIC3R\",\t\t\"Mic Jack\",\n-\t\t\t\"Mic Jack\",\t\t\"Mic Bias\",\n-\t\t\t\"LINE1L\",\t\t\"Line In\",\n-\t\t\t\"LINE1R\",\t\t\"Line In\";\n-\t\tsimple-audio-card,format = \"dsp_b\";\n-\t\tsimple-audio-card,bitclock-master = <&sound0_master>;\n-\t\tsimple-audio-card,frame-master = <&sound0_master>;\n-\t\tsimple-audio-card,bitclock-inversion;\n-\n-\t\tsound0_master: simple-audio-card,cpu {\n-\t\t\tsound-dai = <&mcasp3>;\n-\t\t\tsystem-clock-frequency = <5644800>;\n-\t\t};\n-\n-\t\tsimple-audio-card,codec {\n-\t\t\tsound-dai = <&tlv320aic3106>;\n-\t\t\tclocks = <&atl_clkin2_ck>;\n-\t\t};\n-\t};\n-\n-\tleds {\n-\t\tcompatible = \"gpio-leds\";\n-\t\tled0 {\n-\t\t\tlabel = \"dra7:usr1\";\n-\t\t\tgpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled1 {\n-\t\t\tlabel = \"dra7:usr2\";\n-\t\t\tgpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled2 {\n-\t\t\tlabel = \"dra7:usr3\";\n-\t\t\tgpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\n-\t\tled3 {\n-\t\t\tlabel = \"dra7:usr4\";\n-\t\t\tgpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"off\";\n-\t\t};\n-\t};\n-\n-\tgpio_keys {\n-\t\tcompatible = \"gpio-keys\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tautorepeat;\n-\n-\t\tUSER1 {\n-\t\t\tlabel = \"btnUser1\";\n-\t\t\tlinux,code = <BTN_0>;\n-\t\t\tgpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;\n-\t\t};\n-\n-\t\tUSER2 {\n-\t\t\tlabel = \"btnUser2\";\n-\t\t\tlinux,code = <BTN_1>;\n-\t\t\tgpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;\n-\t\t};\n-\t};\n };\n \n &dra7_pmx_core {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&vtt_pin>;\n-\n-\tvtt_pin: pinmux_vtt_pin {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */\n-\t\t>;\n-\t};\n-\n-\ti2c1_pins: pinmux_i2c1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */\n-\t\t>;\n-\t};\n-\n-\ti2c2_pins: pinmux_i2c2_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */\n-\t\t\tDRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */\n-\t\t>;\n-\t};\n-\n-\ti2c3_pins: pinmux_i2c3_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */\n-\t\t\tDRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */\n-\t\t>;\n-\t};\n-\n-\tmcspi1_pins: pinmux_mcspi1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */\n-\t\t>;\n-\t};\n-\n-\tmcspi2_pins: pinmux_mcspi2_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */\n-\t\t>;\n-\t};\n-\n-\tuart1_pins: pinmux_uart1_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */\n-\t\t>;\n-\t};\n-\n-\tuart2_pins: pinmux_uart2_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */\n-\t\t\tDRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */\n-\t\t>;\n-\t};\n-\n-\tuart3_pins: pinmux_uart3_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */\n-\t\t\tDRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */\n-\t\t>;\n-\t};\n-\n-\tusb1_pins: pinmux_usb1_pins {\n-                pinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */\n-                >;\n-        };\n-\n-\tusb2_pins: pinmux_usb2_pins {\n-                pinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */\n-                >;\n-        };\n-\n-\tnand_flash_x16: nand_flash_x16 {\n-\t\t/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch\n-\t\t * So NAND flash requires following switch settings:\n-\t\t * SW5.1 (NAND_BOOTn) = ON (LOW)\n-\t\t * SW5.9 (GPMC_WPN) = OFF (HIGH)\n-\t\t */\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad0\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad1\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad2\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad3\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad4\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad5\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad6\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad7\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad8\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad9\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad10\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad11\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad12\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad13\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad14\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0)\t/* gpmc_ad15\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP  | MUX_MODE0)\t/* gpmc_wait0\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0)\t/* gpmc_wen\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_csn0\t*/\n-\t\t\tDRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0)\t/* gpmc_advn_ale */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0)\t/* gpmc_oen_ren\t */\n-\t\t\tDRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0)\t/* gpmc_be0n_cle */\n-\t\t>;\n-\t};\n-\n-\tcpsw_default: cpsw_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_txc.rgmii0_txc */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_txctl.rgmii0_txctl */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_td3.rgmii0_txd3 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_txd2.rgmii0_txd2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_txd1.rgmii0_txd1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)\t/* rgmii0_txd0.rgmii0_txd0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxc.rgmii0_rxc */\n-\t\t\tDRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxctl.rgmii0_rxctl */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxd3.rgmii0_rxd3 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxd2.rgmii0_rxd2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxd1.rgmii0_rxd1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)\t/* rgmii0_rxd0.rgmii0_rxd0 */\n-\n-\t\t\t/* Slave 2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d12.rgmii1_txc */\n-\t\t\tDRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d13.rgmii1_tctl */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d14.rgmii1_td3 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d15.rgmii1_td2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d16.rgmii1_td1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)\t/* vin2a_d17.rgmii1_td0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)\t/* vin2a_d18.rgmii1_rclk */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)\t/* vin2a_d19.rgmii1_rctl */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)\t/* vin2a_d20.rgmii1_rd3 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)\t/* vin2a_d21.rgmii1_rd2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)\t/* vin2a_d22.rgmii1_rd1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)\t/* vin2a_d23.rgmii1_rd0 */\n-\t\t>;\n-\n-\t};\n-\n-\tcpsw_sleep: cpsw_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\t/* Slave 1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)\n-\n-\t\t\t/* Slave 2 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_default: davinci_mdio_default {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* mdio_d.mdio_d */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mdio_clk.mdio_clk */\n-\t\t>;\n-\t};\n-\n-\tdavinci_mdio_sleep: davinci_mdio_sleep {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)\n-\t\t>;\n-\t};\n-\n \tdcan1_pins_default: dcan1_pins_default {\n \t\tpinctrl-single,pins = <\n \t\t\tDRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */\n@@ -368,41 +88,43 @@\n \t\t>;\n \t};\n \n-\tatl_pins: pinmux_atl_pins {\n-\t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)\t/* xref_clk1.atl_clk1 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)\t/* xref_clk2.atl_clk2 */\n-\t\t>;\n-\t};\n-\n-\tmcasp3_pins: pinmux_mcasp3_pins {\n+\tmmc1_pins_default: mmc1_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mcasp3_aclkx */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mcasp3_fsx */\n-\t\t\tDRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mcasp3_axr0 */\n-\t\t\tDRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* mcasp3_axr1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)\t/* mmc1sdcd.gpio219 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n \t\t>;\n \t};\n \n-\tmcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {\n+\tmmc2_pins_default: mmc2_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tDRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)\n-\t\t\tDRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n \t\t>;\n \t};\n };\n \n &i2c1 {\n \tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c1_pins>;\n \tclock-frequency = <400000>;\n \n \ttps659038: tps659038@58 {\n \t\tcompatible = \"ti,tps659038\";\n \t\treg = <0x58>;\n+\t\tti,palmas-override-powerhold;\n+\t\tti,system-power-controller;\n \n \t\ttps659038_pmic {\n \t\t\tcompatible = \"ti,tps659038-pmic\";\n@@ -566,7 +288,6 @@\n \t\tinterrupts = <11 IRQ_TYPE_EDGE_FALLING>;\n \t\tinterrupt-controller;\n \t\t#interrupt-cells = <2>;\n-\t\tu-boot,i2c-offset-len = <0>;\n \t};\n \n \ttlv320aic3106: tlv320aic3106@19 {\n@@ -587,8 +308,6 @@\n \n &i2c2 {\n \tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c2_pins>;\n \tclock-frequency = <400000>;\n \n \tpcf_hdmi: gpio@26 {\n@@ -606,156 +325,60 @@\n \t};\n };\n \n-&i2c3 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c3_pins>;\n-\tclock-frequency = <400000>;\n-};\n-\n-&mcspi1 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mcspi1_pins>;\n-};\n-\n-&mcspi2 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&mcspi2_pins>;\n-};\n-\n-&uart1 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart1_pins>;\n-\tinterrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t      <&dra7_pmx_core 0x3e0>;\n-};\n-\n-&uart2 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart2_pins>;\n-};\n-\n-&uart3 {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&uart3_pins>;\n-};\n-\n &mmc1 {\n \tstatus = \"okay\";\n \tvmmc-supply = <&evm_3v3_sd>;\n-\tvmmc_aux-supply = <&ldo1_reg>;\n+\tvqmmc-supply = <&ldo1_reg>;\n \tbus-width = <4>;\n \t/*\n \t * SDCD signal is not being used here - using the fact that GPIO mode\n \t * is always hardwired.\n \t */\n \tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50-rev11\", \"sdr104-rev11\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;\n+\tpinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;\n+\tpinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n };\n \n &mmc2 {\n \tstatus = \"okay\";\n-\tvmmc-supply = <&evm_3v3_sw>;\n+\tvmmc-supply = <&evm_1v8_sw>;\n \tbus-width = <8>;\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v-rev11\", \"ddr_1_8v\", \"hs200_1_8v-rev11\", \"hs200_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;\n+\tpinctrl-3 = <&mmc2_pins_ddr_rev20>;\n+\tpinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;\n+\tpinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;\n };\n \n &cpu0 {\n \tcpu0-supply = <&smps123_reg>;\n };\n \n-&qspi {\n-\tstatus = \"okay\";\n-\n-\tspi-max-frequency = <76800000>;\n-\tm25p80@0 {\n-\t\tcompatible = \"s25fl256s1\", \"spi-flash\";\n-\t\tspi-max-frequency = <76800000>;\n-\t\treg = <0>;\n-\t\tspi-tx-bus-width = <1>;\n-\t\tspi-rx-bus-width = <4>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\n-\t\t/* MTD partition table.\n-\t\t * The ROM checks the first four physical blocks\n-\t\t * for a valid file to boot and the flash here is\n-\t\t * 64KiB block size.\n-\t\t */\n-\t\tpartition@0 {\n-\t\t\tlabel = \"QSPI.SPL\";\n-\t\t\treg = <0x00000000 0x000010000>;\n-\t\t};\n-\t\tpartition@1 {\n-\t\t\tlabel = \"QSPI.SPL.backup1\";\n-\t\t\treg = <0x00010000 0x00010000>;\n-\t\t};\n-\t\tpartition@2 {\n-\t\t\tlabel = \"QSPI.SPL.backup2\";\n-\t\t\treg = <0x00020000 0x00010000>;\n-\t\t};\n-\t\tpartition@3 {\n-\t\t\tlabel = \"QSPI.SPL.backup3\";\n-\t\t\treg = <0x00030000 0x00010000>;\n-\t\t};\n-\t\tpartition@4 {\n-\t\t\tlabel = \"QSPI.u-boot\";\n-\t\t\treg = <0x00040000 0x00100000>;\n-\t\t};\n-\t\tpartition@5 {\n-\t\t\tlabel = \"QSPI.u-boot-spl-os\";\n-\t\t\treg = <0x00140000 0x00080000>;\n-\t\t};\n-\t\tpartition@6 {\n-\t\t\tlabel = \"QSPI.u-boot-env\";\n-\t\t\treg = <0x001c0000 0x00010000>;\n-\t\t};\n-\t\tpartition@7 {\n-\t\t\tlabel = \"QSPI.u-boot-env.backup1\";\n-\t\t\treg = <0x001d0000 0x0010000>;\n-\t\t};\n-\t\tpartition@8 {\n-\t\t\tlabel = \"QSPI.kernel\";\n-\t\t\treg = <0x001e0000 0x0800000>;\n-\t\t};\n-\t\tpartition@9 {\n-\t\t\tlabel = \"QSPI.file-system\";\n-\t\t\treg = <0x009e0000 0x01620000>;\n-\t\t};\n-\t};\n-};\n-\n-&omap_dwc3_1 {\n-\textcon = <&extcon_usb1>;\n-};\n-\n &omap_dwc3_2 {\n \textcon = <&extcon_usb2>;\n };\n \n-&usb1 {\n-\tdr_mode = \"peripheral\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&usb1_pins>;\n-};\n-\n-&usb2 {\n-\tdr_mode = \"host\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&usb2_pins>;\n-};\n-\n &elm {\n \tstatus = \"okay\";\n };\n \n &gpmc {\n-\tstatus = \"okay\";\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&nand_flash_x16>;\n+\t/*\n+\t* For the existing IOdelay configuration via U-Boot we don't\n+\t* support NAND on dra7-evm. Keep it disabled. Enabling it\n+\t* requires a different configuration by U-Boot.\n+\t*/\n+\tstatus = \"disabled\";\n \tranges = <0 0 0x08000000 0x01000000>;\t/* minimum GPMC partition = 16MB */\n \tnand@0,0 {\n \t\tcompatible = \"ti,omap2-nand\";\n@@ -764,6 +387,7 @@\n \t\tinterrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */\n \t\t\t     <1 IRQ_TYPE_NONE>; /* termcount */\n \t\trb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */\n+\t\tti,nand-xfer-type = \"prefetch-dma\";\n \t\tti,nand-ecc-opt = \"bch8\";\n \t\tti,elm-id = <&elm>;\n \t\tnand-bus-width = <16>;\n@@ -851,9 +475,6 @@\n \n &mac {\n \tstatus = \"okay\";\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&cpsw_default>;\n-\tpinctrl-1 = <&cpsw_sleep>;\n \tdual_emac;\n };\n \n@@ -869,12 +490,6 @@\n \tdual_emac_res_vlan = <2>;\n };\n \n-&davinci_mdio {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&davinci_mdio_default>;\n-\tpinctrl-1 = <&davinci_mdio_sleep>;\n-};\n-\n &dcan1 {\n \tstatus = \"ok\";\n \tpinctrl-names = \"default\", \"sleep\", \"active\";\n@@ -883,63 +498,6 @@\n \tpinctrl-2 = <&dcan1_pins_default>;\n };\n \n-&atl {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&atl_pins>;\n-\n-\tassigned-clocks = <&abe_dpll_sys_clk_mux>,\n-\t\t\t  <&atl_gfclk_mux>,\n-\t\t\t  <&dpll_abe_ck>,\n-\t\t\t  <&dpll_abe_m2x2_ck>,\n-\t\t\t  <&atl_clkin2_ck>;\n-\tassigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;\n-\tassigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;\n-\n+&pcie1_rc {\n \tstatus = \"okay\";\n-\n-\tatl2 {\n-\t\tbws = <DRA7_ATL_WS_MCASP2_FSX>;\n-\t\taws = <DRA7_ATL_WS_MCASP3_FSX>;\n-\t};\n-};\n-\n-&mcasp3 {\n-\t#sound-dai-cells = <0>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&mcasp3_pins>;\n-\tpinctrl-1 = <&mcasp3_sleep_pins>;\n-\n-\tassigned-clocks = <&mcasp3_ahclkx_mux>;\n-\tassigned-clock-parents = <&atl_clkin2_ck>;\n-\n-\tstatus = \"okay\";\n-\n-\top-mode = <0>;          /* MCASP_IIS_MODE */\n-\ttdm-slots = <2>;\n-\t/* 4 serializer */\n-\tserial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */\n-\t\t1 2 0 0\n-\t>;\n-\ttx-num-evt = <32>;\n-\trx-num-evt = <32>;\n-};\n-\n-&mailbox5 {\n-\tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n-\t\tstatus = \"okay\";\n-\t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&mailbox6 {\n-\tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n-\t\tstatus = \"okay\";\n-\t};\n-\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n-\t\tstatus = \"okay\";\n-\t};\n };\ndiff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi\nindex 5570e30eb3..02a136a466 100644\n--- a/arch/arm/dts/dra7.dtsi\n+++ b/arch/arm/dts/dra7.dtsi\n@@ -18,6 +18,7 @@\n \n \tcompatible = \"ti,dra7xx\";\n \tinterrupt-parent = <&crossbar_mpu>;\n+\tchosen { };\n \n \taliases {\n \t\ti2c0 = &i2c1;\n@@ -56,7 +57,7 @@\n \t\tinterrupt-controller;\n \t\t#interrupt-cells = <3>;\n \t\treg = <0x0 0x48211000 0x0 0x1000>,\n-\t\t      <0x0 0x48212000 0x0 0x1000>,\n+\t\t      <0x0 0x48212000 0x0 0x2000>,\n \t\t      <0x0 0x48214000 0x0 0x2000>,\n \t\t      <0x0 0x48216000 0x0 0x2000>;\n \t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;\n@@ -80,11 +81,7 @@\n \t\t\tcompatible = \"arm,cortex-a15\";\n \t\t\treg = <0>;\n \n-\t\t\toperating-points = <\n-\t\t\t\t/* kHz    uV */\n-\t\t\t\t1000000\t1060000\n-\t\t\t\t1176000\t1160000\n-\t\t\t\t>;\n+\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n \n \t\t\tclocks = <&dpll_mpu_ck>;\n \t\t\tclock-names = \"cpu\";\n@@ -98,6 +95,24 @@\n \t\t};\n \t};\n \n+\tcpu0_opp_table: opp-table {\n+\t\tcompatible = \"operating-points-v2-ti-cpu\";\n+\t\tsyscon = <&scm_wkup>;\n+\n+\t\topp_nom-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt = <1060000 850000 1150000>;\n+\t\t\topp-supported-hw = <0xFF 0x01>;\n+\t\t\topp-suspend;\n+\t\t};\n+\n+\t\topp_od-1176000000 {\n+\t\t\topp-hz = /bits/ 64 <1176000000>;\n+\t\t\topp-microvolt = <1160000 885000 1160000>;\n+\t\t\topp-supported-hw = <0xFF 0x02>;\n+\t\t};\n+\t};\n+\n \t/*\n \t * The soc node represents the soc top level view. It is used for IPs\n \t * that are not memory mapped in the MPU view or for the MPU itself.\n@@ -171,6 +186,7 @@\n \t\t\t\t\treg = <0x1400 0x0468>;\n \t\t\t\t\t#address-cells = <1>;\n \t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t#pinctrl-cells = <1>;\n \t\t\t\t\t#interrupt-cells = <1>;\n \t\t\t\t\tinterrupt-controller;\n \t\t\t\t\tpinctrl-single,register-width = <32>;\n@@ -180,6 +196,7 @@\n \t\t\t\tscm_conf1: scm_conf@1c04 {\n \t\t\t\t\tcompatible = \"syscon\";\n \t\t\t\t\treg = <0x1c04 0x0020>;\n+\t\t\t\t\t#syscon-cells = <2>;\n \t\t\t\t};\n \n \t\t\t\tscm_conf_pcie: scm_conf@1c24 {\n@@ -271,7 +288,11 @@\n \t\t\t#address-cells = <1>;\n \t\t\tranges = <0x51000000 0x51000000 0x3000\n \t\t\t\t  0x0\t     0x20000000 0x10000000>;\n-\t\t\tpcie1: pcie@51000000 {\n+\t\t\t/**\n+\t\t\t * To enable PCI endpoint mode, disable the pcie1_rc\n+\t\t\t * node and enable pcie1_ep mode.\n+\t\t\t */\n+\t\t\tpcie1_rc: pcie@51000000 {\n \t\t\t\tcompatible = \"ti,dra7-pcie\";\n \t\t\t\treg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;\n \t\t\t\treg-names = \"rc_dbics\", \"ti_conf\", \"config\";\n@@ -281,6 +302,7 @@\n \t\t\t\tdevice_type = \"pci\";\n \t\t\t\tranges = <0x81000000 0 0          0x03000 0 0x00010000\n \t\t\t\t\t  0x82000000 0 0x20013000 0x13000 0 0xffed000>;\n+\t\t\t\tbus-range = <0x00 0xff>;\n \t\t\t\t#interrupt-cells = <1>;\n \t\t\t\tnum-lanes = <1>;\n \t\t\t\tlinux,pci-domain = <0>;\n@@ -292,12 +314,28 @@\n \t\t\t\t\t\t<0 0 0 2 &pcie1_intc 2>,\n \t\t\t\t\t\t<0 0 0 3 &pcie1_intc 3>,\n \t\t\t\t\t\t<0 0 0 4 &pcie1_intc 4>;\n+\t\t\t\tstatus = \"disabled\";\n \t\t\t\tpcie1_intc: interrupt-controller {\n \t\t\t\t\tinterrupt-controller;\n \t\t\t\t\t#address-cells = <0>;\n \t\t\t\t\t#interrupt-cells = <1>;\n \t\t\t\t};\n \t\t\t};\n+\n+\t\t\tpcie1_ep: pcie_ep@51000000 {\n+\t\t\t\tcompatible = \"ti,dra7-pcie-ep\";\n+\t\t\t\treg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;\n+\t\t\t\treg-names = \"ep_dbics\", \"ti_conf\", \"ep_dbics2\", \"addr_space\";\n+\t\t\t\tinterrupts = <0 232 0x4>;\n+\t\t\t\tnum-lanes = <1>;\n+\t\t\t\tnum-ib-windows = <4>;\n+\t\t\t\tnum-ob-windows = <16>;\n+\t\t\t\tti,hwmods = \"pcie1\";\n+\t\t\t\tphys = <&pcie1_phy>;\n+\t\t\t\tphy-names = \"pcie-phy0\";\n+\t\t\t\tti,syscon-unaligned-access = <&scm_conf1 0x14 2>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n \t\t};\n \n \t\taxi@1 {\n@@ -317,6 +355,7 @@\n \t\t\t\tdevice_type = \"pci\";\n \t\t\t\tranges = <0x81000000 0 0          0x03000 0 0x00010000\n \t\t\t\t\t  0x82000000 0 0x30013000 0x13000 0 0xffed000>;\n+\t\t\t\tbus-range = <0x00 0xff>;\n \t\t\t\t#interrupt-cells = <1>;\n \t\t\t\tnum-lanes = <1>;\n \t\t\t\tlinux,pci-domain = <1>;\n@@ -400,6 +439,14 @@\n \t\t\treg = <0x40d00000 0x100>;\n \t\t};\n \n+\t\tdra7_iodelay_core: padconf@4844a000 {\n+\t\t\tcompatible = \"ti,dra7-iodelay\";\n+\t\t\treg = <0x4844a000 0x0d1c>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\t#pinctrl-cells = <2>;\n+\t\t};\n+\n \t\tsdma: dma-controller@4a056000 {\n \t\t\tcompatible = \"ti,omap4430-sdma\";\n \t\t\treg = <0x4a056000 0x1000>;\n@@ -542,7 +589,6 @@\n \t\tuart1: serial@4806a000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x4806a000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart1\";\n \t\t\tclock-frequency = <48000000>;\n@@ -554,7 +600,6 @@\n \t\tuart2: serial@4806c000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x4806c000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart2\";\n \t\t\tclock-frequency = <48000000>;\n@@ -566,7 +611,6 @@\n \t\tuart3: serial@48020000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48020000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart3\";\n \t\t\tclock-frequency = <48000000>;\n@@ -578,7 +622,6 @@\n \t\tuart4: serial@4806e000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x4806e000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart4\";\n \t\t\tclock-frequency = <48000000>;\n@@ -590,7 +633,6 @@\n \t\tuart5: serial@48066000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48066000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart5\";\n \t\t\tclock-frequency = <48000000>;\n@@ -602,7 +644,6 @@\n \t\tuart6: serial@48068000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48068000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart6\";\n \t\t\tclock-frequency = <48000000>;\n@@ -614,7 +655,6 @@\n \t\tuart7: serial@48420000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48420000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart7\";\n \t\t\tclock-frequency = <48000000>;\n@@ -624,7 +664,6 @@\n \t\tuart8: serial@48422000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48422000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart8\";\n \t\t\tclock-frequency = <48000000>;\n@@ -634,7 +673,6 @@\n \t\tuart9: serial@48424000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x48424000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart9\";\n \t\t\tclock-frequency = <48000000>;\n@@ -644,7 +682,6 @@\n \t\tuart10: serial@4ae2b000 {\n \t\t\tcompatible = \"ti,dra742-uart\", \"ti,omap4-uart\";\n \t\t\treg = <0x4ae2b000 0x100>;\n-\t\t\treg-shift = <2>;\n \t\t\tinterrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tti,hwmods = \"uart10\";\n \t\t\tclock-frequency = <48000000>;\n@@ -1029,6 +1066,7 @@\n \t\t\tdma-names = \"tx\", \"rx\";\n \t\t\tstatus = \"disabled\";\n \t\t\tpbias-supply = <&pbias_mmc_reg>;\n+\t\t\tmax-frequency = <192000000>;\n \t\t};\n \n \t\tmmc2: mmc@480b4000 {\n@@ -1040,6 +1078,7 @@\n \t\t\tdmas = <&sdma_xbar 47>, <&sdma_xbar 48>;\n \t\t\tdma-names = \"tx\", \"rx\";\n \t\t\tstatus = \"disabled\";\n+\t\t\tmax-frequency = <192000000>;\n \t\t};\n \n \t\tmmc3: mmc@480ad000 {\n@@ -1051,6 +1090,8 @@\n \t\t\tdmas = <&sdma_xbar 77>, <&sdma_xbar 78>;\n \t\t\tdma-names = \"tx\", \"rx\";\n \t\t\tstatus = \"disabled\";\n+\t\t\t/* Errata i887 limits max-frequency of MMC3 to 64 MHz */\n+\t\t\tmax-frequency = <64000000>;\n \t\t};\n \n \t\tmmc4: mmc@480d1000 {\n@@ -1062,6 +1103,7 @@\n \t\t\tdmas = <&sdma_xbar 57>, <&sdma_xbar 58>;\n \t\t\tdma-names = \"tx\", \"rx\";\n \t\t\tstatus = \"disabled\";\n+\t\t\tmax-frequency = <192000000>;\n \t\t};\n \n \t\tmmu0_dsp1: mmu@40d01000 {\n@@ -1386,6 +1428,7 @@\n \t\t\tphy-names = \"sata-phy\";\n \t\t\tclocks = <&sata_ref_clk>;\n \t\t\tti,hwmods = \"sata\";\n+\t\t\tports-implemented = <0x1>;\n \t\t};\n \n \t\trtc: rtc@48838000 {\n@@ -1716,13 +1759,11 @@\n \t\t\tcpdma_channels = <8>;\n \t\t\tale_entries = <1024>;\n \t\t\tbd_ram_size = <0x2000>;\n-\t\t\tno_bd_ram = <0>;\n \t\t\tmac_control = <0x20>;\n \t\t\tslaves = <2>;\n \t\t\tactive_slave = <0>;\n \t\t\tcpts_clock_mult = <0x784CFE14>;\n \t\t\tcpts_clock_shift = <29>;\n-\t\t\tsyscon = <&scm_conf>;\n \t\t\treg = <0x48484000 0x1000\n \t\t\t       0x48485200 0x2E00>;\n \t\t\t#address-cells = <1>;\n@@ -1748,6 +1789,7 @@\n \t\t\t\t     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t\t     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tranges;\n+\t\t\tsyscon = <&scm_conf>;\n \t\t\tstatus = \"disabled\";\n \n \t\t\tdavinci_mdio: mdio@48485000 {\n@@ -1990,6 +2032,27 @@\n \n &cpu_thermal {\n \tpolling-delay = <500>; /* milliseconds */\n+\tcoefficients = <0 2000>;\n+};\n+\n+&gpu_thermal {\n+\tcoefficients = <0 2000>;\n+};\n+\n+&core_thermal {\n+\tcoefficients = <0 2000>;\n+};\n+\n+&dspeve_thermal {\n+\tcoefficients = <0 2000>;\n+};\n+\n+&iva_thermal {\n+\tcoefficients = <0 2000>;\n+};\n+\n+&cpu_crit {\n+\ttemperature = <120000>; /* milli Celsius */\n };\n \n /include/ \"dra7xx-clocks.dtsi\"\ndiff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts\nindex 875116c67f..41c9132eb5 100644\n--- a/arch/arm/dts/dra71-evm.dts\n+++ b/arch/arm/dts/dra71-evm.dts\n@@ -7,6 +7,7 @@\n  */\n \n #include \"dra72-evm-common.dtsi\"\n+#include \"dra72x-mmc-iodelay.dtsi\"\n #include <dt-bindings/net/ti-dp83867.h>\n \n / {\n@@ -32,6 +33,16 @@\n \t\t\t  3000000 0x1>;\n \t};\n \n+\tevm_1v8_sw: fixedregulator-evm_1v8 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"evm_1v8\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tvin-supply = <&lp8732_buck0_reg>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n \tpoweroff: gpio-poweroff {\n \t\tcompatible = \"gpio-poweroff\";\n \t\tgpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;\n@@ -138,6 +149,11 @@\n \t};\n };\n \n+&pcf_lcd {\n+\tinterrupt-parent = <&gpio7>;\n+\tinterrupts = <31 IRQ_TYPE_EDGE_FALLING>;\n+};\n+\n &pcf_gpio_21 {\n \tinterrupt-parent = <&gpio7>;\n \tinterrupts = <31 IRQ_TYPE_EDGE_FALLING>;\n@@ -157,7 +173,24 @@\n };\n \n &mmc1 {\n-\tvmmc_aux-supply = <&vpo_sd_1v8_3v3>;\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n+\tvqmmc-supply = <&vpo_sd_1v8_3v3>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\", \"hs200_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;\n+\tpinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;\n+\tvmmc-supply = <&evm_1v8_sw>;\n };\n \n &mac {\n@@ -168,13 +201,13 @@\n };\n \n &cpsw_emac0 {\n-\tphy-handle = <&dp83867_0>;\n+\tphy_id = <&davinci_mdio>, <2>;\n \tphy-mode = \"rgmii-id\";\n \tdual_emac_res_vlan = <1>;\n };\n \n &cpsw_emac1 {\n-\tphy-handle = <&dp83867_1>;\n+\tphy_id = <&davinci_mdio>, <3>;\n \tphy-mode = \"rgmii-id\";\n \tdual_emac_res_vlan = <2>;\n };\n@@ -185,7 +218,8 @@\n \t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;\n \t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n \t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n-\t\tti,impedance-control = <0x1f>;\n+\t\tti,min-output-impedance;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n \t};\n \n \tdp83867_1: ethernet-phy@3 {\n@@ -193,7 +227,8 @@\n \t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;\n \t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n \t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n-\t\tti,impedance-control = <0x1f>;\n+\t\tti,min-output-impedance;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n \t};\n };\n \ndiff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi\nindex c83f87fa79..2e485a13df 100644\n--- a/arch/arm/dts/dra72-evm-common.dtsi\n+++ b/arch/arm/dts/dra72-evm-common.dtsi\n@@ -20,7 +20,6 @@\n \n \tchosen {\n \t\tstdout-path = &uart1;\n-\t\ttick-timer = &timer2;\n \t};\n \n \tevm_12v0: fixedregulator-evm12v0 {\n@@ -221,9 +220,17 @@\n \tstatus = \"okay\";\n \tclock-frequency = <400000>;\n \n+\tpcf_lcd: gpio@20 {\n+\t\tcompatible = \"nxp,pcf8575\";\n+\t\treg = <0x20>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t};\n+\n \tpcf_gpio_21: gpio@21 {\n \t\tcompatible = \"ti,pcf8575\", \"nxp,pcf8575\";\n-\t\tu-boot,i2c-offset-len = <0>;\n \t\treg = <0x21>;\n \t\tlines-initial-states = <0x1408>;\n \t\tgpio-controller;\n@@ -254,7 +261,6 @@\n \n \tpcf_hdmi: pcf8575@26 {\n \t\tcompatible = \"ti,pcf8575\", \"nxp,pcf8575\";\n-\t\tu-boot,i2c-offset-len = <0>;\n \t\treg = <0x26>;\n \t\tgpio-controller;\n \t\t#gpio-cells = <2>;\n@@ -287,7 +293,12 @@\n };\n \n &gpmc {\n-\tstatus = \"okay\";\n+\t/*\n+\t * For the existing IOdelay configuration via U-Boot we don't\n+\t * support NAND on dra72-evm. Keep it disabled. Enabling it\n+\t * requires a different configuration by U-Boot.\n+\t */\n+\tstatus = \"disabled\";\n \tranges = <0 0 0x08000000 0x01000000>;\t/* minimum GPMC partition = 16MB */\n \tnand@0,0 {\n \t\t/* To use NAND, DIP switch SW5 must be set like so:\n@@ -300,6 +311,7 @@\n \t\tinterrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */\n \t\t\t     <1 IRQ_TYPE_NONE>;\t/* termcount */\n \t\trb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */\n+\t\tti,nand-xfer-type = \"prefetch-dma\";\n \t\tti,nand-ecc-opt = \"bch8\";\n \t\tti,elm-id = <&elm>;\n \t\tnand-bus-width = <16>;\n@@ -381,7 +393,8 @@\n };\n \n &usb1 {\n-\tdr_mode = \"peripheral\";\n+\tdr_mode = \"otg\";\n+\textcon = <&extcon_usb1>;\n };\n \n &usb2 {\n@@ -407,8 +420,6 @@\n \tstatus = \"okay\";\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&mmc2_pins_default>;\n-\n-\tvmmc-supply = <&evm_3v3_sw>;\n \tbus-width = <8>;\n \tti,non-removable;\n \tmax-frequency = <192000000>;\n@@ -431,7 +442,7 @@\n \n \tspi-max-frequency = <76800000>;\n \tm25p80@0 {\n-\t\tcompatible = \"s25fl256s1\", \"spi-flash\";\n+\t\tcompatible = \"s25fl256s1\";\n \t\tspi-max-frequency = <76800000>;\n \t\treg = <0>;\n \t\tspi-tx-bus-width = <1>;\n@@ -552,3 +563,7 @@\n \t\tstatus = \"okay\";\n \t};\n };\n+\n+&pcie1_rc {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts\nindex bc814f1b4c..bf588d0072 100644\n--- a/arch/arm/dts/dra72-evm-revc.dts\n+++ b/arch/arm/dts/dra72-evm-revc.dts\n@@ -6,6 +6,7 @@\n  * published by the Free Software Foundation.\n  */\n #include \"dra72-evm-common.dtsi\"\n+#include \"dra72x-mmc-iodelay.dtsi\"\n #include <dt-bindings/net/ti-dp83867.h>\n \n / {\n@@ -15,6 +16,16 @@\n \t\tdevice_type = \"memory\";\n \t\treg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */\n \t};\n+\n+\tevm_1v8_sw: fixedregulator-evm_1v8 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"evm_1v8\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tvin-supply = <&smps4_reg>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n };\n \n &i2c1 {\n@@ -50,13 +61,13 @@\n };\n \n &cpsw_emac0 {\n-\tphy-handle = <&dp83867_0>;\n+\tphy_id = <&davinci_mdio>, <2>;\n \tphy-mode = \"rgmii-id\";\n \tdual_emac_res_vlan = <1>;\n };\n \n &cpsw_emac1 {\n-\tphy-handle = <&dp83867_1>;\n+\tphy_id = <&davinci_mdio>, <3>;\n \tphy-mode = \"rgmii-id\";\n \tdual_emac_res_vlan = <2>;\n };\n@@ -68,6 +79,9 @@\n \t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n \t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n \t\tti,min-output-impedance;\n+\t\tinterrupt-parent = <&gpio6>;\n+\t\tinterrupts = <16 IRQ_TYPE_EDGE_FALLING>;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n \t};\n \n \tdp83867_1: ethernet-phy@3 {\n@@ -76,5 +90,29 @@\n \t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n \t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n \t\tti,min-output-impedance;\n+\t\tinterrupt-parent = <&gpio6>;\n+\t\tinterrupts = <16 IRQ_TYPE_EDGE_FALLING>;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n \t};\n };\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;\n+\tvqmmc-supply = <&ldo1_reg>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\", \"hs200_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;\n+\tpinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;\n+\tvmmc-supply = <&evm_1v8_sw>;\n+};\ndiff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi\nindex ee6dac44ed..57bfe5caf5 100644\n--- a/arch/arm/dts/dra72-evm-tps65917.dtsi\n+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi\n@@ -132,3 +132,19 @@\n \t\tti,palmas-long-press-seconds = <6>;\n \t};\n };\n+\n+&usb2_phy1 {\n+\tphy-supply = <&ldo4_reg>;\n+};\n+\n+&usb2_phy2 {\n+\tphy-supply = <&ldo4_reg>;\n+};\n+\n+&dss {\n+\tvdda_video-supply = <&ldo5_reg>;\n+};\n+\n+&mmc1 {\n+\tvqmmc-supply = <&ldo1_reg>;\n+};\ndiff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts\nindex cd9c4ff126..c572693b16 100644\n--- a/arch/arm/dts/dra72-evm.dts\n+++ b/arch/arm/dts/dra72-evm.dts\n@@ -6,6 +6,7 @@\n  * published by the Free Software Foundation.\n  */\n #include \"dra72-evm-common.dtsi\"\n+#include \"dra72x-mmc-iodelay.dtsi\"\n / {\n \tmodel = \"TI DRA722\";\n \n@@ -13,6 +14,16 @@\n \t\tdevice_type = \"memory\";\n \t\treg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */\n \t};\n+\n+\tevm_1v8_sw: fixedregulator-evm_1v8 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"evm_1v8\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tvin-supply = <&smps4_reg>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n };\n \n &i2c1 {\n@@ -43,3 +54,24 @@\n \tphy_id = <&davinci_mdio>, <3>;\n \tphy-mode = \"rgmii\";\n };\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50\", \"sdr104\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_hs>;\n+\tpinctrl-2 = <&mmc1_pins_sdr12>;\n+\tpinctrl-3 = <&mmc1_pins_sdr25>;\n+\tpinctrl-4 = <&mmc1_pins_sdr50>;\n+\tpinctrl-5 = <&mmc1_pins_ddr50_rev10>;\n+\tpinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;\n+\tvqmmc-supply = <&ldo1_reg>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\", \"hs\", \"ddr_1_8v\", \"hs200_1_8v\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+\tpinctrl-1 = <&mmc2_pins_hs>;\n+\tpinctrl-2 = <&mmc2_pins_ddr_rev10>;\n+\tpinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;\n+\tvmmc-supply = <&evm_1v8_sw>;\n+};\ndiff --git a/arch/arm/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/dts/dra72x-mmc-iodelay.dtsi\nnew file mode 100644\nindex 0000000000..088013c6dc\n--- /dev/null\n+++ b/arch/arm/dts/dra72x-mmc-iodelay.dtsi\n@@ -0,0 +1,350 @@\n+/*\n+ * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.\n+ *\n+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation version 2.\n+ *\n+ * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n+ * kind, whether express or implied; without even the implied warranty\n+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+/*\n+ * Rules for modifying this file:\n+ * a) Update of this file should typically correspond to a datamanual revision.\n+ *    Datamanual revision that was used should be updated in comment below.\n+ *    If there is no update to datamanual, do not update the values. If you\n+ *    need to use values different from that recommended by the datamanual\n+ *    for your design, then you should consider adding values to the device-\n+ *    -tree file for your board directly.\n+ * b) We keep the mode names as close to the datamanual as possible. So\n+ *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,\n+ *    we follow that in code too.\n+ * c) If the values change between multiple revisions of silicon, we add\n+ *    a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,\n+ *    'rev20' for PG 2.0 and so on.\n+ * d) The node name and node label should be the exact same string. This is\n+ *    to curb naming creativity and achieve consistency.\n+ * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and\n+ *    'dra72_' tag to entries. Both the new and old entries should gain a tag.\n+ *\n+ * Datamanual Revisions:\n+ *\n+ * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017\n+ * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017\n+ * DRA71x : SPRS960B, Revised February 2017\n+ */\n+\n+&dra7_pmx_core {\n+\tmmc1_pins_default: mmc1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr12: mmc1_pins_sdr12 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_hs: mmc1_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr25: mmc1_pins_sdr25 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr50: mmc1_pins_sdr50 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_clk.mmc1_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_cmd.mmc1_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_dat0.mmc1_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_dat1.mmc1_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_dat2.mmc1_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)\t/* mmc1_dat3.mmc1_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr104: mmc1_pins_sdr104 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_default: mmc2_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_hs: mmc2_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a22.mmc2_dat7 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_cs1.mmc2_cmd */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_hs200: mmc2_pins_hs200 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+};\n+\n+&dra7_iodelay_core {\n+\n+\t/* Corresponds to MMC1_MANUAL1 in datamanual */\n+\tmmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x618 A_DELAY_PS(588) G_DELAY_PS(0)\t/* CFG_MMC1_CLK_IN */\n+\t\t\t0x624 A_DELAY_PS(1000) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_IN */\n+\t\t\t0x630 A_DELAY_PS(1375) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_IN */\n+\t\t\t0x63C A_DELAY_PS(1000) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_IN */\n+\t\t\t0x648 A_DELAY_PS(1000) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_IN */\n+\t\t\t0x654 A_DELAY_PS(1000) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_IN */\n+\t\t\t0x620 A_DELAY_PS(1230) G_DELAY_PS(0)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x62C A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x638 A_DELAY_PS(56) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x644 A_DELAY_PS(76) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x650 A_DELAY_PS(91) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x65C A_DELAY_PS(99) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t\t0x628 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x640 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x64C A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x658 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC1_MANUAL2 in datamanual */\n+\tmmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x620 A_DELAY_PS(560) G_DELAY_PS(365)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x62c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x638 A_DELAY_PS(29) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x644 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x650 A_DELAY_PS(47) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x65c A_DELAY_PS(30) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t\t0x628 A_DELAY_PS(125) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x634 A_DELAY_PS(43) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x640 A_DELAY_PS(433) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x64c A_DELAY_PS(287) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x658 A_DELAY_PS(351) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC1_MANUAL2 in datamanual */\n+\tmmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x620 A_DELAY_PS(520) G_DELAY_PS(320)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x62c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x638 A_DELAY_PS(40) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x644 A_DELAY_PS(83) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x650 A_DELAY_PS(98) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x65c A_DELAY_PS(106) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t\t0x628 A_DELAY_PS(51) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x640 A_DELAY_PS(363) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x64c A_DELAY_PS(199) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x658 A_DELAY_PS(273) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC2_MANUAL1 in datamanual */\n+\tmmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x18c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_IN */\n+\t\t\t0x1a4 A_DELAY_PS(119) G_DELAY_PS(0)\t/* CFG_GPMC_A20_IN */\n+\t\t\t0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A21_IN */\n+\t\t\t0x1bc A_DELAY_PS(18) G_DELAY_PS(0)\t/* CFG_GPMC_A22_IN */\n+\t\t\t0x1c8 A_DELAY_PS(894) G_DELAY_PS(0)\t/* CFG_GPMC_A23_IN */\n+\t\t\t0x1d4 A_DELAY_PS(30) G_DELAY_PS(0)\t/* CFG_GPMC_A24_IN */\n+\t\t\t0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_IN */\n+\t\t\t0x1ec A_DELAY_PS(23) G_DELAY_PS(0)\t/* CFG_GPMC_A26_IN */\n+\t\t\t0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_IN */\n+\t\t\t0x360 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_IN */\n+\t\t\t0x194 A_DELAY_PS(152) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1ac A_DELAY_PS(206) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x200 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x368 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OUT */\n+\t\t\t0x190 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1fc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x364 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OEN */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC2_MANUAL3 in datamanual */\n+\tmmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x194 A_DELAY_PS(150) G_DELAY_PS(95)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1ac A_DELAY_PS(250) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b8 A_DELAY_PS(125) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1c4 A_DELAY_PS(100) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1d0 A_DELAY_PS(870) G_DELAY_PS(415)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1dc A_DELAY_PS(30) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e8 A_DELAY_PS(200) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1f4 A_DELAY_PS(200) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x200 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x368 A_DELAY_PS(240) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OUT */\n+\t\t\t0x190 A_DELAY_PS(695) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x1a8 A_DELAY_PS(924) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1b4 A_DELAY_PS(719) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1c0 A_DELAY_PS(824) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1d8 A_DELAY_PS(877) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1e4 A_DELAY_PS(446) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1f0 A_DELAY_PS(847) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1fc A_DELAY_PS(586) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x364 A_DELAY_PS(1039) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OEN */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC2_MANUAL3 in datamanual */\n+\tmmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x194 A_DELAY_PS(285) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1ac A_DELAY_PS(189) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b8 A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1c4 A_DELAY_PS(0) G_DELAY_PS(70)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1d0 A_DELAY_PS(730) G_DELAY_PS(360)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1f4 A_DELAY_PS(70) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x200 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x368 A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_CS1_OUT */\n+\t\t\t0x190 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x1a8 A_DELAY_PS(231) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1b4 A_DELAY_PS(39) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1c0 A_DELAY_PS(91) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1d8 A_DELAY_PS(176) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1f0 A_DELAY_PS(101) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1fc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x364 A_DELAY_PS(360) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OEN */\n+\t\t>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi\nindex eaca143faa..67107605fb 100644\n--- a/arch/arm/dts/dra72x.dtsi\n+++ b/arch/arm/dts/dra72x.dtsi\n@@ -12,22 +12,6 @@\n / {\n \tcompatible = \"ti,dra722\", \"ti,dra72\", \"ti,dra7\";\n \n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcpu0: cpu@0 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a15\";\n-\t\t\treg = <0>;\n-\n-\t\t\t/* cooling options */\n-\t\t\tcooling-min-level = <0>;\n-\t\t\tcooling-max-level = <2>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n-\t};\n-\n \tpmu {\n \t\tcompatible = \"arm,cortex-a15-pmu\";\n \t\tinterrupt-parent = <&wakeupgen>;\n@@ -45,3 +29,24 @@\n \t\t <&dss_video1_clk>;\n \tclock-names = \"fck\", \"video1_clk\";\n };\n+\n+&mailbox5 {\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tti,mbox-tx = <6 2 2>;\n+\t\tti,mbox-rx = <4 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tti,mbox-tx = <5 2 2>;\n+\t\tti,mbox-rx = <1 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&mailbox6 {\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tti,mbox-tx = <6 2 2>;\n+\t\tti,mbox-rx = <4 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/dts/dra74x-mmc-iodelay.dtsi\nnew file mode 100644\nindex 0000000000..28ebb4eb88\n--- /dev/null\n+++ b/arch/arm/dts/dra74x-mmc-iodelay.dtsi\n@@ -0,0 +1,647 @@\n+/*\n+ * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.\n+ *\n+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation version 2.\n+ *\n+ * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n+ * kind, whether express or implied; without even the implied warranty\n+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+/*\n+ * Rules for modifying this file:\n+ * a) Update of this file should typically correspond to a datamanual revision.\n+ *    Datamanual revision that was used should be updated in comment below.\n+ *    If there is no update to datamanual, do not update the values. If you\n+ *    need to use values different from that recommended by the datamanual\n+ *    for your design, then you should consider adding values to the device-\n+ *    -tree file for your board directly.\n+ * b) We keep the mode names as close to the datamanual as possible. So\n+ *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,\n+ *    we follow that in code too.\n+ * c) If the values change between multiple revisions of silicon, we add\n+ *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,\n+ *    'rev20' for PG 2.0 and so on.\n+ * d) The node name and node label should be the exact same string. This is\n+ *    to curb naming creativity and achieve consistency.\n+ *\n+ * Datamanual Revisions:\n+ *\n+ * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016\n+ * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016\n+ *\n+ */\n+\n+&dra7_pmx_core {\n+\tmmc1_pins_default: mmc1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr12: mmc1_pins_sdr12 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_hs: mmc1_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr25: mmc1_pins_sdr25 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr50: mmc1_pins_sdr50 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_ddr50: mmc1_pins_ddr50 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr104: mmc1_pins_sdr104 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_default: mmc2_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_hs: mmc2_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_hs200: mmc2_pins_hs200 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+\n+\tmmc4_pins_default: mmc4_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc4_pins_hs: mmc4_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc3_pins_default: mmc3_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc3_pins_hs: mmc3_pins_hs {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc3_pins_sdr12: mmc3_pins_sdr12 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc3_pins_sdr25: mmc3_pins_sdr25 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc3_pins_sdr50: mmc3_pins_sdr50 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc4_pins_sdr12: mmc4_pins_sdr12 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc4_pins_sdr25: mmc4_pins_sdr25 {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */\n+\t\t>;\n+\t};\n+};\n+\n+&dra7_iodelay_core {\n+\n+\t/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */\n+\tmmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x618 A_DELAY_PS(572) G_DELAY_PS(540)\t/* CFG_MMC1_CLK_IN */\n+\t\t\t0x620 A_DELAY_PS(1525) G_DELAY_PS(0)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x624 A_DELAY_PS(0) G_DELAY_PS(600)\t/* CFG_MMC1_CMD_IN */\n+\t\t\t0x628 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x62c A_DELAY_PS(55) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x630 A_DELAY_PS(403) G_DELAY_PS(120)\t/* CFG_MMC1_DAT0_IN */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x638 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x63c A_DELAY_PS(23) G_DELAY_PS(60)\t/* CFG_MMC1_DAT1_IN */\n+\t\t\t0x640 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x644 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x648 A_DELAY_PS(25) G_DELAY_PS(60)\t/* CFG_MMC1_DAT2_IN */\n+\t\t\t0x64c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x650 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x654 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_IN */\n+\t\t\t0x658 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t\t0x65c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC1_DDR_MANUAL1 in datamanual */\n+\tmmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x618 A_DELAY_PS(1076) G_DELAY_PS(330)\t/* CFG_MMC1_CLK_IN */\n+\t\t\t0x620 A_DELAY_PS(1271) G_DELAY_PS(0)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x624 A_DELAY_PS(722) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_IN */\n+\t\t\t0x628 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x62C A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x630 A_DELAY_PS(751) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_IN */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x638 A_DELAY_PS(20) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x63C A_DELAY_PS(256) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_IN */\n+\t\t\t0x640 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x644 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x648 A_DELAY_PS(263) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_IN */\n+\t\t\t0x64C A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x650 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x654 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_IN */\n+\t\t\t0x658 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t\t0x65C A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */\n+\tmmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x620 A_DELAY_PS(1063) G_DELAY_PS(17)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x628 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x62c A_DELAY_PS(23) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x638 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x640 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x644 A_DELAY_PS(2) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x64c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x650 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x658 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t\t0x65c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */\n+\tmmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x620 A_DELAY_PS(600) G_DELAY_PS(400)\t/* CFG_MMC1_CLK_OUT */\n+\t\t\t0x628 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OEN */\n+\t\t\t0x62c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_CMD_OUT */\n+\t\t\t0x634 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OEN */\n+\t\t\t0x638 A_DELAY_PS(30) G_DELAY_PS(0)\t/* CFG_MMC1_DAT0_OUT */\n+\t\t\t0x640 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OEN */\n+\t\t\t0x644 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT1_OUT */\n+\t\t\t0x64c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OEN */\n+\t\t\t0x650 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT2_OUT */\n+\t\t\t0x658 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OEN */\n+\t\t\t0x65c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC1_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */\n+\tmmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x190 A_DELAY_PS(621) G_DELAY_PS(600)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x194 A_DELAY_PS(300) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1a8 A_DELAY_PS(739) G_DELAY_PS(600)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1ac A_DELAY_PS(240) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b4 A_DELAY_PS(812) G_DELAY_PS(600)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1b8 A_DELAY_PS(240) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1c0 A_DELAY_PS(954) G_DELAY_PS(600)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1c4 A_DELAY_PS(60)  G_DELAY_PS(0)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1d8 A_DELAY_PS(935) G_DELAY_PS(600)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e4 A_DELAY_PS(525) G_DELAY_PS(600)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1e8 A_DELAY_PS(120) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1f0 A_DELAY_PS(767) G_DELAY_PS(600)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1f4 A_DELAY_PS(225) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x1fc A_DELAY_PS(565) G_DELAY_PS(600)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x200 A_DELAY_PS(60) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x364 A_DELAY_PS(969) G_DELAY_PS(600)\t/* CFG_GPMC_CS1_OEN */\n+\t\t\t0x368 A_DELAY_PS(180) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OUT */\n+\t      >;\n+\t};\n+\n+\t/* Corresponds to MMC2_HS200_MANUAL1 in datamanual */\n+\tmmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x190 A_DELAY_PS(274) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */\n+\t\t\t0x194 A_DELAY_PS(162) G_DELAY_PS(0)       /* CFG_GPMC_A19_OUT */\n+\t\t\t0x1a8 A_DELAY_PS(401) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */\n+\t\t\t0x1ac A_DELAY_PS(73) G_DELAY_PS(0)        /* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b4 A_DELAY_PS(465) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */\n+\t\t\t0x1b8 A_DELAY_PS(115) G_DELAY_PS(0)       /* CFG_GPMC_A21_OUT */\n+\t\t\t0x1c0 A_DELAY_PS(633) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */\n+\t\t\t0x1c4 A_DELAY_PS(47) G_DELAY_PS(0)        /* CFG_GPMC_A22_OUT */\n+\t\t\t0x1d0 A_DELAY_PS(935) G_DELAY_PS(280)     /* CFG_GPMC_A23_OUT */\n+\t\t\t0x1d8 A_DELAY_PS(621) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e4 A_DELAY_PS(183) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */\n+\t\t\t0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A25_OUT */\n+\t\t\t0x1f0 A_DELAY_PS(467) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */\n+\t\t\t0x1f4 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A26_OUT */\n+\t\t\t0x1fc A_DELAY_PS(262) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */\n+\t\t\t0x200 A_DELAY_PS(46) G_DELAY_PS(0)        /* CFG_GPMC_A27_OUT */\n+\t\t\t0x364 A_DELAY_PS(684) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */\n+\t\t\t0x368 A_DELAY_PS(76) G_DELAY_PS(0)        /* CFG_GPMC_CS1_OUT */\n+\t      >;\n+\t};\n+\n+\t/* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */\n+\tmmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x18c A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_A19_IN */\n+\t\t\t0x190 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x194 A_DELAY_PS(174) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1a4 A_DELAY_PS(265) G_DELAY_PS(360)\t/* CFG_GPMC_A20_IN */\n+\t\t\t0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1ac A_DELAY_PS(168) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b0 A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_A21_IN */\n+\t\t\t0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1b8 A_DELAY_PS(136) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1bc A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_A22_IN */\n+\t\t\t0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1c4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1c8 A_DELAY_PS(287) G_DELAY_PS(420)\t/* CFG_GPMC_A23_IN */\n+\t\t\t0x1d0 A_DELAY_PS(879) G_DELAY_PS(0)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1d4 A_DELAY_PS(144) G_DELAY_PS(240)\t/* CFG_GPMC_A24_IN */\n+\t\t\t0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_IN */\n+\t\t\t0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1e8 A_DELAY_PS(34) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1ec A_DELAY_PS(0) G_DELAY_PS(120)\t/* CFG_GPMC_A26_IN */\n+\t\t\t0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1f4 A_DELAY_PS(120) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x1f8 A_DELAY_PS(120) G_DELAY_PS(180)\t/* CFG_GPMC_A27_IN */\n+\t\t\t0x1fc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x200 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x360 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_IN */\n+\t\t\t0x364 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OEN */\n+\t\t\t0x368 A_DELAY_PS(11) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */\n+\tmmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x18c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_IN */\n+\t\t\t0x190 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OEN */\n+\t\t\t0x194 A_DELAY_PS(174) G_DELAY_PS(0)\t/* CFG_GPMC_A19_OUT */\n+\t\t\t0x1a4 A_DELAY_PS(274) G_DELAY_PS(240)\t/* CFG_GPMC_A20_IN */\n+\t\t\t0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OEN */\n+\t\t\t0x1ac A_DELAY_PS(168) G_DELAY_PS(0)\t/* CFG_GPMC_A20_OUT */\n+\t\t\t0x1b0 A_DELAY_PS(0) G_DELAY_PS(60)\t/* CFG_GPMC_A21_IN */\n+\t\t\t0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OEN */\n+\t\t\t0x1b8 A_DELAY_PS(136) G_DELAY_PS(0)\t/* CFG_GPMC_A21_OUT */\n+\t\t\t0x1bc A_DELAY_PS(0) G_DELAY_PS(60)\t/* CFG_GPMC_A22_IN */\n+\t\t\t0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OEN */\n+\t\t\t0x1c4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A22_OUT */\n+\t\t\t0x1c8 A_DELAY_PS(514) G_DELAY_PS(360)\t/* CFG_GPMC_A23_IN */\n+\t\t\t0x1d0 A_DELAY_PS(879) G_DELAY_PS(0)\t/* CFG_GPMC_A23_OUT */\n+\t\t\t0x1d4 A_DELAY_PS(187) G_DELAY_PS(120)\t/* CFG_GPMC_A24_IN */\n+\t\t\t0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OEN */\n+\t\t\t0x1dc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A24_OUT */\n+\t\t\t0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_IN */\n+\t\t\t0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OEN */\n+\t\t\t0x1e8 A_DELAY_PS(34) G_DELAY_PS(0)\t/* CFG_GPMC_A25_OUT */\n+\t\t\t0x1ec A_DELAY_PS(0) G_DELAY_PS(60)\t/* CFG_GPMC_A26_IN */\n+\t\t\t0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OEN */\n+\t\t\t0x1f4 A_DELAY_PS(120) G_DELAY_PS(0)\t/* CFG_GPMC_A26_OUT */\n+\t\t\t0x1f8 A_DELAY_PS(121) G_DELAY_PS(60)\t/* CFG_GPMC_A27_IN */\n+\t\t\t0x1fc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OEN */\n+\t\t\t0x200 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_A27_OUT */\n+\t\t\t0x360 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_IN */\n+\t\t\t0x364 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OEN */\n+\t\t\t0x368 A_DELAY_PS(11) G_DELAY_PS(0)\t/* CFG_GPMC_CS1_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC3_MANUAL1 in datamanual */\n+\tmmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x678 A_DELAY_PS(0) G_DELAY_PS(386)\t/* CFG_MMC3_CLK_IN */\n+\t\t\t0x680 A_DELAY_PS(605) G_DELAY_PS(0)\t/* CFG_MMC3_CLK_OUT */\n+\t\t\t0x684 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_IN */\n+\t\t\t0x688 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_OEN */\n+\t\t\t0x68c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_OUT */\n+\t\t\t0x690 A_DELAY_PS(171) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_IN */\n+\t\t\t0x694 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_OEN */\n+\t\t\t0x698 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_OUT */\n+\t\t\t0x69c A_DELAY_PS(221) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_IN */\n+\t\t\t0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_OEN */\n+\t\t\t0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_OUT */\n+\t\t\t0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_IN */\n+\t\t\t0x6ac A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_OEN */\n+\t\t\t0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_OUT */\n+\t\t\t0x6b4 A_DELAY_PS(474) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_IN */\n+\t\t\t0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_OEN */\n+\t\t\t0x6bc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC3_MANUAL1 in datamanual */\n+\tmmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x678 A_DELAY_PS(406) G_DELAY_PS(0)\t/* CFG_MMC3_CLK_IN */\n+\t\t\t0x680 A_DELAY_PS(659) G_DELAY_PS(0)\t/* CFG_MMC3_CLK_OUT */\n+\t\t\t0x684 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_IN */\n+\t\t\t0x688 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_OEN */\n+\t\t\t0x68c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_CMD_OUT */\n+\t\t\t0x690 A_DELAY_PS(130) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_IN */\n+\t\t\t0x694 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_OEN */\n+\t\t\t0x698 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT0_OUT */\n+\t\t\t0x69c A_DELAY_PS(169) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_IN */\n+\t\t\t0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_OEN */\n+\t\t\t0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT1_OUT */\n+\t\t\t0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_IN */\n+\t\t\t0x6ac A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_OEN */\n+\t\t\t0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT2_OUT */\n+\t\t\t0x6b4 A_DELAY_PS(457) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_IN */\n+\t\t\t0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_OEN */\n+\t\t\t0x6bc A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_MMC3_DAT3_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC4_DS_MANUAL1 in datamanual */\n+\tmmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x840 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_IN */\n+\t\t\t0x848 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_OUT */\n+\t\t\t0x84c A_DELAY_PS(96) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_IN */\n+\t\t\t0x850 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OEN */\n+\t\t\t0x854 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OUT */\n+\t\t\t0x870 A_DELAY_PS(582) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_IN */\n+\t\t\t0x874 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OEN */\n+\t\t\t0x878 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OUT */\n+\t\t\t0x87c A_DELAY_PS(391) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_IN */\n+\t\t\t0x880 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OEN */\n+\t\t\t0x884 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OUT */\n+\t\t\t0x888 A_DELAY_PS(561) G_DELAY_PS(0)\t/* CFG_UART2_RXD_IN */\n+\t\t\t0x88c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OEN */\n+\t\t\t0x890 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OUT */\n+\t\t\t0x894 A_DELAY_PS(588) G_DELAY_PS(0)\t/* CFG_UART2_TXD_IN */\n+\t\t\t0x898 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OEN */\n+\t\t\t0x89c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC4_DS_MANUAL1 in datamanual */\n+\tmmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x840 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_IN */\n+\t\t\t0x848 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_OUT */\n+\t\t\t0x84c A_DELAY_PS(307) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_IN */\n+\t\t\t0x850 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OEN */\n+\t\t\t0x854 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OUT */\n+\t\t\t0x870 A_DELAY_PS(785) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_IN */\n+\t\t\t0x874 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OEN */\n+\t\t\t0x878 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OUT */\n+\t\t\t0x87c A_DELAY_PS(613) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_IN */\n+\t\t\t0x880 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OEN */\n+\t\t\t0x884 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OUT */\n+\t\t\t0x888 A_DELAY_PS(683) G_DELAY_PS(0)\t/* CFG_UART2_RXD_IN */\n+\t\t\t0x88c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OEN */\n+\t\t\t0x890 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OUT */\n+\t\t\t0x894 A_DELAY_PS(835) G_DELAY_PS(0)\t/* CFG_UART2_TXD_IN */\n+\t\t\t0x898 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OEN */\n+\t\t\t0x89c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC4_MANUAL1 in datamanual */\n+\tmmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x840 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_IN */\n+\t\t\t0x848 A_DELAY_PS(2651) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_OUT */\n+\t\t\t0x84c A_DELAY_PS(1572) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_IN */\n+\t\t\t0x850 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OEN */\n+\t\t\t0x854 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OUT */\n+\t\t\t0x870 A_DELAY_PS(1913) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_IN */\n+\t\t\t0x874 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OEN */\n+\t\t\t0x878 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OUT */\n+\t\t\t0x87c A_DELAY_PS(1721) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_IN */\n+\t\t\t0x880 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OEN */\n+\t\t\t0x884 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OUT */\n+\t\t\t0x888 A_DELAY_PS(1891) G_DELAY_PS(0)\t/* CFG_UART2_RXD_IN */\n+\t\t\t0x88c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OEN */\n+\t\t\t0x890 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OUT */\n+\t\t\t0x894 A_DELAY_PS(1919) G_DELAY_PS(0)\t/* CFG_UART2_TXD_IN */\n+\t\t\t0x898 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OEN */\n+\t\t\t0x89c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OUT */\n+\t\t>;\n+\t};\n+\n+\t/* Corresponds to MMC4_MANUAL1 in datamanual */\n+\tmmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {\n+\t\tpinctrl-pin-array = <\n+\t\t\t0x840 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_IN */\n+\t\t\t0x848 A_DELAY_PS(1147) G_DELAY_PS(0)\t/* CFG_UART1_CTSN_OUT */\n+\t\t\t0x84c A_DELAY_PS(1834) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_IN */\n+\t\t\t0x850 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OEN */\n+\t\t\t0x854 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART1_RTSN_OUT */\n+\t\t\t0x870 A_DELAY_PS(2165) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_IN */\n+\t\t\t0x874 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OEN */\n+\t\t\t0x878 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_CTSN_OUT */\n+\t\t\t0x87c A_DELAY_PS(1929) G_DELAY_PS(64)\t/* CFG_UART2_RTSN_IN */\n+\t\t\t0x880 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OEN */\n+\t\t\t0x884 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RTSN_OUT */\n+\t\t\t0x888 A_DELAY_PS(1935) G_DELAY_PS(128)\t/* CFG_UART2_RXD_IN */\n+\t\t\t0x88c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OEN */\n+\t\t\t0x890 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_RXD_OUT */\n+\t\t\t0x894 A_DELAY_PS(2172) G_DELAY_PS(44)\t/* CFG_UART2_TXD_IN */\n+\t\t\t0x898 A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OEN */\n+\t\t\t0x89c A_DELAY_PS(0) G_DELAY_PS(0)\t/* CFG_UART2_TXD_OUT */\n+\t\t>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi\nindex fa995d0ca1..24e6746c5b 100644\n--- a/arch/arm/dts/dra74x.dtsi\n+++ b/arch/arm/dts/dra74x.dtsi\n@@ -13,34 +13,11 @@\n \tcompatible = \"ti,dra742\", \"ti,dra74\", \"ti,dra7\";\n \n \tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcpu0: cpu@0 {\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\tcompatible = \"arm,cortex-a15\";\n-\t\t\treg = <0>;\n-\n-\t\t\toperating-points = <\n-\t\t\t\t/* kHz    uV */\n-\t\t\t\t1000000\t1060000\n-\t\t\t\t1176000\t1160000\n-\t\t\t\t>;\n-\n-\t\t\tclocks = <&dpll_mpu_ck>;\n-\t\t\tclock-names = \"cpu\";\n-\n-\t\t\tclock-latency = <300000>; /* From omap-cpufreq driver */\n-\n-\t\t\t/* cooling options */\n-\t\t\tcooling-min-level = <0>;\n-\t\t\tcooling-max-level = <2>;\n-\t\t\t#cooling-cells = <2>; /* min followed by max */\n-\t\t};\n \t\tcpu@1 {\n \t\t\tdevice_type = \"cpu\";\n \t\t\tcompatible = \"arm,cortex-a15\";\n \t\t\treg = <1>;\n+\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n \t\t};\n \t};\n \n@@ -52,6 +29,11 @@\n \t};\n \n \tocp {\n+\t\tdsp2_system: dsp_system@41500000 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x41500000 0x100>;\n+\t\t};\n+\n \t\tomap_dwc3_4: omap_dwc3_4@48940000 {\n \t\t\tcompatible = \"ti,dwc3\";\n \t\t\tti,hwmods = \"usb_otg_ss4\";\n@@ -65,21 +47,49 @@\n \t\t\tusb4: usb@48950000 {\n \t\t\t\tcompatible = \"snps,dwc3\";\n \t\t\t\treg = <0x48950000 0x17000>;\n-\t\t\t\tinterrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\t\ttx-fifo-resize;\n+\t\t\t\tinterrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tinterrupt-names = \"peripheral\",\n+\t\t\t\t\t\t  \"host\",\n+\t\t\t\t\t\t  \"otg\";\n \t\t\t\tmaximum-speed = \"high-speed\";\n \t\t\t\tdr_mode = \"otg\";\n \t\t\t};\n \t\t};\n+\n+\t\tmmu0_dsp2: mmu@41501000 {\n+\t\t\tcompatible = \"ti,dra7-dsp-iommu\";\n+\t\t\treg = <0x41501000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tti,hwmods = \"mmu0_dsp2\";\n+\t\t\t#iommu-cells = <0>;\n+\t\t\tti,syscon-mmuconfig = <&dsp2_system 0x0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmmu1_dsp2: mmu@41502000 {\n+\t\t\tcompatible = \"ti,dra7-dsp-iommu\";\n+\t\t\treg = <0x41502000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tti,hwmods = \"mmu1_dsp2\";\n+\t\t\t#iommu-cells = <0>;\n+\t\t\tti,syscon-mmuconfig = <&dsp2_system 0x1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n \t};\n };\n \n+&cpu0_opp_table {\n+\topp-shared;\n+};\n+\n &dss {\n \treg = <0x58000000 0x80>,\n \t      <0x58004054 0x4>,\n \t      <0x58004300 0x20>,\n-\t      <0x58005054 0x4>,\n-\t      <0x58005300 0x20>;\n+\t      <0x58009054 0x4>,\n+\t      <0x58009300 0x20>;\n \treg-names = \"dss\", \"pll1_clkctrl\", \"pll1\",\n \t\t    \"pll2_clkctrl\", \"pll2\";\n \n@@ -88,3 +98,29 @@\n \t\t <&dss_video2_clk>;\n \tclock-names = \"fck\", \"video1_clk\", \"video2_clk\";\n };\n+\n+&mailbox5 {\n+\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\t\tti,mbox-tx = <6 2 2>;\n+\t\tti,mbox-rx = <4 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\t\tti,mbox-tx = <5 2 2>;\n+\t\tti,mbox-rx = <1 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&mailbox6 {\n+\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\t\tti,mbox-tx = <6 2 2>;\n+\t\tti,mbox-rx = <4 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\t\tti,mbox-tx = <5 2 2>;\n+\t\tti,mbox-rx = <1 2 2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts\nnew file mode 100644\nindex 0000000000..b024a65c6e\n--- /dev/null\n+++ b/arch/arm/dts/dra76-evm.dts\n@@ -0,0 +1,423 @@\n+/*\n+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+/dts-v1/;\n+\n+#include \"dra76x.dtsi\"\n+#include \"dra7-evm-common.dtsi\"\n+#include <dt-bindings/net/ti-dp83867.h>\n+\n+/ {\n+\tmodel = \"TI DRA762 EVM\";\n+\tcompatible = \"ti,dra76-evm\", \"ti,dra762\", \"ti,dra7\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x80000000 0x0 0x80000000>;\n+\t};\n+\n+\tvsys_12v0: fixedregulator-vsys12v0 {\n+\t\t/* main supply */\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vsys_12v0\";\n+\t\tregulator-min-microvolt = <12000000>;\n+\t\tregulator-max-microvolt = <12000000>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n+\tvsys_5v0: fixedregulator-vsys5v0 {\n+\t\t/* Output of Cntlr B of TPS43351-Q1 on dra76-evm */\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vsys_5v0\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tvin-supply = <&vsys_12v0>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n+\tvsys_3v3: fixedregulator-vsys3v3 {\n+\t\t/* Output of Cntlr A of TPS43351-Q1 on dra76-evm */\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vsys_3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tvin-supply = <&vsys_12v0>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n+\tvio_3v3: fixedregulator-vio_3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vio_3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tvin-supply = <&vsys_3v3>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n+\tvio_3v3_sd: fixedregulator-sd {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vio_3v3_sd\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tvin-supply = <&vio_3v3>;\n+\t\tenable-active-high;\n+\t\tgpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tvio_1v8: fixedregulator-vio_1v8 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vio_1v8\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tvin-supply = <&smps5_reg>;\n+\t};\n+\n+\tvtt_fixed: fixedregulator-vtt {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vtt_fixed\";\n+\t\tregulator-min-microvolt = <1350000>;\n+\t\tregulator-max-microvolt = <1350000>;\n+\t\tvin-supply = <&vsys_3v3>;\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+\n+\taic_dvdd: fixedregulator-aic_dvdd {\n+\t\t/* TPS77018DBVT */\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"aic_dvdd\";\n+\t\tvin-supply = <&vio_3v3>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t};\n+};\n+\n+&dra7_pmx_core {\n+\tmmc1_pins_default: mmc1_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)\t/* mmc1sdcd.gpio219 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_clk.clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_cmd.cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat0.dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat1.dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat2.dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc1_dat3.dat3 */\n+\t\t>;\n+\t};\n+\n+\tmmc2_pins_default: mmc2_pins_default {\n+\t\tpinctrl-single,pins = <\n+\t\t\tDRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */\n+\t\t\tDRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */\n+\t\t>;\n+\t};\n+};\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\n+\ttps65917: tps65917@58 {\n+\t\tcompatible = \"ti,tps65917\";\n+\t\treg = <0x58>;\n+\t\tti,system-power-controller;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\n+\t\ttps65917_pmic {\n+\t\t\tcompatible = \"ti,tps65917-pmic\";\n+\n+\t\t\tsmps12-in-supply = <&vsys_3v3>;\n+\t\t\tsmps3-in-supply = <&vsys_3v3>;\n+\t\t\tsmps4-in-supply = <&vsys_3v3>;\n+\t\t\tsmps5-in-supply = <&vsys_3v3>;\n+\t\t\tldo1-in-supply = <&vsys_3v3>;\n+\t\t\tldo2-in-supply = <&vsys_3v3>;\n+\t\t\tldo3-in-supply = <&vsys_5v0>;\n+\t\t\tldo4-in-supply = <&vsys_5v0>;\n+\t\t\tldo5-in-supply = <&vsys_3v3>;\n+\n+\t\t\ttps65917_regulators: regulators {\n+\t\t\t\tsmps12_reg: smps12 {\n+\t\t\t\t\t/* VDD_DSPEVE */\n+\t\t\t\t\tregulator-name = \"smps12\";\n+\t\t\t\t\tregulator-min-microvolt = <850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps3_reg: smps3 {\n+\t\t\t\t\t/* VDD_CORE */\n+\t\t\t\t\tregulator-name = \"smps3\";\n+\t\t\t\t\tregulator-min-microvolt = <850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps4_reg: smps4 {\n+\t\t\t\t\t/* VDD_IVA */\n+\t\t\t\t\tregulator-name = \"smps4\";\n+\t\t\t\t\tregulator-min-microvolt = <850000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tsmps5_reg: smps5 {\n+\t\t\t\t\t/* VDDS1V8 */\n+\t\t\t\t\tregulator-name = \"smps5\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo1_reg: ldo1 {\n+\t\t\t\t\t/* LDO1_OUT --> VDA_PHY1_1V8  */\n+\t\t\t\t\tregulator-name = \"ldo1\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-allow-bypass;\n+\t\t\t\t};\n+\n+\t\t\t\tldo2_reg: ldo2 {\n+\t\t\t\t\t/* LDO2_OUT --> VDA_PHY2_1V8 */\n+\t\t\t\t\tregulator-name = \"ldo2\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-allow-bypass;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo3_reg: ldo3 {\n+\t\t\t\t\t/* VDA_USB_3V3 */\n+\t\t\t\t\tregulator-name = \"ldo3\";\n+\t\t\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo5_reg: ldo5 {\n+\t\t\t\t\t/* VDDA_1V8_PLL */\n+\t\t\t\t\tregulator-name = \"ldo5\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t};\n+\n+\t\t\t\tldo4_reg: ldo4 {\n+\t\t\t\t\t/* VDD_SDIO_DV */\n+\t\t\t\t\tregulator-name = \"ldo4\";\n+\t\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\t\tregulator-boot-on;\n+\t\t\t\t\tregulator-always-on;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttps65917_power_button {\n+\t\t\tcompatible = \"ti,palmas-pwrbutton\";\n+\t\t\tinterrupt-parent = <&tps65917>;\n+\t\t\tinterrupts = <1 IRQ_TYPE_NONE>;\n+\t\t\twakeup-source;\n+\t\t\tti,palmas-long-press-seconds = <6>;\n+\t\t};\n+\t};\n+\n+\tlp87565: lp87565@60 {\n+\t\tcompatible = \"ti,lp87565-q1\";\n+\t\treg = <0x60>;\n+\n+\t\tbuck10-in-supply =<&vsys_3v3>;\n+\t\tbuck23-in-supply =<&vsys_3v3>;\n+\n+\t\tregulators: regulators {\n+\t\t\tbuck10_reg: buck10 {\n+\t\t\t\t/*VDD_MPU*/\n+\t\t\t\tregulator-name = \"buck10\";\n+\t\t\t\tregulator-min-microvolt = <850000>;\n+\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t};\n+\n+\t\t\tbuck23_reg: buck23 {\n+\t\t\t\t/* VDD_GPU*/\n+\t\t\t\tregulator-name = \"buck23\";\n+\t\t\t\tregulator-min-microvolt = <850000>;\n+\t\t\t\tregulator-max-microvolt = <1250000>;\n+\t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpcf_lcd: pcf8757@20 {\n+\t\tcompatible = \"ti,pcf8575\", \"nxp,pcf8575\";\n+\t\treg = <0x20>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <3 IRQ_TYPE_EDGE_FALLING>;\n+\t};\n+\n+\tpcf_gpio_21: pcf8757@21 {\n+\t\tcompatible = \"ti,pcf8575\", \"nxp,pcf8575\";\n+\t\treg = <0x21>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <3 IRQ_TYPE_EDGE_FALLING>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t};\n+\n+\tpcf_hdmi: pcf8575@26 {\n+\t\tcompatible = \"ti,pcf8575\", \"nxp,pcf8575\";\n+\t\treg = <0x26>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tp1 {\n+\t\t\t/* vin6_sel_s0: high: VIN6, low: audio */\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-low;\n+\t\t\tline-name = \"vin6_sel_s0\";\n+\t\t};\n+\t};\n+\n+\ttlv320aic3106: tlv320aic3106@19 {\n+\t\t#sound-dai-cells = <0>;\n+\t\tcompatible = \"ti,tlv320aic3106\";\n+\t\treg = <0x19>;\n+\t\tadc-settle-ms = <40>;\n+\t\tai3x-micbias-vg = <1>;\t\t/* 2.0V */\n+\t\tstatus = \"okay\";\n+\n+\t\t/* Regulators */\n+\t\tAVDD-supply = <&vio_3v3>;\n+\t\tIOVDD-supply = <&vio_3v3>;\n+\t\tDRVDD-supply = <&vio_3v3>;\n+\t\tDVDD-supply = <&aic_dvdd>;\n+\t};\n+};\n+\n+&cpu0 {\n+\tvdd-supply = <&buck10_reg>;\n+};\n+\n+&mmc1 {\n+\tstatus = \"okay\";\n+\tvmmc-supply = <&vio_3v3_sd>;\n+\tvmmc_aux-supply = <&ldo4_reg>;\n+\tbus-width = <4>;\n+\t/*\n+\t * SDCD signal is not being used here - using the fact that GPIO mode\n+\t * is always hardwired.\n+\t */\n+\tcd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+};\n+\n+&mmc2 {\n+\tstatus = \"okay\";\n+\tvmmc-supply = <&vio_1v8>;\n+\tbus-width = <8>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc2_pins_default>;\n+};\n+\n+/* No RTC on this device */\n+&rtc {\n+\tstatus = \"disabled\";\n+};\n+\n+&mac {\n+\tstatus = \"okay\";\n+\n+\tdual_emac;\n+};\n+\n+&cpsw_emac0 {\n+\tphy_id = <&davinci_mdio>, <2>;\n+\tphy-mode = \"rgmii-id\";\n+\tdual_emac_res_vlan = <1>;\n+};\n+\n+&cpsw_emac1 {\n+\tphy_id = <&davinci_mdio>, <3>;\n+\tphy-mode = \"rgmii-id\";\n+\tdual_emac_res_vlan = <2>;\n+};\n+\n+&davinci_mdio {\n+\tdp83867_0: ethernet-phy@2 {\n+\t\treg = <2>;\n+\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;\n+\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n+\t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n+\t\tti,min-output-impedance;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n+\t};\n+\n+\tdp83867_1: ethernet-phy@3 {\n+\t\treg = <3>;\n+\t\tti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;\n+\t\tti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;\n+\t\tti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;\n+\t\tti,min-output-impedance;\n+\t\tti,dp83867-rxctrl-strap-quirk;\n+\t};\n+};\n+\n+&usb2_phy1 {\n+\tphy-supply = <&ldo3_reg>;\n+};\n+\n+&usb2_phy2 {\n+\tphy-supply = <&ldo3_reg>;\n+};\n+\n+&qspi {\n+\tspi-max-frequency = <96000000>;\n+\tm25p80@0 {\n+\t\tspi-max-frequency = <96000000>;\n+\t};\n+};\ndiff --git a/arch/arm/dts/dra76x.dtsi b/arch/arm/dts/dra76x.dtsi\nnew file mode 100644\nindex 0000000000..1c88c581ff\n--- /dev/null\n+++ b/arch/arm/dts/dra76x.dtsi\n@@ -0,0 +1,19 @@\n+/*\n+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include \"dra74x.dtsi\"\n+\n+/ {\n+\tcompatible = \"ti,dra762\", \"ti,dra7\";\n+\n+};\n+\n+/* MCAN interrupts are hard-wired to irqs 67, 68 */\n+&crossbar_mpu {\n+\tti,irqs-skip = <10 67 68 133 139 140>;\n+};\ndiff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi\nindex 3330738e4c..cf229dfabf 100644\n--- a/arch/arm/dts/dra7xx-clocks.dtsi\n+++ b/arch/arm/dts/dra7xx-clocks.dtsi\n@@ -338,6 +338,8 @@\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;\n \t\treg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;\n+\t\tassigned-clocks = <&dpll_dsp_ck>;\n+\t\tassigned-clock-rates = <600000000>;\n \t};\n \n \tdpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {\n@@ -349,6 +351,8 @@\n \t\treg = <0x0244>;\n \t\tti,index-starts-at-one;\n \t\tti,invert-autoidle-bit;\n+\t\tassigned-clocks = <&dpll_dsp_m2_ck>;\n+\t\tassigned-clock-rates = <600000000>;\n \t};\n \n \tiva_dpll_hs_clk_div: iva_dpll_hs_clk_div {\n@@ -372,6 +376,8 @@\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;\n \t\treg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;\n+\t\tassigned-clocks = <&dpll_iva_ck>;\n+\t\tassigned-clock-rates = <1165000000>;\n \t};\n \n \tdpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {\n@@ -383,6 +389,8 @@\n \t\treg = <0x01b0>;\n \t\tti,index-starts-at-one;\n \t\tti,invert-autoidle-bit;\n+\t\tassigned-clocks = <&dpll_iva_m2_ck>;\n+\t\tassigned-clock-rates = <388333334>;\n \t};\n \n \tiva_dclk: iva_dclk {\n@@ -406,6 +414,8 @@\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;\n \t\treg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;\n+\t\tassigned-clocks = <&dpll_gpu_ck>;\n+\t\tassigned-clock-rates = <1277000000>;\n \t};\n \n \tdpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {\n@@ -417,6 +427,8 @@\n \t\treg = <0x02e8>;\n \t\tti,index-starts-at-one;\n \t\tti,invert-autoidle-bit;\n+\t\tassigned-clocks = <&dpll_gpu_m2_ck>;\n+\t\tassigned-clock-rates = <425666667>;\n \t};\n \n \tdpll_core_m2_ck: dpll_core_m2_ck@130 {\n@@ -659,6 +671,8 @@\n \t\treg = <0x0248>;\n \t\tti,index-starts-at-one;\n \t\tti,invert-autoidle-bit;\n+\t\tassigned-clocks = <&dpll_dsp_m3x2_ck>;\n+\t\tassigned-clock-rates = <400000000>;\n \t};\n \n \tdpll_gmac_x2_ck: dpll_gmac_x2_ck {\n@@ -791,6 +805,8 @@\n \t\tclocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;\n \t\tti,bit-shift = <24>;\n \t\treg = <0x0520>;\n+\t\tassigned-clocks = <&ipu1_gfclk_mux>;\n+\t\tassigned-clock-parents = <&dpll_core_h22x2_ck>;\n \t};\n \n \tmcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {\n@@ -1748,6 +1764,8 @@\n \t\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;\n \t\tti,bit-shift = <24>;\n \t\treg = <0x1220>;\n+\t\tassigned-clocks = <&gpu_core_gclk_mux>;\n+\t\tassigned-clock-parents = <&dpll_gpu_m2_ck>;\n \t};\n \n \tgpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {\n@@ -1756,6 +1774,8 @@\n \t\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;\n \t\tti,bit-shift = <26>;\n \t\treg = <0x1220>;\n+\t\tassigned-clocks = <&gpu_hyd_gclk_mux>;\n+\t\tassigned-clock-parents = <&dpll_gpu_m2_ck>;\n \t};\n \n \tl3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {\ndiff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h\nindex 5c75e80915..18ec5df5a5 100644\n--- a/include/dt-bindings/pinctrl/dra.h\n+++ b/include/dt-bindings/pinctrl/dra.h\n@@ -73,5 +73,8 @@\n  */\n #define DRA7XX_CORE_IOPAD(pa, val)\t(((pa) & 0xffff) - 0x3400) (val)\n \n+/* DRA7 IODELAY configuration parameters */\n+#define A_DELAY_PS(val)\t\t\t((val) & 0xffff)\n+#define G_DELAY_PS(val)\t\t\t((val) & 0xffff)\n #endif\n \n",
    "prefixes": [
        "U-Boot",
        "v2",
        "11/13"
    ]
}